1 @c Copyright (C) 1991-2018 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
7 @chapter MIPS Dependent Features
10 @node Machine Dependencies
11 @chapter MIPS Dependent Features
14 @cindex MIPS processor
15 @sc{gnu} @code{@value{AS}} for MIPS architectures supports several
16 different MIPS processors, and MIPS ISA levels I through V, MIPS32,
17 and MIPS64. For information about the MIPS instruction set, see
18 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
19 For an overview of MIPS assembly conventions, see ``Appendix D:
20 Assembly Language Programming'' in the same work.
23 * MIPS Options:: Assembler options
24 * MIPS Macros:: High-level assembly macros
25 * MIPS Symbol Sizes:: Directives to override the size of symbols
26 * MIPS Small Data:: Controlling the use of small data accesses
27 * MIPS ISA:: Directives to override the ISA level
28 * MIPS assembly options:: Directives to control code generation
29 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
30 * MIPS insn:: Directive to mark data as an instruction
31 * MIPS FP ABIs:: Marking which FP ABI is in use
32 * MIPS NaN Encodings:: Directives to record which NaN encoding is being used
33 * MIPS Option Stack:: Directives to save and restore options
34 * MIPS ASE Instruction Generation Overrides:: Directives to control
35 generation of MIPS ASE instructions
36 * MIPS Floating-Point:: Directives to override floating-point options
37 * MIPS Syntax:: MIPS specific syntactical considerations
41 @section Assembler options
43 The MIPS configurations of @sc{gnu} @code{@value{AS}} support these
47 @cindex @code{-G} option (MIPS)
49 Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes.
50 @xref{MIPS Small Data,, Controlling the use of small data accesses}.
52 @cindex @code{-EB} option (MIPS)
53 @cindex @code{-EL} option (MIPS)
54 @cindex MIPS big-endian output
55 @cindex MIPS little-endian output
56 @cindex big-endian output, MIPS
57 @cindex little-endian output, MIPS
60 Any MIPS configuration of @code{@value{AS}} can select big-endian or
61 little-endian output at run time (unlike the other @sc{gnu} development
62 tools, which must be configured for one or the other). Use @samp{-EB}
63 to select big-endian output, and @samp{-EL} for little-endian.
66 @cindex PIC selection, MIPS
67 @cindex @option{-KPIC} option, MIPS
68 Generate SVR4-style PIC. This option tells the assembler to generate
69 SVR4-style position-independent macro expansions. It also tells the
70 assembler to mark the output file as PIC.
73 @cindex @option{-mvxworks-pic} option, MIPS
74 Generate VxWorks PIC. This option tells the assembler to generate
75 VxWorks-style position-independent macro expansions.
77 @cindex MIPS architecture options
93 Generate code for a particular MIPS Instruction Set Architecture level.
94 @samp{-mips1} corresponds to the R2000 and R3000 processors,
95 @samp{-mips2} to the R6000 processor, @samp{-mips3} to the
96 R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors.
97 @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3},
98 @samp{-mips32r5}, @samp{-mips32r6}, @samp{-mips64}, @samp{-mips64r2},
99 @samp{-mips64r3}, @samp{-mips64r5}, and @samp{-mips64r6} correspond to
100 generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32
101 Release 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64
102 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors,
103 respectively. You can also switch instruction sets during the assembly;
104 see @ref{MIPS ISA, Directives to override the ISA level}.
108 Some macros have different expansions for 32-bit and 64-bit registers.
109 The register sizes are normally inferred from the ISA and ABI, but these
110 flags force a certain group of registers to be treated as 32 bits wide at
111 all times. @samp{-mgp32} controls the size of general-purpose registers
112 and @samp{-mfp32} controls the size of floating-point registers.
114 The @code{.set gp=32} and @code{.set fp=32} directives allow the size
115 of registers to be changed for parts of an object. The default value is
116 restored by @code{.set gp=default} and @code{.set fp=default}.
118 On some MIPS variants there is a 32-bit mode flag; when this flag is
119 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
120 save the 32-bit registers on a context switch, so it is essential never
121 to use the 64-bit registers.
125 Assume that 64-bit registers are available. This is provided in the
126 interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
128 The @code{.set gp=64} and @code{.set fp=64} directives allow the size
129 of registers to be changed for parts of an object. The default value is
130 restored by @code{.set gp=default} and @code{.set fp=default}.
133 Make no assumptions about whether 32-bit or 64-bit floating-point
134 registers are available. This is provided to support having modules
135 compatible with either @samp{-mfp32} or @samp{-mfp64}. This option can
136 only be used with MIPS II and above.
138 The @code{.set fp=xx} directive allows a part of an object to be marked
139 as not making assumptions about 32-bit or 64-bit FP registers. The
140 default value is restored by @code{.set fp=default}.
143 @itemx -mno-odd-spreg
144 Enable use of floating-point operations on odd-numbered single-precision
145 registers when supported by the ISA. @samp{-mfpxx} implies
146 @samp{-mno-odd-spreg}, otherwise the default is @samp{-modd-spreg}
150 Generate code for the MIPS 16 processor. This is equivalent to putting
151 @code{.module mips16} at the start of the assembly file. @samp{-no-mips16}
152 turns off this option.
156 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent
157 to putting @code{.module mips16e2} at the start of the assembly file.
158 @samp{-mno-mips16e2} turns off this option.
161 @itemx -mno-micromips
162 Generate code for the microMIPS processor. This is equivalent to putting
163 @code{.module micromips} at the start of the assembly file.
164 @samp{-mno-micromips} turns off this option. This is equivalent to putting
165 @code{.module nomicromips} at the start of the assembly file.
168 @itemx -mno-smartmips
169 Enables the SmartMIPS extensions to the MIPS32 instruction set, which
170 provides a number of new instructions which target smartcard and
171 cryptographic applications. This is equivalent to putting
172 @code{.module smartmips} at the start of the assembly file.
173 @samp{-mno-smartmips} turns off this option.
177 Generate code for the MIPS-3D Application Specific Extension.
178 This tells the assembler to accept MIPS-3D instructions.
179 @samp{-no-mips3d} turns off this option.
183 Generate code for the MDMX Application Specific Extension.
184 This tells the assembler to accept MDMX instructions.
185 @samp{-no-mdmx} turns off this option.
189 Generate code for the DSP Release 1 Application Specific Extension.
190 This tells the assembler to accept DSP Release 1 instructions.
191 @samp{-mno-dsp} turns off this option.
195 Generate code for the DSP Release 2 Application Specific Extension.
196 This option implies @samp{-mdsp}.
197 This tells the assembler to accept DSP Release 2 instructions.
198 @samp{-mno-dspr2} turns off this option.
202 Generate code for the DSP Release 3 Application Specific Extension.
203 This option implies @samp{-mdsp} and @samp{-mdspr2}.
204 This tells the assembler to accept DSP Release 3 instructions.
205 @samp{-mno-dspr3} turns off this option.
209 Generate code for the MT Application Specific Extension.
210 This tells the assembler to accept MT instructions.
211 @samp{-mno-mt} turns off this option.
215 Generate code for the MCU Application Specific Extension.
216 This tells the assembler to accept MCU instructions.
217 @samp{-mno-mcu} turns off this option.
221 Generate code for the MIPS SIMD Architecture Extension.
222 This tells the assembler to accept MSA instructions.
223 @samp{-mno-msa} turns off this option.
227 Generate code for the MIPS eXtended Physical Address (XPA) Extension.
228 This tells the assembler to accept XPA instructions.
229 @samp{-mno-xpa} turns off this option.
233 Generate code for the Virtualization Application Specific Extension.
234 This tells the assembler to accept Virtualization instructions.
235 @samp{-mno-virt} turns off this option.
239 Generate code for the cyclic redundancy check (CRC) Application Specific
240 Extension. This tells the assembler to accept CRC instructions.
241 @samp{-mno-crc} turns off this option.
245 Generate code for the Global INValidate (GINV) Application Specific
246 Extension. This tells the assembler to accept GINV instructions.
247 @samp{-mno-ginv} turns off this option.
250 @itemx -mno-loongson-mmi
251 Generate code for the Loongson MultiMedia extensions Instructions (MMI)
252 Application Specific Extension. This tells the assembler to accept MMI
254 @samp{-mno-loongson-mmi} turns off this option.
257 @itemx -mno-loongson-cam
258 Generate code for the Loongson Content Address Memory (CAM)
259 Application Specific Extension. This tells the assembler to accept CAM
261 @samp{-mno-loongson-cam} turns off this option.
264 @itemx -mno-loongson-ext
265 Generate code for the Loongson EXTensions (EXT) instructions
266 Application Specific Extension. This tells the assembler to accept EXT
268 @samp{-mno-loongson-ext} turns off this option.
272 Only use 32-bit instruction encodings when generating code for the
273 microMIPS processor. This option inhibits the use of any 16-bit
274 instructions. This is equivalent to putting @code{.set insn32} at
275 the start of the assembly file. @samp{-mno-insn32} turns off this
276 option. This is equivalent to putting @code{.set noinsn32} at the
277 start of the assembly file. By default @samp{-mno-insn32} is
278 selected, allowing all instructions to be used.
282 Cause nops to be inserted if the read of the destination register
283 of an mfhi or mflo instruction occurs in the following two instructions.
286 @itemx -mno-fix-rm7000
287 Cause nops to be inserted if a dmult or dmultu instruction is
288 followed by a load instruction.
290 @item -mfix-loongson2f-jump
291 @itemx -mno-fix-loongson2f-jump
292 Eliminate instruction fetch from outside 256M region to work around the
293 Loongson2F @samp{jump} instructions. Without it, under extreme cases,
294 the kernel may crash. The issue has been solved in latest processor
295 batches, but this fix has no side effect to them.
297 @item -mfix-loongson2f-nop
298 @itemx -mno-fix-loongson2f-nop
299 Replace nops by @code{or at,at,zero} to work around the Loongson2F
300 @samp{nop} errata. Without it, under extreme cases, the CPU might
301 deadlock. The issue has been solved in later Loongson2F batches, but
302 this fix has no side effect to them.
305 @itemx -mno-fix-vr4120
306 Insert nops to work around certain VR4120 errata. This option is
307 intended to be used on GCC-generated code: it is not designed to catch
308 all problems in hand-written assembler code.
311 @itemx -mno-fix-vr4130
312 Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
316 Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
319 @itemx -mno-fix-cn63xxp1
320 Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around
321 certain CN63XXP1 errata.
325 Generate code for the LSI R4010 chip. This tells the assembler to
326 accept the R4010-specific instructions (@samp{addciu}, @samp{ffc},
327 etc.), and to not schedule @samp{nop} instructions around accesses to
328 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
333 Generate code for the MIPS R4650 chip. This tells the assembler to accept
334 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
335 instructions around accesses to the @samp{HI} and @samp{LO} registers.
336 @samp{-no-m4650} turns off this option.
342 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
343 R@var{nnnn} chip. This tells the assembler to accept instructions
344 specific to that chip, and to schedule for that chip's hazards.
346 @item -march=@var{cpu}
347 Generate code for a particular MIPS CPU. It is exactly equivalent to
348 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
349 understood. Valid @var{cpu} value are:
442 For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
443 accepted as synonyms for @samp{@var{n}f1_1}. These values are
446 @item -mtune=@var{cpu}
447 Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are
448 identical to @samp{-march=@var{cpu}}.
450 @item -mabi=@var{abi}
451 Record which ABI the source code uses. The recognized arguments
452 are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
458 Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
459 the beginning of the assembler input. @xref{MIPS Symbol Sizes}.
461 @cindex @code{-nocpp} ignored (MIPS)
463 This option is ignored. It is accepted for command-line compatibility with
464 other assemblers, which use it to turn off C style preprocessing. With
465 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
466 @sc{gnu} assembler itself never runs the C preprocessor.
470 Disable or enable floating-point instructions. Note that by default
471 floating-point instructions are always allowed even with CPU targets
472 that don't have support for these instructions.
475 @itemx -mdouble-float
476 Disable or enable double-precision floating-point operations. Note
477 that by default double-precision floating-point operations are always
478 allowed even with CPU targets that don't have support for these
481 @item --construct-floats
482 @itemx --no-construct-floats
483 The @code{--no-construct-floats} option disables the construction of
484 double width floating point constants by loading the two halves of the
485 value into the two single width floating point registers that make up
486 the double width register. This feature is useful if the processor
487 support the FR bit in its status register, and this bit is known (by
488 the programmer) to be set. This bit prevents the aliasing of the double
489 width register by the single width registers.
491 By default @code{--construct-floats} is selected, allowing construction
492 of these floating point constants.
495 @itemx --no-relax-branch
496 The @samp{--relax-branch} option enables the relaxation of out-of-range
497 branches. Any branches whose target cannot be reached directly are
498 converted to a small instruction sequence including an inverse-condition
499 branch to the physically next instruction, and a jump to the original
500 target is inserted between the two instructions. In PIC code the jump
501 will involve further instructions for address calculation.
503 The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T},
504 @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from
505 relaxation, because they have no complementing counterparts. They could
506 be relaxed with the use of a longer sequence involving another branch,
507 however this has not been implemented and if their target turns out of
508 reach, they produce an error even if branch relaxation is enabled.
510 Also no MIPS16 branches are ever relaxed.
512 By default @samp{--no-relax-branch} is selected, causing any out-of-range
513 branches to produce an error.
515 @item -mignore-branch-isa
516 @itemx -mno-ignore-branch-isa
517 Ignore branch checks for invalid transitions between ISA modes.
519 The semantics of branches does not provide for an ISA mode switch, so in
520 most cases the ISA mode a branch has been encoded for has to be the same
521 as the ISA mode of the branch's target label. If the ISA modes do not
522 match, then such a branch, if taken, will cause the ISA mode to remain
523 unchanged and instructions that follow will be executed in the wrong ISA
524 mode causing the program to misbehave or crash.
526 In the case of the @code{BAL} instruction it may be possible to relax
527 it to an equivalent @code{JALX} instruction so that the ISA mode is
528 switched at the run time as required. For other branches no relaxation
529 is possible and therefore GAS has checks implemented that verify in
530 branch assembly that the two ISA modes match, and report an error
531 otherwise so that the problem with code can be diagnosed at the assembly
532 time rather than at the run time.
534 However some assembly code, including generated code produced by some
535 versions of GCC, may incorrectly include branches to data labels, which
536 appear to require a mode switch but are either dead or immediately
537 followed by valid instructions encoded for the same ISA the branch has
538 been encoded for. While not strictly correct at the source level such
539 code will execute as intended, so to help with these cases
540 @samp{-mignore-branch-isa} is supported which disables ISA mode checks
543 By default @samp{-mno-ignore-branch-isa} is selected, causing any invalid
544 branch requiring a transition between ISA modes to produce an error.
546 @cindex @option{-mnan=} command-line option, MIPS
547 @item -mnan=@var{encoding}
548 This option indicates whether the source code uses the IEEE 2008
549 NaN encoding (@option{-mnan=2008}) or the original MIPS encoding
550 (@option{-mnan=legacy}). It is equivalent to adding a @code{.nan}
551 directive to the beginning of the source file. @xref{MIPS NaN Encodings}.
553 @option{-mnan=legacy} is the default if no @option{-mnan} option or
554 @code{.nan} directive is used.
558 @c FIXME! (1) reflect these options (next item too) in option summaries;
559 @c (2) stop teasing, say _which_ instructions expanded _how_.
560 @code{@value{AS}} automatically macro expands certain division and
561 multiplication instructions to check for overflow and division by zero. This
562 option causes @code{@value{AS}} to generate code to take a trap exception
563 rather than a break exception when an error is detected. The trap instructions
564 are only supported at Instruction Set Architecture level 2 and higher.
568 Generate code to take a break exception rather than a trap exception when an
569 error is detected. This is the default.
573 Control generation of @code{.pdr} sections. Off by default on IRIX, on
578 When generating code using the Unix calling conventions (selected by
579 @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
580 which can go into a shared library. The @samp{-mno-shared} option
581 tells gas to generate code which uses the calling convention, but can
582 not go into a shared library. The resulting code is slightly more
583 efficient. This option only affects the handling of the
584 @samp{.cpload} and @samp{.cpsetup} pseudo-ops.
588 @section High-level assembly macros
590 MIPS assemblers have traditionally provided a wider range of
591 instructions than the MIPS architecture itself. These extra
592 instructions are usually referred to as ``macro'' instructions
593 @footnote{The term ``macro'' is somewhat overloaded here, since
594 these macros have no relation to those defined by @code{.macro},
595 @pxref{Macro,, @code{.macro}}.}.
597 Some MIPS macro instructions extend an underlying architectural instruction
598 while others are entirely new. An example of the former type is @code{and},
599 which allows the third operand to be either a register or an arbitrary
600 immediate value. Examples of the latter type include @code{bgt}, which
601 branches to the third operand when the first operand is greater than
602 the second operand, and @code{ulh}, which implements an unaligned
605 One of the most common extensions provided by macros is to expand
606 memory offsets to the full address range (32 or 64 bits) and to allow
607 symbolic offsets such as @samp{my_data + 4} to be used in place of
608 integer constants. For example, the architectural instruction
609 @code{lbu} allows only a signed 16-bit offset, whereas the macro
610 @code{lbu} allows code such as @samp{lbu $4,array+32769($5)}.
611 The implementation of these symbolic offsets depends on several factors,
612 such as whether the assembler is generating SVR4-style PIC (selected by
613 @option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols
614 (@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}),
615 and the small data limit (@pxref{MIPS Small Data,, Controlling the use
616 of small data accesses}).
618 @kindex @code{.set macro}
619 @kindex @code{.set nomacro}
620 Sometimes it is undesirable to have one assembly instruction expand
621 to several machine instructions. The directive @code{.set nomacro}
622 tells the assembler to warn when this happens. @code{.set macro}
623 restores the default behavior.
625 @cindex @code{at} register, MIPS
626 @kindex @code{.set at=@var{reg}}
627 Some macro instructions need a temporary register to store intermediate
628 results. This register is usually @code{$1}, also known as @code{$at},
629 but it can be changed to any core register @var{reg} using
630 @code{.set at=@var{reg}}. Note that @code{$at} always refers
631 to @code{$1} regardless of which register is being used as the
634 @kindex @code{.set at}
635 @kindex @code{.set noat}
636 Implicit uses of the temporary register in macros could interfere with
637 explicit uses in the assembly code. The assembler therefore warns
638 whenever it sees an explicit use of the temporary register. The directive
639 @code{.set noat} silences this warning while @code{.set at} restores
640 the default behavior. It is safe to use @code{.set noat} while
641 @code{.set nomacro} is in effect since single-instruction macros
642 never need a temporary register.
644 Note that while the @sc{gnu} assembler provides these macros for compatibility,
645 it does not make any attempt to optimize them with the surrounding code.
647 @node MIPS Symbol Sizes
648 @section Directives to override the size of symbols
650 @kindex @code{.set sym32}
651 @kindex @code{.set nosym32}
652 The n64 ABI allows symbols to have any 64-bit value. Although this
653 provides a great deal of flexibility, it means that some macros have
654 much longer expansions than their 32-bit counterparts. For example,
655 the non-PIC expansion of @samp{dla $4,sym} is usually:
660 daddiu $4,$4,%higher(sym)
661 daddiu $1,$1,%lo(sym)
666 whereas the 32-bit expansion is simply:
670 daddiu $4,$4,%lo(sym)
673 n64 code is sometimes constructed in such a way that all symbolic
674 constants are known to have 32-bit values, and in such cases, it's
675 preferable to use the 32-bit expansion instead of the 64-bit
678 You can use the @code{.set sym32} directive to tell the assembler
679 that, from this point on, all expressions of the form
680 @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
681 have 32-bit values. For example:
690 will cause the assembler to treat @samp{sym}, @code{sym+16} and
691 @code{sym+0x8000} as 32-bit values. The handling of non-symbolic
692 addresses is not affected.
694 The directive @code{.set nosym32} ends a @code{.set sym32} block and
695 reverts to the normal behavior. It is also possible to change the
696 symbol size using the command-line options @option{-msym32} and
699 These options and directives are always accepted, but at present,
700 they have no effect for anything other than n64.
702 @node MIPS Small Data
703 @section Controlling the use of small data accesses
705 @c This section deliberately glosses over the possibility of using -G
706 @c in SVR4-style PIC, as could be done on IRIX. We don't support that.
707 @cindex small data, MIPS
708 @cindex @code{gp} register, MIPS
709 It often takes several instructions to load the address of a symbol.
710 For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion
711 of @samp{dla $4,addr} is usually:
715 daddiu $4,$4,%lo(addr)
718 The sequence is much longer when @samp{addr} is a 64-bit symbol.
719 @xref{MIPS Symbol Sizes,, Directives to override the size of symbols}.
721 In order to cut down on this overhead, most embedded MIPS systems
722 set aside a 64-kilobyte ``small data'' area and guarantee that all
723 data of size @var{n} and smaller will be placed in that area.
724 The limit @var{n} is passed to both the assembler and the linker
725 using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,,
726 Assembler options}. Note that the same value of @var{n} must be used
727 when linking and when assembling all input files to the link; any
728 inconsistency could cause a relocation overflow error.
730 The size of an object in the @code{.bss} section is set by the
731 @code{.comm} or @code{.lcomm} directive that defines it. The size of
732 an external object may be set with the @code{.extern} directive. For
733 example, @samp{.extern sym,4} declares that the object at @code{sym}
734 is 4 bytes in length, while leaving @code{sym} otherwise undefined.
736 When no @option{-G} option is given, the default limit is 8 bytes.
737 The option @option{-G 0} prevents any data from being automatically
740 It is also possible to mark specific objects as small by putting them
741 in the special sections @code{.sdata} and @code{.sbss}, which are
742 ``small'' counterparts of @code{.data} and @code{.bss} respectively.
743 The toolchain will treat such data as small regardless of the
746 On startup, systems that support a small data area are expected to
747 initialize register @code{$28}, also known as @code{$gp}, in such a
748 way that small data can be accessed using a 16-bit offset from that
749 register. For example, when @samp{addr} is small data,
750 the @samp{dla $4,addr} instruction above is equivalent to:
753 daddiu $4,$28,%gp_rel(addr)
756 Small data is not supported for SVR4-style PIC.
759 @section Directives to override the ISA level
761 @cindex MIPS ISA override
762 @kindex @code{.set mips@var{n}}
763 @sc{gnu} @code{@value{AS}} supports an additional directive to change
764 the MIPS Instruction Set Architecture level on the fly: @code{.set
765 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 32r3,
766 32r5, 32r6, 64, 64r2, 64r3, 64r5 or 64r6.
767 The values other than 0 make the assembler accept instructions
768 for the corresponding ISA level, from that point on in the
769 assembly. @code{.set mips@var{n}} affects not only which instructions
770 are permitted, but also how certain macros are expanded. @code{.set
771 mips0} restores the ISA level to its original level: either the
772 level you selected with command-line options, or the default for your
773 configuration. You can use this feature to permit specific MIPS III
774 instructions while assembling in 32 bit mode. Use this directive with
777 @cindex MIPS CPU override
778 @kindex @code{.set arch=@var{cpu}}
779 The @code{.set arch=@var{cpu}} directive provides even finer control.
780 It changes the effective CPU target and allows the assembler to use
781 instructions specific to a particular CPU. All CPUs supported by the
782 @samp{-march} command-line option are also selectable by this directive.
783 The original value is restored by @code{.set arch=default}.
785 The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
786 in which it will assemble instructions for the MIPS 16 processor. Use
787 @code{.set nomips16} to return to normal 32 bit mode.
789 Traditional MIPS assemblers do not support this directive.
791 The directive @code{.set micromips} puts the assembler into microMIPS mode,
792 in which it will assemble instructions for the microMIPS processor. Use
793 @code{.set nomicromips} to return to normal 32 bit mode.
795 Traditional MIPS assemblers do not support this directive.
797 @node MIPS assembly options
798 @section Directives to control code generation
800 @cindex MIPS directives to override command-line options
801 @kindex @code{.module}
802 The @code{.module} directive allows command-line options to be set directly
803 from assembly. The format of the directive matches the @code{.set}
804 directive but only those options which are relevant to a whole module are
805 supported. The effect of a @code{.module} directive is the same as the
806 corresponding command-line option. Where @code{.set} directives support
807 returning to a default then the @code{.module} directives do not as they
810 These module-level directives must appear first in assembly.
812 Traditional MIPS assemblers do not support this directive.
814 @cindex MIPS 32-bit microMIPS instruction generation override
815 @kindex @code{.set insn32}
816 @kindex @code{.set noinsn32}
817 The directive @code{.set insn32} makes the assembler only use 32-bit
818 instruction encodings when generating code for the microMIPS processor.
819 This directive inhibits the use of any 16-bit instructions from that
820 point on in the assembly. The @code{.set noinsn32} directive allows
821 16-bit instructions to be accepted.
823 Traditional MIPS assemblers do not support this directive.
825 @node MIPS autoextend
826 @section Directives for extending MIPS 16 bit instructions
828 @kindex @code{.set autoextend}
829 @kindex @code{.set noautoextend}
830 By default, MIPS 16 instructions are automatically extended to 32 bits
831 when necessary. The directive @code{.set noautoextend} will turn this
832 off. When @code{.set noautoextend} is in effect, any 32 bit instruction
833 must be explicitly extended with the @code{.e} modifier (e.g.,
834 @code{li.e $4,1000}). The directive @code{.set autoextend} may be used
835 to once again automatically extend instructions when necessary.
837 This directive is only meaningful when in MIPS 16 mode. Traditional
838 MIPS assemblers do not support this directive.
841 @section Directive to mark data as an instruction
844 The @code{.insn} directive tells @code{@value{AS}} that the following
845 data is actually instructions. This makes a difference in MIPS 16 and
846 microMIPS modes: when loading the address of a label which precedes
847 instructions, @code{@value{AS}} automatically adds 1 to the value, so
848 that jumping to the loaded address will do the right thing.
850 @kindex @code{.global}
851 The @code{.global} and @code{.globl} directives supported by
852 @code{@value{AS}} will by default mark the symbol as pointing to a
853 region of data not code. This means that, for example, any
854 instructions following such a symbol will not be disassembled by
855 @code{objdump} as it will regard them as data. To change this
856 behavior an optional section name can be placed after the symbol name
857 in the @code{.global} directive. If this section exists and is known
858 to be a code section, then the symbol will be marked as pointing at
859 code not data. Ie the syntax for the directive is:
861 @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
863 Here is a short example:
866 .global foo .text, bar, baz .data
877 @section Directives to control the FP ABI
879 * MIPS FP ABI History:: History of FP ABIs
880 * MIPS FP ABI Variants:: Supported FP ABIs
881 * MIPS FP ABI Selection:: Automatic selection of FP ABI
882 * MIPS FP ABI Compatibility:: Linking different FP ABI variants
885 @node MIPS FP ABI History
886 @subsection History of FP ABIs
887 @cindex @code{.gnu_attribute 4, @var{n}} directive, MIPS
888 @cindex @code{.gnu_attribute Tag_GNU_MIPS_ABI_FP, @var{n}} directive, MIPS
889 The MIPS ABIs support a variety of different floating-point extensions
890 where calling-convention and register sizes vary for floating-point data.
891 The extensions exist to support a wide variety of optional architecture
892 features. The resulting ABI variants are generally incompatible with each
893 other and must be tracked carefully.
895 Traditionally the use of an explicit @code{.gnu_attribute 4, @var{n}}
896 directive is used to indicate which ABI is in use by a specific module.
897 It was then left to the user to ensure that command-line options and the
898 selected ABI were compatible with some potential for inconsistencies.
900 @node MIPS FP ABI Variants
901 @subsection Supported FP ABIs
902 The supported floating-point ABI variants are:
905 @item 0 - No floating-point
906 This variant is used to indicate that floating-point is not used within
907 the module at all and therefore has no impact on the ABI. This is the
910 @item 1 - Double-precision
911 This variant indicates that double-precision support is used. For 64-bit
912 ABIs this means that 64-bit wide floating-point registers are required.
913 For 32-bit ABIs this means that 32-bit wide floating-point registers are
914 required and double-precision operations use pairs of registers.
916 @item 2 - Single-precision
917 This variant indicates that single-precision support is used. Double
918 precision operations will be supported via soft-float routines.
921 This variant indicates that although floating-point support is used all
922 operations are emulated in software. This means the ABI is modified to
923 pass all floating-point data in general-purpose registers.
926 This variant existed as an initial attempt at supporting 64-bit wide
927 floating-point registers for O32 ABI on a MIPS32r2 CPU. This has been
928 superseded by 5, 6 and 7.
930 @item 5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU
931 This variant is used by 32-bit ABIs to indicate that the floating-point
932 code in the module has been designed to operate correctly with either
933 32-bit wide or 64-bit wide floating-point registers. Double-precision
934 support is used. Only O32 currently supports this variant and requires
935 a minimum architecture of MIPS II.
937 @item 6 - Double-precision 32-bit FPU, 64-bit FPU
938 This variant is used by 32-bit ABIs to indicate that the floating-point
939 code in the module requires 64-bit wide floating-point registers.
940 Double-precision support is used. Only O32 currently supports this
941 variant and requires a minimum architecture of MIPS32r2.
943 @item 7 - Double-precision compat 32-bit FPU, 64-bit FPU
944 This variant is used by 32-bit ABIs to indicate that the floating-point
945 code in the module requires 64-bit wide floating-point registers.
946 Double-precision support is used. This differs from the previous ABI
947 as it restricts use of odd-numbered single-precision registers. Only
948 O32 currently supports this variant and requires a minimum architecture
952 @node MIPS FP ABI Selection
953 @subsection Automatic selection of FP ABI
954 @cindex @code{.module fp=@var{nn}} directive, MIPS
955 In order to simplify and add safety to the process of selecting the
956 correct floating-point ABI, the assembler will automatically infer the
957 correct @code{.gnu_attribute 4, @var{n}} directive based on command-line
958 options and @code{.module} overrides. Where an explicit
959 @code{.gnu_attribute 4, @var{n}} directive has been seen then a warning
960 will be raised if it does not match an inferred setting.
962 The floating-point ABI is inferred as follows. If @samp{-msoft-float}
963 has been used the module will be marked as soft-float. If
964 @samp{-msingle-float} has been used then the module will be marked as
965 single-precision. The remaining ABIs are then selected based
966 on the FP register width. Double-precision is selected if the width
967 of GP and FP registers match and the special double-precision variants
968 for 32-bit ABIs are then selected depending on @samp{-mfpxx},
969 @samp{-mfp64} and @samp{-mno-odd-spreg}.
971 @node MIPS FP ABI Compatibility
972 @subsection Linking different FP ABI variants
973 Modules using the default FP ABI (no floating-point) can be linked with
974 any other (singular) FP ABI variant.
976 Special compatibility support exists for O32 with the four
977 double-precision FP ABI variants. The @samp{-mfpxx} FP ABI is specifically
978 designed to be compatible with the standard double-precision ABI and the
979 @samp{-mfp64} FP ABIs. This makes it desirable for O32 modules to be
980 built as @samp{-mfpxx} to ensure the maximum compatibility with other
981 modules produced for more specific needs. The only FP ABIs which cannot
982 be linked together are the standard double-precision ABI and the full
983 @samp{-mfp64} ABI with @samp{-modd-spreg}.
985 @node MIPS NaN Encodings
986 @section Directives to record which NaN encoding is being used
988 @cindex MIPS IEEE 754 NaN data encoding selection
989 @cindex @code{.nan} directive, MIPS
990 The IEEE 754 floating-point standard defines two types of not-a-number
991 (NaN) data: ``signalling'' NaNs and ``quiet'' NaNs. The original version
992 of the standard did not specify how these two types should be
993 distinguished. Most implementations followed the i387 model, in which
994 the first bit of the significand is set for quiet NaNs and clear for
995 signalling NaNs. However, the original MIPS implementation assigned the
996 opposite meaning to the bit, so that it was set for signalling NaNs and
997 clear for quiet NaNs.
999 The 2008 revision of the standard formally suggested the i387 choice
1000 and as from Sep 2012 the current release of the MIPS architecture
1001 therefore optionally supports that form. Code that uses one NaN encoding
1002 would usually be incompatible with code that uses the other NaN encoding,
1003 so MIPS ELF objects have a flag (@code{EF_MIPS_NAN2008}) to record which
1004 encoding is being used.
1006 Assembly files can use the @code{.nan} directive to select between the
1007 two encodings. @samp{.nan 2008} says that the assembly file uses the
1008 IEEE 754-2008 encoding while @samp{.nan legacy} says that the file uses
1009 the original MIPS encoding. If several @code{.nan} directives are given,
1010 the final setting is the one that is used.
1012 The command-line options @option{-mnan=legacy} and @option{-mnan=2008}
1013 can be used instead of @samp{.nan legacy} and @samp{.nan 2008}
1014 respectively. However, any @code{.nan} directive overrides the
1015 command-line setting.
1017 @samp{.nan legacy} is the default if no @code{.nan} directive or
1018 @option{-mnan} option is given.
1020 Note that @sc{gnu} @code{@value{AS}} does not produce NaNs itself and
1021 therefore these directives do not affect code generation. They simply
1022 control the setting of the @code{EF_MIPS_NAN2008} flag.
1024 Traditional MIPS assemblers do not support these directives.
1026 @node MIPS Option Stack
1027 @section Directives to save and restore options
1029 @cindex MIPS option stack
1030 @kindex @code{.set push}
1031 @kindex @code{.set pop}
1032 The directives @code{.set push} and @code{.set pop} may be used to save
1033 and restore the current settings for all the options which are
1034 controlled by @code{.set}. The @code{.set push} directive saves the
1035 current settings on a stack. The @code{.set pop} directive pops the
1036 stack and restores the settings.
1038 These directives can be useful inside an macro which must change an
1039 option such as the ISA level or instruction reordering but does not want
1040 to change the state of the code which invoked the macro.
1042 Traditional MIPS assemblers do not support these directives.
1044 @node MIPS ASE Instruction Generation Overrides
1045 @section Directives to control generation of MIPS ASE instructions
1047 @cindex MIPS MIPS-3D instruction generation override
1048 @kindex @code{.set mips3d}
1049 @kindex @code{.set nomips3d}
1050 The directive @code{.set mips3d} makes the assembler accept instructions
1051 from the MIPS-3D Application Specific Extension from that point on
1052 in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
1053 instructions from being accepted.
1055 @cindex SmartMIPS instruction generation override
1056 @kindex @code{.set smartmips}
1057 @kindex @code{.set nosmartmips}
1058 The directive @code{.set smartmips} makes the assembler accept
1059 instructions from the SmartMIPS Application Specific Extension to the
1060 MIPS32 ISA from that point on in the assembly. The
1061 @code{.set nosmartmips} directive prevents SmartMIPS instructions from
1064 @cindex MIPS MDMX instruction generation override
1065 @kindex @code{.set mdmx}
1066 @kindex @code{.set nomdmx}
1067 The directive @code{.set mdmx} makes the assembler accept instructions
1068 from the MDMX Application Specific Extension from that point on
1069 in the assembly. The @code{.set nomdmx} directive prevents MDMX
1070 instructions from being accepted.
1072 @cindex MIPS DSP Release 1 instruction generation override
1073 @kindex @code{.set dsp}
1074 @kindex @code{.set nodsp}
1075 The directive @code{.set dsp} makes the assembler accept instructions
1076 from the DSP Release 1 Application Specific Extension from that point
1077 on in the assembly. The @code{.set nodsp} directive prevents DSP
1078 Release 1 instructions from being accepted.
1080 @cindex MIPS DSP Release 2 instruction generation override
1081 @kindex @code{.set dspr2}
1082 @kindex @code{.set nodspr2}
1083 The directive @code{.set dspr2} makes the assembler accept instructions
1084 from the DSP Release 2 Application Specific Extension from that point
1085 on in the assembly. This directive implies @code{.set dsp}. The
1086 @code{.set nodspr2} directive prevents DSP Release 2 instructions from
1089 @cindex MIPS DSP Release 3 instruction generation override
1090 @kindex @code{.set dspr3}
1091 @kindex @code{.set nodspr3}
1092 The directive @code{.set dspr3} makes the assembler accept instructions
1093 from the DSP Release 3 Application Specific Extension from that point
1094 on in the assembly. This directive implies @code{.set dsp} and
1095 @code{.set dspr2}. The @code{.set nodspr3} directive prevents DSP
1096 Release 3 instructions from being accepted.
1098 @cindex MIPS MT instruction generation override
1099 @kindex @code{.set mt}
1100 @kindex @code{.set nomt}
1101 The directive @code{.set mt} makes the assembler accept instructions
1102 from the MT Application Specific Extension from that point on
1103 in the assembly. The @code{.set nomt} directive prevents MT
1104 instructions from being accepted.
1106 @cindex MIPS MCU instruction generation override
1107 @kindex @code{.set mcu}
1108 @kindex @code{.set nomcu}
1109 The directive @code{.set mcu} makes the assembler accept instructions
1110 from the MCU Application Specific Extension from that point on
1111 in the assembly. The @code{.set nomcu} directive prevents MCU
1112 instructions from being accepted.
1114 @cindex MIPS SIMD Architecture instruction generation override
1115 @kindex @code{.set msa}
1116 @kindex @code{.set nomsa}
1117 The directive @code{.set msa} makes the assembler accept instructions
1118 from the MIPS SIMD Architecture Extension from that point on
1119 in the assembly. The @code{.set nomsa} directive prevents MSA
1120 instructions from being accepted.
1122 @cindex Virtualization instruction generation override
1123 @kindex @code{.set virt}
1124 @kindex @code{.set novirt}
1125 The directive @code{.set virt} makes the assembler accept instructions
1126 from the Virtualization Application Specific Extension from that point
1127 on in the assembly. The @code{.set novirt} directive prevents Virtualization
1128 instructions from being accepted.
1130 @cindex MIPS eXtended Physical Address (XPA) instruction generation override
1131 @kindex @code{.set xpa}
1132 @kindex @code{.set noxpa}
1133 The directive @code{.set xpa} makes the assembler accept instructions
1134 from the XPA Extension from that point on in the assembly. The
1135 @code{.set noxpa} directive prevents XPA instructions from being accepted.
1137 @cindex MIPS16e2 instruction generation override
1138 @kindex @code{.set mips16e2}
1139 @kindex @code{.set nomips16e2}
1140 The directive @code{.set mips16e2} makes the assembler accept instructions
1141 from the MIPS16e2 Application Specific Extension from that point on in the
1142 assembly, whenever in MIPS16 mode. The @code{.set nomips16e2} directive
1143 prevents MIPS16e2 instructions from being accepted, in MIPS16 mode. Neither
1144 directive affects the state of MIPS16 mode being active itself which has
1147 @cindex MIPS cyclic redundancy check (CRC) instruction generation override
1148 @kindex @code{.set crc}
1149 @kindex @code{.set nocrc}
1150 The directive @code{.set crc} makes the assembler accept instructions
1151 from the CRC Extension from that point on in the assembly. The
1152 @code{.set nocrc} directive prevents CRC instructions from being accepted.
1154 @cindex MIPS Global INValidate (GINV) instruction generation override
1155 @kindex @code{.set ginv}
1156 @kindex @code{.set noginv}
1157 The directive @code{.set ginv} makes the assembler accept instructions
1158 from the GINV Extension from that point on in the assembly. The
1159 @code{.set noginv} directive prevents GINV instructions from being accepted.
1161 @cindex Loongson MultiMedia extensions Instructions (MMI) generation override
1162 @kindex @code{.set loongson-mmi}
1163 @kindex @code{.set noloongson-mmi}
1164 The directive @code{.set loongson-mmi} makes the assembler accept
1165 instructions from the MMI Extension from that point on in the assembly.
1166 The @code{.set noloongson-mmi} directive prevents MMI instructions from
1169 @cindex Loongson Content Address Memory (CAM) generation override
1170 @kindex @code{.set loongson-cam}
1171 @kindex @code{.set noloongson-cam}
1172 The directive @code{.set loongson-cam} makes the assembler accept
1173 instructions from the Loongson CAM from that point on in the assembly.
1174 The @code{.set noloongson-cam} directive prevents Loongson CAM instructions
1175 from being accepted.
1177 @cindex Loongson EXTensions (EXT) instructions generation override
1178 @kindex @code{.set loongson-ext}
1179 @kindex @code{.set noloongson-ext}
1180 The directive @code{.set loongson-ext} makes the assembler accept
1181 instructions from the Loongson EXT from that point on in the assembly.
1182 The @code{.set noloongson-ext} directive prevents Loongson EXT instructions
1183 from being accepted.
1185 Traditional MIPS assemblers do not support these directives.
1187 @node MIPS Floating-Point
1188 @section Directives to override floating-point options
1190 @cindex Disable floating-point instructions
1191 @kindex @code{.set softfloat}
1192 @kindex @code{.set hardfloat}
1193 The directives @code{.set softfloat} and @code{.set hardfloat} provide
1194 finer control of disabling and enabling float-point instructions.
1195 These directives always override the default (that hard-float
1196 instructions are accepted) or the command-line options
1197 (@samp{-msoft-float} and @samp{-mhard-float}).
1199 @cindex Disable single-precision floating-point operations
1200 @kindex @code{.set singlefloat}
1201 @kindex @code{.set doublefloat}
1202 The directives @code{.set singlefloat} and @code{.set doublefloat}
1203 provide finer control of disabling and enabling double-precision
1204 float-point operations. These directives always override the default
1205 (that double-precision operations are accepted) or the command-line
1206 options (@samp{-msingle-float} and @samp{-mdouble-float}).
1208 Traditional MIPS assemblers do not support these directives.
1211 @section Syntactical considerations for the MIPS assembler
1213 * MIPS-Chars:: Special Characters
1217 @subsection Special Characters
1219 @cindex line comment character, MIPS
1220 @cindex MIPS line comment character
1221 The presence of a @samp{#} on a line indicates the start of a comment
1222 that extends to the end of the current line.
1224 If a @samp{#} appears as the first character of a line, the whole line
1225 is treated as a comment, but in this case the line can also be a
1226 logical line number directive (@pxref{Comments}) or a
1227 preprocessor control command (@pxref{Preprocessing}).
1229 @cindex line separator, MIPS
1230 @cindex statement separator, MIPS
1231 @cindex MIPS line separator
1232 The @samp{;} character can be used to separate statements on the same
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