1 @c Copyright (C) 1991-2018 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
7 @chapter MIPS Dependent Features
10 @node Machine Dependencies
11 @chapter MIPS Dependent Features
14 @cindex MIPS processor
15 @sc{gnu} @code{@value{AS}} for MIPS architectures supports several
16 different MIPS processors, and MIPS ISA levels I through V, MIPS32,
17 and MIPS64. For information about the MIPS instruction set, see
18 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
19 For an overview of MIPS assembly conventions, see ``Appendix D:
20 Assembly Language Programming'' in the same work.
23 * MIPS Options:: Assembler options
24 * MIPS Macros:: High-level assembly macros
25 * MIPS Symbol Sizes:: Directives to override the size of symbols
26 * MIPS Small Data:: Controlling the use of small data accesses
27 * MIPS ISA:: Directives to override the ISA level
28 * MIPS assembly options:: Directives to control code generation
29 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
30 * MIPS insn:: Directive to mark data as an instruction
31 * MIPS FP ABIs:: Marking which FP ABI is in use
32 * MIPS NaN Encodings:: Directives to record which NaN encoding is being used
33 * MIPS Option Stack:: Directives to save and restore options
34 * MIPS ASE Instruction Generation Overrides:: Directives to control
35 generation of MIPS ASE instructions
36 * MIPS Floating-Point:: Directives to override floating-point options
37 * MIPS Syntax:: MIPS specific syntactical considerations
41 @section Assembler options
43 The MIPS configurations of @sc{gnu} @code{@value{AS}} support these
47 @cindex @code{-G} option (MIPS)
49 Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes.
50 @xref{MIPS Small Data,, Controlling the use of small data accesses}.
52 @cindex @code{-EB} option (MIPS)
53 @cindex @code{-EL} option (MIPS)
54 @cindex MIPS big-endian output
55 @cindex MIPS little-endian output
56 @cindex big-endian output, MIPS
57 @cindex little-endian output, MIPS
60 Any MIPS configuration of @code{@value{AS}} can select big-endian or
61 little-endian output at run time (unlike the other @sc{gnu} development
62 tools, which must be configured for one or the other). Use @samp{-EB}
63 to select big-endian output, and @samp{-EL} for little-endian.
66 @cindex PIC selection, MIPS
67 @cindex @option{-KPIC} option, MIPS
68 Generate SVR4-style PIC. This option tells the assembler to generate
69 SVR4-style position-independent macro expansions. It also tells the
70 assembler to mark the output file as PIC.
73 @cindex @option{-mvxworks-pic} option, MIPS
74 Generate VxWorks PIC. This option tells the assembler to generate
75 VxWorks-style position-independent macro expansions.
77 @cindex MIPS architecture options
93 Generate code for a particular MIPS Instruction Set Architecture level.
94 @samp{-mips1} corresponds to the R2000 and R3000 processors,
95 @samp{-mips2} to the R6000 processor, @samp{-mips3} to the
96 R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors.
97 @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3},
98 @samp{-mips32r5}, @samp{-mips32r6}, @samp{-mips64}, @samp{-mips64r2},
99 @samp{-mips64r3}, @samp{-mips64r5}, and @samp{-mips64r6} correspond to
100 generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32
101 Release 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64
102 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors,
103 respectively. You can also switch instruction sets during the assembly;
104 see @ref{MIPS ISA, Directives to override the ISA level}.
108 Some macros have different expansions for 32-bit and 64-bit registers.
109 The register sizes are normally inferred from the ISA and ABI, but these
110 flags force a certain group of registers to be treated as 32 bits wide at
111 all times. @samp{-mgp32} controls the size of general-purpose registers
112 and @samp{-mfp32} controls the size of floating-point registers.
114 The @code{.set gp=32} and @code{.set fp=32} directives allow the size
115 of registers to be changed for parts of an object. The default value is
116 restored by @code{.set gp=default} and @code{.set fp=default}.
118 On some MIPS variants there is a 32-bit mode flag; when this flag is
119 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
120 save the 32-bit registers on a context switch, so it is essential never
121 to use the 64-bit registers.
125 Assume that 64-bit registers are available. This is provided in the
126 interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
128 The @code{.set gp=64} and @code{.set fp=64} directives allow the size
129 of registers to be changed for parts of an object. The default value is
130 restored by @code{.set gp=default} and @code{.set fp=default}.
133 Make no assumptions about whether 32-bit or 64-bit floating-point
134 registers are available. This is provided to support having modules
135 compatible with either @samp{-mfp32} or @samp{-mfp64}. This option can
136 only be used with MIPS II and above.
138 The @code{.set fp=xx} directive allows a part of an object to be marked
139 as not making assumptions about 32-bit or 64-bit FP registers. The
140 default value is restored by @code{.set fp=default}.
143 @itemx -mno-odd-spreg
144 Enable use of floating-point operations on odd-numbered single-precision
145 registers when supported by the ISA. @samp{-mfpxx} implies
146 @samp{-mno-odd-spreg}, otherwise the default is @samp{-modd-spreg}
150 Generate code for the MIPS 16 processor. This is equivalent to putting
151 @code{.module mips16} at the start of the assembly file. @samp{-no-mips16}
152 turns off this option.
156 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent
157 to putting @code{.module mips16e2} at the start of the assembly file.
158 @samp{-mno-mips16e2} turns off this option.
161 @itemx -mno-micromips
162 Generate code for the microMIPS processor. This is equivalent to putting
163 @code{.module micromips} at the start of the assembly file.
164 @samp{-mno-micromips} turns off this option. This is equivalent to putting
165 @code{.module nomicromips} at the start of the assembly file.
168 @itemx -mno-smartmips
169 Enables the SmartMIPS extensions to the MIPS32 instruction set, which
170 provides a number of new instructions which target smartcard and
171 cryptographic applications. This is equivalent to putting
172 @code{.module smartmips} at the start of the assembly file.
173 @samp{-mno-smartmips} turns off this option.
177 Generate code for the MIPS-3D Application Specific Extension.
178 This tells the assembler to accept MIPS-3D instructions.
179 @samp{-no-mips3d} turns off this option.
183 Generate code for the MDMX Application Specific Extension.
184 This tells the assembler to accept MDMX instructions.
185 @samp{-no-mdmx} turns off this option.
189 Generate code for the DSP Release 1 Application Specific Extension.
190 This tells the assembler to accept DSP Release 1 instructions.
191 @samp{-mno-dsp} turns off this option.
195 Generate code for the DSP Release 2 Application Specific Extension.
196 This option implies @samp{-mdsp}.
197 This tells the assembler to accept DSP Release 2 instructions.
198 @samp{-mno-dspr2} turns off this option.
202 Generate code for the DSP Release 3 Application Specific Extension.
203 This option implies @samp{-mdsp} and @samp{-mdspr2}.
204 This tells the assembler to accept DSP Release 3 instructions.
205 @samp{-mno-dspr3} turns off this option.
209 Generate code for the MT Application Specific Extension.
210 This tells the assembler to accept MT instructions.
211 @samp{-mno-mt} turns off this option.
215 Generate code for the MCU Application Specific Extension.
216 This tells the assembler to accept MCU instructions.
217 @samp{-mno-mcu} turns off this option.
221 Generate code for the MIPS SIMD Architecture Extension.
222 This tells the assembler to accept MSA instructions.
223 @samp{-mno-msa} turns off this option.
227 Generate code for the MIPS eXtended Physical Address (XPA) Extension.
228 This tells the assembler to accept XPA instructions.
229 @samp{-mno-xpa} turns off this option.
233 Generate code for the Virtualization Application Specific Extension.
234 This tells the assembler to accept Virtualization instructions.
235 @samp{-mno-virt} turns off this option.
239 Generate code for the cyclic redundancy check (CRC) Application Specific
240 Extension. This tells the assembler to accept CRC instructions.
241 @samp{-mno-crc} turns off this option.
245 Generate code for the Global INValidate (GINV) Application Specific
246 Extension. This tells the assembler to accept GINV instructions.
247 @samp{-mno-ginv} turns off this option.
250 @itemx -mno-loongson-mmi
251 Generate code for the Loongson MultiMedia extensions Instructions (MMI)
252 Application Specific Extension. This tells the assembler to accept MMI
254 @samp{-mno-loongson-mmi} turns off this option.
257 @itemx -mno-loongson-cam
258 Generate code for the Loongson Content Address Memory (CAM)
259 Application Specific Extension. This tells the assembler to accept CAM
261 @samp{-mno-loongson-cam} turns off this option.
264 @itemx -mno-loongson-ext
265 Generate code for the Loongson EXTensions (EXT) instructions
266 Application Specific Extension. This tells the assembler to accept EXT
268 @samp{-mno-loongson-ext} turns off this option.
270 @item -mloongson-ext2
271 @itemx -mno-loongson-ext2
272 Generate code for the Loongson EXTensions R2 (EXT2) instructions
273 Application Specific Extension. This tells the assembler to accept EXT2
275 @samp{-mno-loongson-ext2} turns off this option.
279 Only use 32-bit instruction encodings when generating code for the
280 microMIPS processor. This option inhibits the use of any 16-bit
281 instructions. This is equivalent to putting @code{.set insn32} at
282 the start of the assembly file. @samp{-mno-insn32} turns off this
283 option. This is equivalent to putting @code{.set noinsn32} at the
284 start of the assembly file. By default @samp{-mno-insn32} is
285 selected, allowing all instructions to be used.
289 Cause nops to be inserted if the read of the destination register
290 of an mfhi or mflo instruction occurs in the following two instructions.
293 @itemx -mno-fix-rm7000
294 Cause nops to be inserted if a dmult or dmultu instruction is
295 followed by a load instruction.
297 @item -mfix-loongson2f-jump
298 @itemx -mno-fix-loongson2f-jump
299 Eliminate instruction fetch from outside 256M region to work around the
300 Loongson2F @samp{jump} instructions. Without it, under extreme cases,
301 the kernel may crash. The issue has been solved in latest processor
302 batches, but this fix has no side effect to them.
304 @item -mfix-loongson2f-nop
305 @itemx -mno-fix-loongson2f-nop
306 Replace nops by @code{or at,at,zero} to work around the Loongson2F
307 @samp{nop} errata. Without it, under extreme cases, the CPU might
308 deadlock. The issue has been solved in later Loongson2F batches, but
309 this fix has no side effect to them.
312 @itemx -mno-fix-vr4120
313 Insert nops to work around certain VR4120 errata. This option is
314 intended to be used on GCC-generated code: it is not designed to catch
315 all problems in hand-written assembler code.
318 @itemx -mno-fix-vr4130
319 Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
323 Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
326 @itemx -mno-fix-cn63xxp1
327 Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around
328 certain CN63XXP1 errata.
332 Generate code for the LSI R4010 chip. This tells the assembler to
333 accept the R4010-specific instructions (@samp{addciu}, @samp{ffc},
334 etc.), and to not schedule @samp{nop} instructions around accesses to
335 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
340 Generate code for the MIPS R4650 chip. This tells the assembler to accept
341 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
342 instructions around accesses to the @samp{HI} and @samp{LO} registers.
343 @samp{-no-m4650} turns off this option.
349 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
350 R@var{nnnn} chip. This tells the assembler to accept instructions
351 specific to that chip, and to schedule for that chip's hazards.
353 @item -march=@var{cpu}
354 Generate code for a particular MIPS CPU. It is exactly equivalent to
355 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
356 understood. Valid @var{cpu} value are:
449 For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
450 accepted as synonyms for @samp{@var{n}f1_1}. These values are
453 @item -mtune=@var{cpu}
454 Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are
455 identical to @samp{-march=@var{cpu}}.
457 @item -mabi=@var{abi}
458 Record which ABI the source code uses. The recognized arguments
459 are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
465 Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
466 the beginning of the assembler input. @xref{MIPS Symbol Sizes}.
468 @cindex @code{-nocpp} ignored (MIPS)
470 This option is ignored. It is accepted for command-line compatibility with
471 other assemblers, which use it to turn off C style preprocessing. With
472 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
473 @sc{gnu} assembler itself never runs the C preprocessor.
477 Disable or enable floating-point instructions. Note that by default
478 floating-point instructions are always allowed even with CPU targets
479 that don't have support for these instructions.
482 @itemx -mdouble-float
483 Disable or enable double-precision floating-point operations. Note
484 that by default double-precision floating-point operations are always
485 allowed even with CPU targets that don't have support for these
488 @item --construct-floats
489 @itemx --no-construct-floats
490 The @code{--no-construct-floats} option disables the construction of
491 double width floating point constants by loading the two halves of the
492 value into the two single width floating point registers that make up
493 the double width register. This feature is useful if the processor
494 support the FR bit in its status register, and this bit is known (by
495 the programmer) to be set. This bit prevents the aliasing of the double
496 width register by the single width registers.
498 By default @code{--construct-floats} is selected, allowing construction
499 of these floating point constants.
502 @itemx --no-relax-branch
503 The @samp{--relax-branch} option enables the relaxation of out-of-range
504 branches. Any branches whose target cannot be reached directly are
505 converted to a small instruction sequence including an inverse-condition
506 branch to the physically next instruction, and a jump to the original
507 target is inserted between the two instructions. In PIC code the jump
508 will involve further instructions for address calculation.
510 The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T},
511 @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from
512 relaxation, because they have no complementing counterparts. They could
513 be relaxed with the use of a longer sequence involving another branch,
514 however this has not been implemented and if their target turns out of
515 reach, they produce an error even if branch relaxation is enabled.
517 Also no MIPS16 branches are ever relaxed.
519 By default @samp{--no-relax-branch} is selected, causing any out-of-range
520 branches to produce an error.
522 @item -mignore-branch-isa
523 @itemx -mno-ignore-branch-isa
524 Ignore branch checks for invalid transitions between ISA modes.
526 The semantics of branches does not provide for an ISA mode switch, so in
527 most cases the ISA mode a branch has been encoded for has to be the same
528 as the ISA mode of the branch's target label. If the ISA modes do not
529 match, then such a branch, if taken, will cause the ISA mode to remain
530 unchanged and instructions that follow will be executed in the wrong ISA
531 mode causing the program to misbehave or crash.
533 In the case of the @code{BAL} instruction it may be possible to relax
534 it to an equivalent @code{JALX} instruction so that the ISA mode is
535 switched at the run time as required. For other branches no relaxation
536 is possible and therefore GAS has checks implemented that verify in
537 branch assembly that the two ISA modes match, and report an error
538 otherwise so that the problem with code can be diagnosed at the assembly
539 time rather than at the run time.
541 However some assembly code, including generated code produced by some
542 versions of GCC, may incorrectly include branches to data labels, which
543 appear to require a mode switch but are either dead or immediately
544 followed by valid instructions encoded for the same ISA the branch has
545 been encoded for. While not strictly correct at the source level such
546 code will execute as intended, so to help with these cases
547 @samp{-mignore-branch-isa} is supported which disables ISA mode checks
550 By default @samp{-mno-ignore-branch-isa} is selected, causing any invalid
551 branch requiring a transition between ISA modes to produce an error.
553 @cindex @option{-mnan=} command-line option, MIPS
554 @item -mnan=@var{encoding}
555 This option indicates whether the source code uses the IEEE 2008
556 NaN encoding (@option{-mnan=2008}) or the original MIPS encoding
557 (@option{-mnan=legacy}). It is equivalent to adding a @code{.nan}
558 directive to the beginning of the source file. @xref{MIPS NaN Encodings}.
560 @option{-mnan=legacy} is the default if no @option{-mnan} option or
561 @code{.nan} directive is used.
565 @c FIXME! (1) reflect these options (next item too) in option summaries;
566 @c (2) stop teasing, say _which_ instructions expanded _how_.
567 @code{@value{AS}} automatically macro expands certain division and
568 multiplication instructions to check for overflow and division by zero. This
569 option causes @code{@value{AS}} to generate code to take a trap exception
570 rather than a break exception when an error is detected. The trap instructions
571 are only supported at Instruction Set Architecture level 2 and higher.
575 Generate code to take a break exception rather than a trap exception when an
576 error is detected. This is the default.
580 Control generation of @code{.pdr} sections. Off by default on IRIX, on
585 When generating code using the Unix calling conventions (selected by
586 @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
587 which can go into a shared library. The @samp{-mno-shared} option
588 tells gas to generate code which uses the calling convention, but can
589 not go into a shared library. The resulting code is slightly more
590 efficient. This option only affects the handling of the
591 @samp{.cpload} and @samp{.cpsetup} pseudo-ops.
595 @section High-level assembly macros
597 MIPS assemblers have traditionally provided a wider range of
598 instructions than the MIPS architecture itself. These extra
599 instructions are usually referred to as ``macro'' instructions
600 @footnote{The term ``macro'' is somewhat overloaded here, since
601 these macros have no relation to those defined by @code{.macro},
602 @pxref{Macro,, @code{.macro}}.}.
604 Some MIPS macro instructions extend an underlying architectural instruction
605 while others are entirely new. An example of the former type is @code{and},
606 which allows the third operand to be either a register or an arbitrary
607 immediate value. Examples of the latter type include @code{bgt}, which
608 branches to the third operand when the first operand is greater than
609 the second operand, and @code{ulh}, which implements an unaligned
612 One of the most common extensions provided by macros is to expand
613 memory offsets to the full address range (32 or 64 bits) and to allow
614 symbolic offsets such as @samp{my_data + 4} to be used in place of
615 integer constants. For example, the architectural instruction
616 @code{lbu} allows only a signed 16-bit offset, whereas the macro
617 @code{lbu} allows code such as @samp{lbu $4,array+32769($5)}.
618 The implementation of these symbolic offsets depends on several factors,
619 such as whether the assembler is generating SVR4-style PIC (selected by
620 @option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols
621 (@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}),
622 and the small data limit (@pxref{MIPS Small Data,, Controlling the use
623 of small data accesses}).
625 @kindex @code{.set macro}
626 @kindex @code{.set nomacro}
627 Sometimes it is undesirable to have one assembly instruction expand
628 to several machine instructions. The directive @code{.set nomacro}
629 tells the assembler to warn when this happens. @code{.set macro}
630 restores the default behavior.
632 @cindex @code{at} register, MIPS
633 @kindex @code{.set at=@var{reg}}
634 Some macro instructions need a temporary register to store intermediate
635 results. This register is usually @code{$1}, also known as @code{$at},
636 but it can be changed to any core register @var{reg} using
637 @code{.set at=@var{reg}}. Note that @code{$at} always refers
638 to @code{$1} regardless of which register is being used as the
641 @kindex @code{.set at}
642 @kindex @code{.set noat}
643 Implicit uses of the temporary register in macros could interfere with
644 explicit uses in the assembly code. The assembler therefore warns
645 whenever it sees an explicit use of the temporary register. The directive
646 @code{.set noat} silences this warning while @code{.set at} restores
647 the default behavior. It is safe to use @code{.set noat} while
648 @code{.set nomacro} is in effect since single-instruction macros
649 never need a temporary register.
651 Note that while the @sc{gnu} assembler provides these macros for compatibility,
652 it does not make any attempt to optimize them with the surrounding code.
654 @node MIPS Symbol Sizes
655 @section Directives to override the size of symbols
657 @kindex @code{.set sym32}
658 @kindex @code{.set nosym32}
659 The n64 ABI allows symbols to have any 64-bit value. Although this
660 provides a great deal of flexibility, it means that some macros have
661 much longer expansions than their 32-bit counterparts. For example,
662 the non-PIC expansion of @samp{dla $4,sym} is usually:
667 daddiu $4,$4,%higher(sym)
668 daddiu $1,$1,%lo(sym)
673 whereas the 32-bit expansion is simply:
677 daddiu $4,$4,%lo(sym)
680 n64 code is sometimes constructed in such a way that all symbolic
681 constants are known to have 32-bit values, and in such cases, it's
682 preferable to use the 32-bit expansion instead of the 64-bit
685 You can use the @code{.set sym32} directive to tell the assembler
686 that, from this point on, all expressions of the form
687 @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
688 have 32-bit values. For example:
697 will cause the assembler to treat @samp{sym}, @code{sym+16} and
698 @code{sym+0x8000} as 32-bit values. The handling of non-symbolic
699 addresses is not affected.
701 The directive @code{.set nosym32} ends a @code{.set sym32} block and
702 reverts to the normal behavior. It is also possible to change the
703 symbol size using the command-line options @option{-msym32} and
706 These options and directives are always accepted, but at present,
707 they have no effect for anything other than n64.
709 @node MIPS Small Data
710 @section Controlling the use of small data accesses
712 @c This section deliberately glosses over the possibility of using -G
713 @c in SVR4-style PIC, as could be done on IRIX. We don't support that.
714 @cindex small data, MIPS
715 @cindex @code{gp} register, MIPS
716 It often takes several instructions to load the address of a symbol.
717 For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion
718 of @samp{dla $4,addr} is usually:
722 daddiu $4,$4,%lo(addr)
725 The sequence is much longer when @samp{addr} is a 64-bit symbol.
726 @xref{MIPS Symbol Sizes,, Directives to override the size of symbols}.
728 In order to cut down on this overhead, most embedded MIPS systems
729 set aside a 64-kilobyte ``small data'' area and guarantee that all
730 data of size @var{n} and smaller will be placed in that area.
731 The limit @var{n} is passed to both the assembler and the linker
732 using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,,
733 Assembler options}. Note that the same value of @var{n} must be used
734 when linking and when assembling all input files to the link; any
735 inconsistency could cause a relocation overflow error.
737 The size of an object in the @code{.bss} section is set by the
738 @code{.comm} or @code{.lcomm} directive that defines it. The size of
739 an external object may be set with the @code{.extern} directive. For
740 example, @samp{.extern sym,4} declares that the object at @code{sym}
741 is 4 bytes in length, while leaving @code{sym} otherwise undefined.
743 When no @option{-G} option is given, the default limit is 8 bytes.
744 The option @option{-G 0} prevents any data from being automatically
747 It is also possible to mark specific objects as small by putting them
748 in the special sections @code{.sdata} and @code{.sbss}, which are
749 ``small'' counterparts of @code{.data} and @code{.bss} respectively.
750 The toolchain will treat such data as small regardless of the
753 On startup, systems that support a small data area are expected to
754 initialize register @code{$28}, also known as @code{$gp}, in such a
755 way that small data can be accessed using a 16-bit offset from that
756 register. For example, when @samp{addr} is small data,
757 the @samp{dla $4,addr} instruction above is equivalent to:
760 daddiu $4,$28,%gp_rel(addr)
763 Small data is not supported for SVR4-style PIC.
766 @section Directives to override the ISA level
768 @cindex MIPS ISA override
769 @kindex @code{.set mips@var{n}}
770 @sc{gnu} @code{@value{AS}} supports an additional directive to change
771 the MIPS Instruction Set Architecture level on the fly: @code{.set
772 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 32r3,
773 32r5, 32r6, 64, 64r2, 64r3, 64r5 or 64r6.
774 The values other than 0 make the assembler accept instructions
775 for the corresponding ISA level, from that point on in the
776 assembly. @code{.set mips@var{n}} affects not only which instructions
777 are permitted, but also how certain macros are expanded. @code{.set
778 mips0} restores the ISA level to its original level: either the
779 level you selected with command-line options, or the default for your
780 configuration. You can use this feature to permit specific MIPS III
781 instructions while assembling in 32 bit mode. Use this directive with
784 @cindex MIPS CPU override
785 @kindex @code{.set arch=@var{cpu}}
786 The @code{.set arch=@var{cpu}} directive provides even finer control.
787 It changes the effective CPU target and allows the assembler to use
788 instructions specific to a particular CPU. All CPUs supported by the
789 @samp{-march} command-line option are also selectable by this directive.
790 The original value is restored by @code{.set arch=default}.
792 The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
793 in which it will assemble instructions for the MIPS 16 processor. Use
794 @code{.set nomips16} to return to normal 32 bit mode.
796 Traditional MIPS assemblers do not support this directive.
798 The directive @code{.set micromips} puts the assembler into microMIPS mode,
799 in which it will assemble instructions for the microMIPS processor. Use
800 @code{.set nomicromips} to return to normal 32 bit mode.
802 Traditional MIPS assemblers do not support this directive.
804 @node MIPS assembly options
805 @section Directives to control code generation
807 @cindex MIPS directives to override command-line options
808 @kindex @code{.module}
809 The @code{.module} directive allows command-line options to be set directly
810 from assembly. The format of the directive matches the @code{.set}
811 directive but only those options which are relevant to a whole module are
812 supported. The effect of a @code{.module} directive is the same as the
813 corresponding command-line option. Where @code{.set} directives support
814 returning to a default then the @code{.module} directives do not as they
817 These module-level directives must appear first in assembly.
819 Traditional MIPS assemblers do not support this directive.
821 @cindex MIPS 32-bit microMIPS instruction generation override
822 @kindex @code{.set insn32}
823 @kindex @code{.set noinsn32}
824 The directive @code{.set insn32} makes the assembler only use 32-bit
825 instruction encodings when generating code for the microMIPS processor.
826 This directive inhibits the use of any 16-bit instructions from that
827 point on in the assembly. The @code{.set noinsn32} directive allows
828 16-bit instructions to be accepted.
830 Traditional MIPS assemblers do not support this directive.
832 @node MIPS autoextend
833 @section Directives for extending MIPS 16 bit instructions
835 @kindex @code{.set autoextend}
836 @kindex @code{.set noautoextend}
837 By default, MIPS 16 instructions are automatically extended to 32 bits
838 when necessary. The directive @code{.set noautoextend} will turn this
839 off. When @code{.set noautoextend} is in effect, any 32 bit instruction
840 must be explicitly extended with the @code{.e} modifier (e.g.,
841 @code{li.e $4,1000}). The directive @code{.set autoextend} may be used
842 to once again automatically extend instructions when necessary.
844 This directive is only meaningful when in MIPS 16 mode. Traditional
845 MIPS assemblers do not support this directive.
848 @section Directive to mark data as an instruction
851 The @code{.insn} directive tells @code{@value{AS}} that the following
852 data is actually instructions. This makes a difference in MIPS 16 and
853 microMIPS modes: when loading the address of a label which precedes
854 instructions, @code{@value{AS}} automatically adds 1 to the value, so
855 that jumping to the loaded address will do the right thing.
857 @kindex @code{.global}
858 The @code{.global} and @code{.globl} directives supported by
859 @code{@value{AS}} will by default mark the symbol as pointing to a
860 region of data not code. This means that, for example, any
861 instructions following such a symbol will not be disassembled by
862 @code{objdump} as it will regard them as data. To change this
863 behavior an optional section name can be placed after the symbol name
864 in the @code{.global} directive. If this section exists and is known
865 to be a code section, then the symbol will be marked as pointing at
866 code not data. Ie the syntax for the directive is:
868 @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
870 Here is a short example:
873 .global foo .text, bar, baz .data
884 @section Directives to control the FP ABI
886 * MIPS FP ABI History:: History of FP ABIs
887 * MIPS FP ABI Variants:: Supported FP ABIs
888 * MIPS FP ABI Selection:: Automatic selection of FP ABI
889 * MIPS FP ABI Compatibility:: Linking different FP ABI variants
892 @node MIPS FP ABI History
893 @subsection History of FP ABIs
894 @cindex @code{.gnu_attribute 4, @var{n}} directive, MIPS
895 @cindex @code{.gnu_attribute Tag_GNU_MIPS_ABI_FP, @var{n}} directive, MIPS
896 The MIPS ABIs support a variety of different floating-point extensions
897 where calling-convention and register sizes vary for floating-point data.
898 The extensions exist to support a wide variety of optional architecture
899 features. The resulting ABI variants are generally incompatible with each
900 other and must be tracked carefully.
902 Traditionally the use of an explicit @code{.gnu_attribute 4, @var{n}}
903 directive is used to indicate which ABI is in use by a specific module.
904 It was then left to the user to ensure that command-line options and the
905 selected ABI were compatible with some potential for inconsistencies.
907 @node MIPS FP ABI Variants
908 @subsection Supported FP ABIs
909 The supported floating-point ABI variants are:
912 @item 0 - No floating-point
913 This variant is used to indicate that floating-point is not used within
914 the module at all and therefore has no impact on the ABI. This is the
917 @item 1 - Double-precision
918 This variant indicates that double-precision support is used. For 64-bit
919 ABIs this means that 64-bit wide floating-point registers are required.
920 For 32-bit ABIs this means that 32-bit wide floating-point registers are
921 required and double-precision operations use pairs of registers.
923 @item 2 - Single-precision
924 This variant indicates that single-precision support is used. Double
925 precision operations will be supported via soft-float routines.
928 This variant indicates that although floating-point support is used all
929 operations are emulated in software. This means the ABI is modified to
930 pass all floating-point data in general-purpose registers.
933 This variant existed as an initial attempt at supporting 64-bit wide
934 floating-point registers for O32 ABI on a MIPS32r2 CPU. This has been
935 superseded by 5, 6 and 7.
937 @item 5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU
938 This variant is used by 32-bit ABIs to indicate that the floating-point
939 code in the module has been designed to operate correctly with either
940 32-bit wide or 64-bit wide floating-point registers. Double-precision
941 support is used. Only O32 currently supports this variant and requires
942 a minimum architecture of MIPS II.
944 @item 6 - Double-precision 32-bit FPU, 64-bit FPU
945 This variant is used by 32-bit ABIs to indicate that the floating-point
946 code in the module requires 64-bit wide floating-point registers.
947 Double-precision support is used. Only O32 currently supports this
948 variant and requires a minimum architecture of MIPS32r2.
950 @item 7 - Double-precision compat 32-bit FPU, 64-bit FPU
951 This variant is used by 32-bit ABIs to indicate that the floating-point
952 code in the module requires 64-bit wide floating-point registers.
953 Double-precision support is used. This differs from the previous ABI
954 as it restricts use of odd-numbered single-precision registers. Only
955 O32 currently supports this variant and requires a minimum architecture
959 @node MIPS FP ABI Selection
960 @subsection Automatic selection of FP ABI
961 @cindex @code{.module fp=@var{nn}} directive, MIPS
962 In order to simplify and add safety to the process of selecting the
963 correct floating-point ABI, the assembler will automatically infer the
964 correct @code{.gnu_attribute 4, @var{n}} directive based on command-line
965 options and @code{.module} overrides. Where an explicit
966 @code{.gnu_attribute 4, @var{n}} directive has been seen then a warning
967 will be raised if it does not match an inferred setting.
969 The floating-point ABI is inferred as follows. If @samp{-msoft-float}
970 has been used the module will be marked as soft-float. If
971 @samp{-msingle-float} has been used then the module will be marked as
972 single-precision. The remaining ABIs are then selected based
973 on the FP register width. Double-precision is selected if the width
974 of GP and FP registers match and the special double-precision variants
975 for 32-bit ABIs are then selected depending on @samp{-mfpxx},
976 @samp{-mfp64} and @samp{-mno-odd-spreg}.
978 @node MIPS FP ABI Compatibility
979 @subsection Linking different FP ABI variants
980 Modules using the default FP ABI (no floating-point) can be linked with
981 any other (singular) FP ABI variant.
983 Special compatibility support exists for O32 with the four
984 double-precision FP ABI variants. The @samp{-mfpxx} FP ABI is specifically
985 designed to be compatible with the standard double-precision ABI and the
986 @samp{-mfp64} FP ABIs. This makes it desirable for O32 modules to be
987 built as @samp{-mfpxx} to ensure the maximum compatibility with other
988 modules produced for more specific needs. The only FP ABIs which cannot
989 be linked together are the standard double-precision ABI and the full
990 @samp{-mfp64} ABI with @samp{-modd-spreg}.
992 @node MIPS NaN Encodings
993 @section Directives to record which NaN encoding is being used
995 @cindex MIPS IEEE 754 NaN data encoding selection
996 @cindex @code{.nan} directive, MIPS
997 The IEEE 754 floating-point standard defines two types of not-a-number
998 (NaN) data: ``signalling'' NaNs and ``quiet'' NaNs. The original version
999 of the standard did not specify how these two types should be
1000 distinguished. Most implementations followed the i387 model, in which
1001 the first bit of the significand is set for quiet NaNs and clear for
1002 signalling NaNs. However, the original MIPS implementation assigned the
1003 opposite meaning to the bit, so that it was set for signalling NaNs and
1004 clear for quiet NaNs.
1006 The 2008 revision of the standard formally suggested the i387 choice
1007 and as from Sep 2012 the current release of the MIPS architecture
1008 therefore optionally supports that form. Code that uses one NaN encoding
1009 would usually be incompatible with code that uses the other NaN encoding,
1010 so MIPS ELF objects have a flag (@code{EF_MIPS_NAN2008}) to record which
1011 encoding is being used.
1013 Assembly files can use the @code{.nan} directive to select between the
1014 two encodings. @samp{.nan 2008} says that the assembly file uses the
1015 IEEE 754-2008 encoding while @samp{.nan legacy} says that the file uses
1016 the original MIPS encoding. If several @code{.nan} directives are given,
1017 the final setting is the one that is used.
1019 The command-line options @option{-mnan=legacy} and @option{-mnan=2008}
1020 can be used instead of @samp{.nan legacy} and @samp{.nan 2008}
1021 respectively. However, any @code{.nan} directive overrides the
1022 command-line setting.
1024 @samp{.nan legacy} is the default if no @code{.nan} directive or
1025 @option{-mnan} option is given.
1027 Note that @sc{gnu} @code{@value{AS}} does not produce NaNs itself and
1028 therefore these directives do not affect code generation. They simply
1029 control the setting of the @code{EF_MIPS_NAN2008} flag.
1031 Traditional MIPS assemblers do not support these directives.
1033 @node MIPS Option Stack
1034 @section Directives to save and restore options
1036 @cindex MIPS option stack
1037 @kindex @code{.set push}
1038 @kindex @code{.set pop}
1039 The directives @code{.set push} and @code{.set pop} may be used to save
1040 and restore the current settings for all the options which are
1041 controlled by @code{.set}. The @code{.set push} directive saves the
1042 current settings on a stack. The @code{.set pop} directive pops the
1043 stack and restores the settings.
1045 These directives can be useful inside an macro which must change an
1046 option such as the ISA level or instruction reordering but does not want
1047 to change the state of the code which invoked the macro.
1049 Traditional MIPS assemblers do not support these directives.
1051 @node MIPS ASE Instruction Generation Overrides
1052 @section Directives to control generation of MIPS ASE instructions
1054 @cindex MIPS MIPS-3D instruction generation override
1055 @kindex @code{.set mips3d}
1056 @kindex @code{.set nomips3d}
1057 The directive @code{.set mips3d} makes the assembler accept instructions
1058 from the MIPS-3D Application Specific Extension from that point on
1059 in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
1060 instructions from being accepted.
1062 @cindex SmartMIPS instruction generation override
1063 @kindex @code{.set smartmips}
1064 @kindex @code{.set nosmartmips}
1065 The directive @code{.set smartmips} makes the assembler accept
1066 instructions from the SmartMIPS Application Specific Extension to the
1067 MIPS32 ISA from that point on in the assembly. The
1068 @code{.set nosmartmips} directive prevents SmartMIPS instructions from
1071 @cindex MIPS MDMX instruction generation override
1072 @kindex @code{.set mdmx}
1073 @kindex @code{.set nomdmx}
1074 The directive @code{.set mdmx} makes the assembler accept instructions
1075 from the MDMX Application Specific Extension from that point on
1076 in the assembly. The @code{.set nomdmx} directive prevents MDMX
1077 instructions from being accepted.
1079 @cindex MIPS DSP Release 1 instruction generation override
1080 @kindex @code{.set dsp}
1081 @kindex @code{.set nodsp}
1082 The directive @code{.set dsp} makes the assembler accept instructions
1083 from the DSP Release 1 Application Specific Extension from that point
1084 on in the assembly. The @code{.set nodsp} directive prevents DSP
1085 Release 1 instructions from being accepted.
1087 @cindex MIPS DSP Release 2 instruction generation override
1088 @kindex @code{.set dspr2}
1089 @kindex @code{.set nodspr2}
1090 The directive @code{.set dspr2} makes the assembler accept instructions
1091 from the DSP Release 2 Application Specific Extension from that point
1092 on in the assembly. This directive implies @code{.set dsp}. The
1093 @code{.set nodspr2} directive prevents DSP Release 2 instructions from
1096 @cindex MIPS DSP Release 3 instruction generation override
1097 @kindex @code{.set dspr3}
1098 @kindex @code{.set nodspr3}
1099 The directive @code{.set dspr3} makes the assembler accept instructions
1100 from the DSP Release 3 Application Specific Extension from that point
1101 on in the assembly. This directive implies @code{.set dsp} and
1102 @code{.set dspr2}. The @code{.set nodspr3} directive prevents DSP
1103 Release 3 instructions from being accepted.
1105 @cindex MIPS MT instruction generation override
1106 @kindex @code{.set mt}
1107 @kindex @code{.set nomt}
1108 The directive @code{.set mt} makes the assembler accept instructions
1109 from the MT Application Specific Extension from that point on
1110 in the assembly. The @code{.set nomt} directive prevents MT
1111 instructions from being accepted.
1113 @cindex MIPS MCU instruction generation override
1114 @kindex @code{.set mcu}
1115 @kindex @code{.set nomcu}
1116 The directive @code{.set mcu} makes the assembler accept instructions
1117 from the MCU Application Specific Extension from that point on
1118 in the assembly. The @code{.set nomcu} directive prevents MCU
1119 instructions from being accepted.
1121 @cindex MIPS SIMD Architecture instruction generation override
1122 @kindex @code{.set msa}
1123 @kindex @code{.set nomsa}
1124 The directive @code{.set msa} makes the assembler accept instructions
1125 from the MIPS SIMD Architecture Extension from that point on
1126 in the assembly. The @code{.set nomsa} directive prevents MSA
1127 instructions from being accepted.
1129 @cindex Virtualization instruction generation override
1130 @kindex @code{.set virt}
1131 @kindex @code{.set novirt}
1132 The directive @code{.set virt} makes the assembler accept instructions
1133 from the Virtualization Application Specific Extension from that point
1134 on in the assembly. The @code{.set novirt} directive prevents Virtualization
1135 instructions from being accepted.
1137 @cindex MIPS eXtended Physical Address (XPA) instruction generation override
1138 @kindex @code{.set xpa}
1139 @kindex @code{.set noxpa}
1140 The directive @code{.set xpa} makes the assembler accept instructions
1141 from the XPA Extension from that point on in the assembly. The
1142 @code{.set noxpa} directive prevents XPA instructions from being accepted.
1144 @cindex MIPS16e2 instruction generation override
1145 @kindex @code{.set mips16e2}
1146 @kindex @code{.set nomips16e2}
1147 The directive @code{.set mips16e2} makes the assembler accept instructions
1148 from the MIPS16e2 Application Specific Extension from that point on in the
1149 assembly, whenever in MIPS16 mode. The @code{.set nomips16e2} directive
1150 prevents MIPS16e2 instructions from being accepted, in MIPS16 mode. Neither
1151 directive affects the state of MIPS16 mode being active itself which has
1154 @cindex MIPS cyclic redundancy check (CRC) instruction generation override
1155 @kindex @code{.set crc}
1156 @kindex @code{.set nocrc}
1157 The directive @code{.set crc} makes the assembler accept instructions
1158 from the CRC Extension from that point on in the assembly. The
1159 @code{.set nocrc} directive prevents CRC instructions from being accepted.
1161 @cindex MIPS Global INValidate (GINV) instruction generation override
1162 @kindex @code{.set ginv}
1163 @kindex @code{.set noginv}
1164 The directive @code{.set ginv} makes the assembler accept instructions
1165 from the GINV Extension from that point on in the assembly. The
1166 @code{.set noginv} directive prevents GINV instructions from being accepted.
1168 @cindex Loongson MultiMedia extensions Instructions (MMI) generation override
1169 @kindex @code{.set loongson-mmi}
1170 @kindex @code{.set noloongson-mmi}
1171 The directive @code{.set loongson-mmi} makes the assembler accept
1172 instructions from the MMI Extension from that point on in the assembly.
1173 The @code{.set noloongson-mmi} directive prevents MMI instructions from
1176 @cindex Loongson Content Address Memory (CAM) generation override
1177 @kindex @code{.set loongson-cam}
1178 @kindex @code{.set noloongson-cam}
1179 The directive @code{.set loongson-cam} makes the assembler accept
1180 instructions from the Loongson CAM from that point on in the assembly.
1181 The @code{.set noloongson-cam} directive prevents Loongson CAM instructions
1182 from being accepted.
1184 @cindex Loongson EXTensions (EXT) instructions generation override
1185 @kindex @code{.set loongson-ext}
1186 @kindex @code{.set noloongson-ext}
1187 The directive @code{.set loongson-ext} makes the assembler accept
1188 instructions from the Loongson EXT from that point on in the assembly.
1189 The @code{.set noloongson-ext} directive prevents Loongson EXT instructions
1190 from being accepted.
1192 @cindex Loongson EXTensions R2 (EXT2) instructions generation override
1193 @kindex @code{.set loongson-ext2}
1194 @kindex @code{.set noloongson-ext2}
1195 The directive @code{.set loongson-ext2} makes the assembler accept
1196 instructions from the Loongson EXT2 from that point on in the assembly.
1197 This directive implies @code{.set loognson-ext}.
1198 The @code{.set noloongson-ext2} directive prevents Loongson EXT2 instructions
1199 from being accepted.
1201 Traditional MIPS assemblers do not support these directives.
1203 @node MIPS Floating-Point
1204 @section Directives to override floating-point options
1206 @cindex Disable floating-point instructions
1207 @kindex @code{.set softfloat}
1208 @kindex @code{.set hardfloat}
1209 The directives @code{.set softfloat} and @code{.set hardfloat} provide
1210 finer control of disabling and enabling float-point instructions.
1211 These directives always override the default (that hard-float
1212 instructions are accepted) or the command-line options
1213 (@samp{-msoft-float} and @samp{-mhard-float}).
1215 @cindex Disable single-precision floating-point operations
1216 @kindex @code{.set singlefloat}
1217 @kindex @code{.set doublefloat}
1218 The directives @code{.set singlefloat} and @code{.set doublefloat}
1219 provide finer control of disabling and enabling double-precision
1220 float-point operations. These directives always override the default
1221 (that double-precision operations are accepted) or the command-line
1222 options (@samp{-msingle-float} and @samp{-mdouble-float}).
1224 Traditional MIPS assemblers do not support these directives.
1227 @section Syntactical considerations for the MIPS assembler
1229 * MIPS-Chars:: Special Characters
1233 @subsection Special Characters
1235 @cindex line comment character, MIPS
1236 @cindex MIPS line comment character
1237 The presence of a @samp{#} on a line indicates the start of a comment
1238 that extends to the end of the current line.
1240 If a @samp{#} appears as the first character of a line, the whole line
1241 is treated as a comment, but in this case the line can also be a
1242 logical line number directive (@pxref{Comments}) or a
1243 preprocessor control command (@pxref{Preprocessing}).
1245 @cindex line separator, MIPS
1246 @cindex statement separator, MIPS
1247 @cindex MIPS line separator
1248 The @samp{;} character can be used to separate statements on the same
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