gas/doc/c-mips.texi

   1 @c Copyright (C) 1991, 92, 93, 94, 95, 1997 Free Software Foundation, Inc.
   2 @c This is part of the GAS manual.
   3 @c For copying conditions, see the file as.texinfo.
   4 @ifset GENERIC
   5 @page
   6 @node MIPS-Dependent
   7 @chapter MIPS Dependent Features
   8 @end ifset
   9 @ifclear GENERIC
  10 @node Machine Dependencies
  11 @chapter MIPS Dependent Features
  12 @end ifclear
  13
  14 @cindex MIPS processor
  15 @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
  16 different @sc{mips} processors, and MIPS ISA levels I through IV.  For
  17 information about the @sc{mips} instruction set, see @cite{MIPS RISC
  18 Architecture}, by Kane and Heindrich (Prentice-Hall).  For an overview
  19 of @sc{mips} assembly conventions, see ``Appendix D: Assembly Language
  20 Programming'' in the same work.
  21
  22 @menu
  23 * MIPS Opts::           Assembler options
  24 * MIPS Object::         ECOFF object code
  25 * MIPS Stabs::          Directives for debugging information
  26 * MIPS ISA::            Directives to override the ISA level
  27 * MIPS autoextend::     Directives for extending MIPS 16 bit instructions
  28 * MIPS insn::           Directive to mark data as an instruction
  29 * MIPS option stack::   Directives to save and restore options
  30 @end menu
  31
  32 @node MIPS Opts
  33 @section Assembler options
  34
  35 The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these
  36 special options:
  37
  38 @table @code
  39 @cindex @code{-G} option (MIPS)
  40 @item -G @var{num}
  41 This option sets the largest size of an object that can be referenced
  42 implicitly with the @code{gp} register.  It is only accepted for targets
  43 that use @sc{ecoff} format.  The default value is 8.
  44
  45 @cindex @code{-EB} option (MIPS)
  46 @cindex @code{-EL} option (MIPS)
  47 @cindex MIPS big-endian output
  48 @cindex MIPS little-endian output
  49 @cindex big-endian output, MIPS
  50 @cindex little-endian output, MIPS
  51 @item -EB
  52 @itemx -EL
  53 Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or
  54 little-endian output at run time (unlike the other @sc{gnu} development
  55 tools, which must be configured for one or the other).  Use @samp{-EB}
  56 to select big-endian output, and @samp{-EL} for little-endian.
  57
  58 @cindex MIPS architecture options
  59 @item -mips1
  60 @itemx -mips2
  61 @itemx -mips3
  62 @itemx -mips4
  63 Generate code for a particular MIPS Instruction Set Architecture level.
  64 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
  65 @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
  66 @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
  67 @sc{r10000} processors.  You can also switch instruction sets during the
  68 assembly; see @ref{MIPS ISA,, Directives to override the ISA level}.
  69
  70 @item -mgp32
  71 Assume that 32-bit general purpose registers are available.  This
  72 affects synthetic instructions such as @code{move}, which will assemble
  73 to a 32-bit or a 64-bit instruction depending on this flag.  On some
  74 MIPS variants there is a 32-bit mode flag; when this flag is set,
  75 64-bit instructions generate a trap.  Also, some 32-bit OSes only save
  76 the 32-bit registers on a context switch, so it is essential never to
  77 use the 64-bit registers.
  78
  79 @item -mgp64
  80 Assume that 64-bit general purpose registers are available.  This is
  81 provided in the interests of symmetry with -gp32.
  82
  83 @item -mips16
  84 @itemx -no-mips16
  85 Generate code for the MIPS 16 processor.  This is equivalent to putting
  86 @samp{.set mips16} at the start of the assembly file.  @samp{-no-mips16}
  87 turns off this option.
  88
  89 @item -mfix7000
  90 @itemx -no-mfix7000
  91 Cause nops to be inserted if the read of the destination register
  92 of an mfhi or mflo instruction occurs in the following two instructions.
  93
  94 @item -m4010
  95 @itemx -no-m4010
  96 Generate code for the LSI @sc{r4010} chip.  This tells the assembler to
  97 accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc},
  98 etc.), and to not schedule @samp{nop} instructions around accesses to
  99 the @samp{HI} and @samp{LO} registers.  @samp{-no-m4010} turns off this
 100 option.
 101
 102 @item -m4650
 103 @itemx -no-m4650
 104 Generate code for the MIPS @sc{r4650} chip.  This tells the assembler to accept
 105 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
 106 instructions around accesses to the @samp{HI} and @samp{LO} registers.
 107 @samp{-no-m4650} turns off this option.
 108
 109 @itemx -m3900
 110 @itemx -no-m3900
 111 @itemx -m4100
 112 @itemx -no-m4100
 113 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
 114 @sc{r@var{nnnn}} chip.  This tells the assembler to accept instructions
 115 specific to that chip, and to schedule for that chip's hazards.
 116
 117 @item -mcpu=@var{cpu}
 118 Generate code for a particular MIPS cpu.  It is exactly equivalent to
 119 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
 120 understood.  Valid @var{cpu} value are:
 121
 122 @quotation
 123 2000,
 124 3000,
 125 3900,
 126 4000,
 127 4010,
 128 4100,
 129 4111,
 130 4300,
 131 4400,
 132 4600,
 133 4650,
 134 5000,
 135 rm5200,
 136 rm5230,
 137 rm5231,
 138 rm5261,
 139 rm5721,
 140 6000,
 141 rm7000,
 142 8000,
 143 10000
 144 @end quotation
 145
 146
 147 @cindex @code{-nocpp} ignored (MIPS)
 148 @item -nocpp
 149 This option is ignored.  It is accepted for command-line compatibility with
 150 other assemblers, which use it to turn off C style preprocessing.  With
 151 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
 152 @sc{gnu} assembler itself never runs the C preprocessor.
 153
 154 @item --trap
 155 @itemx --no-break
 156 @c FIXME!  (1) reflect these options (next item too) in option summaries;
 157 @c         (2) stop teasing, say _which_ instructions expanded _how_.
 158 @code{@value{AS}} automatically macro expands certain division and
 159 multiplication instructions to check for overflow and division by zero.  This
 160 option causes @code{@value{AS}} to generate code to take a trap exception
 161 rather than a break exception when an error is detected.  The trap instructions
 162 are only supported at Instruction Set Architecture level 2 and higher.
 163
 164 @item --break
 165 @itemx --no-trap
 166 Generate code to take a break exception rather than a trap exception when an
 167 error is detected.  This is the default.
 168 @end table
 169
 170 @node MIPS Object
 171 @section MIPS ECOFF object code
 172
 173 @cindex ECOFF sections
 174 @cindex MIPS ECOFF sections
 175 Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections
 176 besides the usual @code{.text}, @code{.data} and @code{.bss}.  The
 177 additional sections are @code{.rdata}, used for read-only data,
 178 @code{.sdata}, used for small data, and @code{.sbss}, used for small
 179 common objects.
 180
 181 @cindex small objects, MIPS ECOFF
 182 @cindex @code{gp} register, MIPS
 183 When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28})
 184 register to form the address of a ``small object''.  Any object in the
 185 @code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense.
 186 For external objects, or for objects in the @code{.bss} section, you can use
 187 the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via
 188 @code{$gp}; the default value is 8, meaning that a reference to any object
 189 eight bytes or smaller uses @code{$gp}.  Passing @samp{-G 0} to
 190 @code{@value{AS}} prevents it from using the @code{$gp} register on the basis
 191 of object size (but the assembler uses @code{$gp} for objects in @code{.sdata}
 192 or @code{sbss} in any case).  The size of an object in the @code{.bss} section
 193 is set by the @code{.comm} or @code{.lcomm} directive that defines it.  The
 194 size of an external object may be set with the @code{.extern} directive.  For
 195 example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes
 196 in length, whie leaving @code{sym} otherwise undefined.
 197
 198 Using small @sc{ecoff} objects requires linker support, and assumes that the
 199 @code{$gp} register is correctly initialized (normally done automatically by
 200 the startup code).  @sc{mips} @sc{ecoff} assembly code must not modify the
 201 @code{$gp} register.
 202
 203 @node MIPS Stabs
 204 @section Directives for debugging information
 205
 206 @cindex MIPS debugging directives
 207 @sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for
 208 generating debugging information which are not support by traditional @sc{mips}
 209 assemblers.  These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file},
 210 @code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val},
 211 @code{.stabd}, @code{.stabn}, and @code{.stabs}.  The debugging information
 212 generated by the three @code{.stab} directives can only be read by @sc{gdb},
 213 not by traditional @sc{mips} debuggers (this enhancement is required to fully
 214 support C++ debugging).  These directives are primarily used by compilers, not
 215 assembly language programmers!
 216
 217 @node MIPS ISA
 218 @section Directives to override the ISA level
 219
 220 @cindex MIPS ISA override
 221 @kindex @code{.set mips@var{n}}
 222 @sc{gnu} @code{@value{AS}} supports an additional directive to change
 223 the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
 224 mips@var{n}}.  @var{n} should be a number from 0 to 4.  A value from 1
 225 to 4 makes the assembler accept instructions for the corresponding
 226 @sc{isa} level, from that point on in the assembly.  @code{.set
 227 mips@var{n}} affects not only which instructions are permitted, but also
 228 how certain macros are expanded.  @code{.set mips0} restores the
 229 @sc{isa} level to its original level: either the level you selected with
 230 command line options, or the default for your configuration.  You can
 231 use this feature to permit specific @sc{r4000} instructions while
 232 assembling in 32 bit mode.  Use this directive with care!
 233
 234 The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
 235 in which it will assemble instructions for the MIPS 16 processor.  Use
 236 @samp{.set nomips16} to return to normal 32 bit mode.
 237
 238 Traditional @sc{mips} assemblers do not support this directive.
 239
 240 @node MIPS autoextend
 241 @section Directives for extending MIPS 16 bit instructions
 242
 243 @kindex @code{.set autoextend}
 244 @kindex @code{.set noautoextend}
 245 By default, MIPS 16 instructions are automatically extended to 32 bits
 246 when necessary.  The directive @samp{.set noautoextend} will turn this
 247 off.  When @samp{.set noautoextend} is in effect, any 32 bit instruction
 248 must be explicitly extended with the @samp{.e} modifier (e.g.,
 249 @samp{li.e $4,1000}).  The directive @samp{.set autoextend} may be used
 250 to once again automatically extend instructions when necessary.
 251
 252 This directive is only meaningful when in MIPS 16 mode.  Traditional
 253 @sc{mips} assemblers do not support this directive.
 254
 255 @node MIPS insn
 256 @section Directive to mark data as an instruction
 257
 258 @kindex @code{.insn}
 259 The @code{.insn} directive tells @code{@value{AS}} that the following
 260 data is actually instructions.  This makes a difference in MIPS 16 mode:
 261 when loading the address of a label which precedes instructions,
 262 @code{@value{AS}} automatically adds 1 to the value, so that jumping to
 263 the loaded address will do the right thing.
 264
 265 @node MIPS option stack
 266 @section Directives to save and restore options
 267
 268 @cindex MIPS option stack
 269 @kindex @code{.set push}
 270 @kindex @code{.set pop}
 271 The directives @code{.set push} and @code{.set pop} may be used to save
 272 and restore the current settings for all the options which are
 273 controlled by @code{.set}.  The @code{.set push} directive saves the
 274 current settings on a stack.  The @code{.set pop} directive pops the
 275 stack and restores the settings.
 276
 277 These directives can be useful inside an macro which must change an
 278 option such as the ISA level or instruction reordering but does not want
 279 to change the state of the code which invoked the macro.
 280
 281 Traditional @sc{mips} assemblers do not support these directives.