gas/doc/c-riscv.texi

   1 @c Copyright (C) 2016-2020 Free Software Foundation, Inc.
   2 @c This is part of the GAS anual.
   3 @c For copying conditions, see the file as.texinfo
   4 @c man end
   5
   6 @ifset GENERIC
   7 @page
   8 @node RISC-V-Dependent
   9 @chapter RISC-V Dependent Features
  10 @end ifset
  11 @ifclear GENERIC
  12 @node Machine Dependencies
  13 @chapter RISC-V Dependent Features
  14 @end ifclear
  15
  16 @cindex RISC-V support
  17 @menu
  18 * RISC-V-Options::        RISC-V Options
  19 * RISC-V-Directives::     RISC-V Directives
  20 * RISC-V-Modifiers::      RISC-V Assembler Modifiers
  21 * RISC-V-Formats::        RISC-V Instruction Formats
  22 * RISC-V-ATTRIBUTE::      RISC-V Object Attribute
  23 @end menu
  24
  25 @node RISC-V-Options
  26 @section RISC-V Options
  27
  28 The following table lists all available RISC-V specific options.
  29
  30 @c man begin OPTIONS
  31 @table @gcctabopt
  32
  33 @cindex @samp{-fpic} option, RISC-V
  34 @item -fpic
  35 @itemx -fPIC
  36 Generate position-independent code
  37
  38 @cindex @samp{-fno-pic} option, RISC-V
  39 @item -fno-pic
  40 Don't generate position-independent code (default)
  41
  42 @cindex @samp{-march=ISA} option, RISC-V
  43 @item -march=ISA
  44 Select the base isa, as specified by ISA.  For example -march=rv32ima.
  45
  46 @cindex @samp{-mabi=ABI} option, RISC-V
  47 @item -mabi=ABI
  48 Selects the ABI, which is either "ilp32" or "lp64", optionally followed
  49 by "f", "d", or "q" to indicate single-precision, double-precision, or
  50 quad-precision floating-point calling convention, or none to indicate
  51 the soft-float calling convention.  Also, "ilp32" can optionally be followed
  52 by "e" to indicate the RVE ABI, which is always soft-float.
  53
  54 @cindex @samp{-mrelax} option, RISC-V
  55 @item -mrelax
  56 Take advantage of linker relaxations to reduce the number of instructions
  57 required to materialize symbol addresses. (default)
  58
  59 @cindex @samp{-mno-relax} option, RISC-V
  60 @item -mno-relax
  61 Don't do linker relaxations.
  62
  63 @cindex @samp{-march-attr} option, RISC-V
  64 @item -march-attr
  65 Generate the default contents for the riscv elf attribute section if the
  66 .attribute directives are not set.  This section is used to record the
  67 information that a linker or runtime loader needs to check compatibility.
  68 This information includes ISA string, stack alignment requirement, unaligned
  69 memory accesses, and the major, minor and revision version of privileged
  70 specification.
  71
  72 @cindex @samp{-mno-arch-attr} option, RISC-V
  73 @item -mno-arch-attr
  74 Don't generate the default riscv elf attribute section if the .attribute
  75 directives are not set.
  76
  77 @cindex @samp{-mcsr-check} option, RISC-V
  78 @item -mcsr-check
  79 Enable the CSR checking for the ISA-dependent CRS and the read-only CSR.
  80 The ISA-dependent CSR are only valid when the specific ISA is set.  The
  81 read-only CSR can not be written by the CSR instructions.
  82
  83 @cindex @samp{-mno-csr-check} option, RISC-V
  84 @item -mno-csr-check
  85 Don't do CSR cheching.
  86 @end table
  87 @c man end
  88
  89 @node RISC-V-Directives
  90 @section RISC-V Directives
  91 @cindex machine directives, RISC-V
  92 @cindex RISC-V machine directives
  93
  94 The following table lists all available RISC-V specific directives.
  95
  96 @table @code
  97
  98 @cindex @code{align} directive
  99 @item .align @var{size-log-2}
 100 Align to the given boundary, with the size given as log2 the number of bytes to
 101 align to.
 102
 103 @cindex Data directives
 104 @item .half @var{value}
 105 @itemx .word @var{value}
 106 @itemx .dword @var{value}
 107 Emits a half-word, word, or double-word value at the current position.
 108
 109 @cindex DTP-relative data directives
 110 @item .dtprelword @var{value}
 111 @itemx .dtpreldword @var{value}
 112 Emits a DTP-relative word (or double-word) at the current position.  This is
 113 meant to be used by the compiler in shared libraries for DWARF debug info for
 114 thread local variables.
 115
 116 @cindex BSS directive
 117 @item .bss
 118 Sets the current section to the BSS section.
 119
 120 @cindex LEB128 directives
 121 @item .uleb128 @var{value}
 122 @itemx .sleb128 @var{value}
 123 Emits a signed or unsigned LEB128 value at the current position.  This only
 124 accepts constant expressions, because symbol addresses can change with
 125 relaxation, and we don't support relocations to modify LEB128 values at link
 126 time.
 127
 128 @cindex Option directive
 129 @cindex @code{option} directive
 130 @item .option @var{argument}
 131 Modifies RISC-V specific assembler options inline with the assembly code.
 132 This is used when particular instruction sequences must be assembled with a
 133 specific set of options.  For example, since we relax addressing sequences to
 134 shorter GP-relative sequences when possible the initial load of GP must not be
 135 relaxed and should be emitted as something like
 136
 137 @smallexample
 138         .option push
 139         .option norelax
 140         la gp, __global_pointer$
 141         .option pop
 142 @end smallexample
 143
 144 in order to produce after linker relaxation the expected
 145
 146 @smallexample
 147         auipc gp, %pcrel_hi(__global_pointer$)
 148         addi gp, gp, %pcrel_lo(__global_pointer$)
 149 @end smallexample
 150
 151 instead of just
 152
 153 @smallexample
 154         addi gp, gp, 0
 155 @end smallexample
 156
 157 It's not expected that options are changed in this manner during regular use,
 158 but there are a handful of esoteric cases like the one above where users need
 159 to disable particular features of the assembler for particular code sequences.
 160 The complete list of option arguments is shown below:
 161
 162 @table @code
 163 @item push
 164 @itemx pop
 165 Pushes or pops the current option stack.  These should be used whenever
 166 changing an option in line with assembly code in order to ensure the user's
 167 command-line options are respected for the bulk of the file being assembled.
 168
 169 @item rvc
 170 @itemx norvc
 171 Enables or disables the generation of compressed instructions.  Instructions
 172 are opportunistically compressed by the RISC-V assembler when possible, but
 173 sometimes this behavior is not desirable.
 174
 175 @item pic
 176 @itemx nopic
 177 Enables or disables position-independent code generation.  Unless you really
 178 know what you're doing, this should only be at the top of a file.
 179
 180 @item relax
 181 @itemx norelax
 182 Enables or disables relaxation.  The RISC-V assembler and linker
 183 opportunistically relax some code sequences, but sometimes this behavior is not
 184 desirable.
 185 @end table
 186
 187 @item csr-check
 188 @itemx no-csr-check
 189 Enables or disables the CSR checking.
 190
 191 @cindex INSN directives
 192 @item .insn @var{value}
 193 @itemx .insn @var{value}
 194 This directive permits the numeric representation of an instructions
 195 and makes the assembler insert the operands according to one of the
 196 instruction formats for @samp{.insn} (@ref{RISC-V-Formats}).
 197 For example, the instruction @samp{add a0, a1, a2} could be written as
 198 @samp{.insn r 0x33, 0, 0, a0, a1, a2}.
 199
 200 @cindex @code{.attribute} directive, RISC-V
 201 @item .attribute @var{tag}, @var{value}
 202 Set the object attribute @var{tag} to @var{value}.
 203
 204 The @var{tag} is either an attribute number, or one of the following:
 205 @code{Tag_RISCV_arch}, @code{Tag_RISCV_stack_align},
 206 @code{Tag_RISCV_unaligned_access}, @code{Tag_RISCV_priv_spec},
 207 @code{Tag_RISCV_priv_spec_minor}, @code{Tag_RISCV_priv_spec_revision}.
 208
 209 @end table
 210
 211 @node RISC-V-Modifiers
 212 @section RISC-V Assembler Modifiers
 213
 214 The RISC-V assembler supports following modifiers for relocatable addresses
 215 used in RISC-V instruction operands.  However, we also support some pseudo
 216 instructions that are easier to use than these modifiers.
 217
 218 @table @code
 219 @item %lo(@var{symbol})
 220 The low 12 bits of absolute address for @var{symbol}.
 221
 222 @item %hi(@var{symbol})
 223 The high 20 bits of absolute address for @var{symbol}.  This is usually
 224 used with the %lo modifier to represent a 32-bit absolute address.
 225
 226 @smallexample
 227         lui        a0, %hi(@var{symbol})     // R_RISCV_HI20
 228         addi       a0, a0, %lo(@var{symbol}) // R_RISCV_LO12_I
 229
 230         lui        a0, %hi(@var{symbol})     // R_RISCV_HI20
 231         load/store a0, %lo(@var{symbol})(a0) // R_RISCV_LO12_I/S
 232 @end smallexample
 233
 234 @item %pcrel_lo(@var{label})
 235 The low 12 bits of relative address between pc and @var{symbol}.
 236 The @var{symbol} is related to the high part instruction which is marked
 237 by @var{label}.
 238
 239 @item %pcrel_hi(@var{symbol})
 240 The high 20 bits of relative address between pc and @var{symbol}.
 241 This is usually used with the %pcrel_lo modifier to represent a +/-2GB
 242 pc-relative range.
 243
 244 @smallexample
 245 @var{label}:
 246         auipc      a0, %pcrel_hi(@var{symbol})    // R_RISCV_PCREL_HI20
 247         addi       a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I
 248
 249 @var{label}:
 250         auipc      a0, %pcrel_hi(@var{symbol})    // R_RISCV_PCREL_HI20
 251         load/store a0, %pcrel_lo(@var{label})(a0) // R_RISCV_PCREL_LO12_I/S
 252 @end smallexample
 253
 254 Or you can use the pseudo lla/lw/sw/... instruction to do this.
 255
 256 @smallexample
 257         lla  a0, @var{symbol}
 258 @end smallexample
 259
 260 @item %got_pcrel_hi(@var{symbol})
 261 The high 20 bits of relative address between pc and the GOT entry of
 262 @var{symbol}.  This is usually used with the %pcrel_lo modifier to access
 263 the GOT entry.
 264
 265 @smallexample
 266 @var{label}:
 267         auipc      a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20
 268         addi       a0, a0, %pcrel_lo(@var{label})  // R_RISCV_PCREL_LO12_I
 269
 270 @var{label}:
 271         auipc      a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20
 272         load/store a0, %pcrel_lo(@var{label})(a0)  // R_RISCV_PCREL_LO12_I/S
 273 @end smallexample
 274
 275 Also, the pseudo la instruction with PIC has similar behavior.
 276
 277 @item %tprel_add(@var{symbol})
 278 This is used purely to associate the R_RISCV_TPREL_ADD relocation for
 279 TLS relaxation.  This one is only valid as the fourth operand to the normally
 280 3 operand add instruction.
 281
 282 @item %tprel_lo(@var{symbol})
 283 The low 12 bits of relative address between tp and @var{symbol}.
 284
 285 @item %tprel_hi(@var{symbol})
 286 The high 20 bits of relative address between tp and @var{symbol}.  This is
 287 usually used with the %tprel_lo and %tprel_add modifiers to access the thread
 288 local variable @var{symbol} in TLS Local Exec.
 289
 290 @smallexample
 291         lui        a5, %tprel_hi(@var{symbol})          // R_RISCV_TPREL_HI20
 292         add        a5, a5, tp, %tprel_add(@var{symbol}) // R_RISCV_TPREL_ADD
 293         load/store t0, %tprel_lo(@var{symbol})(a5)      // R_RISCV_TPREL_LO12_I/S
 294 @end smallexample
 295
 296 @item %tls_ie_pcrel_hi(@var{symbol})
 297 The high 20 bits of relative address between pc and GOT entry.  It is
 298 usually used with the %pcrel_lo modifier to access the thread local
 299 variable @var{symbol} in TLS Initial Exec.
 300
 301 @smallexample
 302         la.tls.ie  a5, @var{symbol}
 303         add        a5, a5, tp
 304         load/store t0, 0(a5)
 305 @end smallexample
 306
 307 The pseudo la.tls.ie instruction can be expended to
 308
 309 @smallexample
 310 @var{label}:
 311         auipc a5, %tls_ie_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GOT_HI20
 312         load  a5, %pcrel_lo(@var{label})(a5)     // R_RISCV_PCREL_LO12_I
 313 @end smallexample
 314
 315 @item %tls_gd_pcrel_hi(@var{symbol})
 316 The high 20 bits of relative address between pc and GOT entry.  It is
 317 usually used with the %pcrel_lo modifier to access the thread local variable
 318 @var{symbol} in TLS Global Dynamic.
 319
 320 @smallexample
 321         la.tls.gd  a0, @var{symbol}
 322         call       __tls_get_addr@@plt
 323         mv         a5, a0
 324         load/store t0, 0(a5)
 325 @end smallexample
 326
 327 The pseudo la.tls.gd instruction can be expended to
 328
 329 @smallexample
 330 @var{label}:
 331         auipc a0, %tls_gd_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GD_HI20
 332         addi  a0, a0, %pcrel_lo(@var{label})     // R_RISCV_PCREL_LO12_I
 333 @end smallexample
 334
 335 @end table
 336
 337 @node RISC-V-Formats
 338 @section RISC-V Instruction Formats
 339 @cindex instruction formats, risc-v
 340 @cindex RISC-V instruction formats
 341
 342 The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 12
 343 instruction formats where some of the formats have multiple variants.
 344 For the @samp{.insn} pseudo directive the assembler recognizes some
 345 of the formats.
 346 Typically, the most general variant of the instruction format is used
 347 by the @samp{.insn} directive.
 348
 349 The following table lists the abbreviations used in the table of
 350 instruction formats:
 351
 352 @display
 353 @multitable @columnfractions .15 .40
 354 @item opcode @tab Unsigned immediate or opcode name for 7-bits opcode.
 355 @item opcode2 @tab Unsigned immediate or opcode name for 2-bits opcode.
 356 @item func7 @tab Unsigned immediate for 7-bits function code.
 357 @item func6 @tab Unsigned immediate for 6-bits function code.
 358 @item func4 @tab Unsigned immediate for 4-bits function code.
 359 @item func3 @tab Unsigned immediate for 3-bits function code.
 360 @item func2 @tab Unsigned immediate for 2-bits function code.
 361 @item rd @tab Destination register number for operand x, can be GPR or FPR.
 362 @item rd' @tab Destination register number for operand x,
 363 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
 364 @item rs1 @tab First source register number for operand x, can be GPR or FPR.
 365 @item rs1' @tab First source register number for operand x,
 366 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
 367 @item rs2 @tab Second source register number for operand x, can be GPR or FPR.
 368 @item rs2' @tab Second source register number for operand x,
 369 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
 370 @item simm12 @tab Sign-extended 12-bit immediate for operand x.
 371 @item simm20 @tab Sign-extended 20-bit immediate for operand x.
 372 @item simm6 @tab Sign-extended 6-bit immediate for operand x.
 373 @item uimm8 @tab Unsigned 8-bit immediate for operand x.
 374 @item symbol @tab Symbol or lable reference for operand x.
 375 @end multitable
 376 @end display
 377
 378 The following table lists all available opcode name:
 379
 380 @table @code
 381 @item C0
 382 @item C1
 383 @item C2
 384 Opcode space for compressed instructions.
 385
 386 @item LOAD
 387 Opcode space for load instructions.
 388
 389 @item LOAD_FP
 390 Opcode space for floating-point load instructions.
 391
 392 @item STORE
 393 Opcode space for store instructions.
 394
 395 @item STORE_FP
 396 Opcode space for floating-point store instructions.
 397
 398 @item AUIPC
 399 Opcode space for auipc instruction.
 400
 401 @item LUI
 402 Opcode space for lui instruction.
 403
 404 @item BRANCH
 405 Opcode space for branch instructions.
 406
 407 @item JAL
 408 Opcode space for jal instruction.
 409
 410 @item JALR
 411 Opcode space for jalr instruction.
 412
 413 @item OP
 414 Opcode space for ALU instructions.
 415
 416 @item OP_32
 417 Opcode space for 32-bits ALU instructions.
 418
 419 @item OP_IMM
 420 Opcode space for ALU with immediate instructions.
 421
 422 @item OP_IMM_32
 423 Opcode space for 32-bits ALU with immediate instructions.
 424
 425 @item OP_FP
 426 Opcode space for floating-point operation instructions.
 427
 428 @item MADD
 429 Opcode space for madd instruction.
 430
 431 @item MSUB
 432 Opcode space for msub instruction.
 433
 434 @item NMADD
 435 Opcode space for nmadd instruction.
 436
 437 @item NMSUB
 438 Opcode space for msub instruction.
 439
 440 @item AMO
 441 Opcode space for atomic memory operation instructions.
 442
 443 @item MISC_MEM
 444 Opcode space for misc instructions.
 445
 446 @item SYSTEM
 447 Opcode space for system instructions.
 448
 449 @item CUSTOM_0
 450 @item CUSTOM_1
 451 @item CUSTOM_2
 452 @item CUSTOM_3
 453 Opcode space for customize instructions.
 454
 455 @end table
 456
 457 An instruction is two or four bytes in length and must be aligned
 458 on a 2 byte boundary. The first two bits of the instruction specify the
 459 length of the instruction, 00, 01 and 10 indicates a two byte instruction,
 460 11 indicates a four byte instruction.
 461
 462 The following table lists the RISC-V instruction formats that are available
 463 with the @samp{.insn} pseudo directive:
 464
 465 @table @code
 466 @item R type: .insn r opcode, func3, func7, rd, rs1, rs2
 467 @verbatim
 468 +-------+-----+-----+-------+----+-------------+
 469 | func7 | rs2 | rs1 | func3 | rd |      opcode |
 470 +-------+-----+-----+-------+----+-------------+
 471 31      25    20    15      12   7             0
 472 @end verbatim
 473
 474 @item R type with 4 register operands: .insn r opcode, func3, func2, rd, rs1, rs2, rs3
 475 @itemx R4 type: .insn r4 opcode, func3, func2, rd, rs1, rs2, rs3
 476 @verbatim
 477 +-----+-------+-----+-----+-------+----+-------------+
 478 | rs3 | func2 | rs2 | rs1 | func3 | rd |      opcode |
 479 +-----+-------+-----+-----+-------+----+-------------+
 480 31    27      25    20    15      12   7             0
 481 @end verbatim
 482
 483 @item I type: .insn i opcode, func3, rd, rs1, simm12
 484 @verbatim
 485 +-------------+-----+-------+----+-------------+
 486 |      simm12 | rs1 | func3 | rd |      opcode |
 487 +-------------+-----+-------+----+-------------+
 488 31            20    15      12   7             0
 489 @end verbatim
 490
 491 @item S type: .insn s opcode, func3, rd, rs1, simm12
 492 @verbatim
 493 +--------------+-----+-----+-------+-------------+-------------+
 494 | simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] |      opcode |
 495 +--------------+-----+-----+-------+-------------+-------------+
 496 31             25    20    15      12            7             0
 497 @end verbatim
 498
 499 @item SB type: .insn sb opcode, func3, rd, rs1, symbol
 500 @itemx SB type: .insn sb opcode, func3, rd, simm12(rs1)
 501 @itemx B type: .insn s opcode, func3, rd, rs1, symbol
 502 @itemx B type: .insn s opcode, func3, rd, simm12(rs1)
 503 @verbatim
 504 +------------+--------------+-----+-----+-------+-------------+-------------+--------+
 505 | simm12[12] | simm12[10:5] | rs2 | rs1 | func3 | simm12[4:1] | simm12[11]] | opcode |
 506 +------------+--------------+-----+-----+-------+-------------+-------------+--------+
 507 31          30            25    20    15      12           7            0
 508 @end verbatim
 509
 510 @item U type: .insn u opcode, rd, simm20
 511 @verbatim
 512 +---------------------------+----+-------------+
 513 |                    simm20 | rd |      opcode |
 514 +---------------------------+----+-------------+
 515 31                          12   7             0
 516 @end verbatim
 517
 518 @item UJ type: .insn uj opcode, rd, symbol
 519 @itemx J type: .insn j opcode, rd, symbol
 520 @verbatim
 521 +------------+--------------+------------+---------------+----+-------------+
 522 | simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd |      opcode |
 523 +------------+--------------+------------+---------------+----+-------------+
 524 31           30             21           20              12   7             0
 525 @end verbatim
 526
 527 @item CR type: .insn cr opcode2, func4, rd, rs2
 528 @verbatim
 529 +---------+--------+-----+---------+
 530 |   func4 | rd/rs1 | rs2 | opcode2 |
 531 +---------+--------+-----+---------+
 532 15        12       7     2        0
 533 @end verbatim
 534
 535 @item CI type: .insn ci opcode2, func3, rd, simm6
 536 @verbatim
 537 +---------+-----+--------+-----+---------+
 538 |   func3 | imm | rd/rs1 | imm | opcode2 |
 539 +---------+-----+--------+-----+---------+
 540 15        13    12       7     2         0
 541 @end verbatim
 542
 543 @item CIW type: .insn ciw opcode2, func3, rd, uimm8
 544 @verbatim
 545 +---------+--------------+-----+---------+
 546 |   func3 |          imm | rd' | opcode2 |
 547 +---------+--------------+-----+---------+
 548 15        13             7     2         0
 549 @end verbatim
 550
 551 @item CA type: .insn ca opcode2, func6, func2, rd, rs2
 552 @verbatim
 553 +---------+----------+-------+------+--------+
 554 |   func6 | rd'/rs1' | func2 | rs2' | opcode |
 555 +---------+----------+-------+------+--------+
 556 15        10         7       5      2        0
 557 @end verbatim
 558
 559 @item CB type: .insn cb opcode2, func3, rs1, symbol
 560 @verbatim
 561 +---------+--------+------+--------+---------+
 562 |   func3 | offset | rs1' | offset | opcode2 |
 563 +---------+--------+------+--------+---------+
 564 15        13       10     7        2         0
 565 @end verbatim
 566
 567 @item CJ type: .insn cj opcode2, symbol
 568 @verbatim
 569 +---------+--------------------+---------+
 570 |   func3 |        jump target | opcode2 |
 571 +---------+--------------------+---------+
 572 15        13             7     2         0
 573 @end verbatim
 574
 575
 576 @end table
 577
 578 For the complete list of all instruction format variants see
 579 The RISC-V Instruction Set Manual Volume I: User-Level ISA.
 580
 581 @node RISC-V-ATTRIBUTE
 582 @section RISC-V Object Attribute
 583 @cindex Object Attribute, RISC-V
 584
 585 RISC-V attributes have a string value if the tag number is odd and an integer
 586 value if the tag number is even.
 587
 588 @table @r
 589 @item Tag_RISCV_stack_align (4)
 590 Tag_RISCV_strict_align records the N-byte stack alignment for this object.  The
 591 default value is 16 for RV32I or RV64I, and 4 for RV32E.
 592
 593 The smallest value will be used if object files with different
 594 Tag_RISCV_stack_align values are merged.
 595
 596 @item Tag_RISCV_arch (5)
 597 Tag_RISCV_arch contains a string for the target architecture taken from the
 598 option @option{-march}.  Different architectures will be integrated into a
 599 superset when object files are merged.
 600
 601 Note that the version information of the target architecture must be presented
 602 explicitly in the attribute and abbreviations must be expanded.  The version
 603 information, if not given by @option{-march}, must be in accordance with the
 604 default specified by the tool.  For example, the architecture @code{RV32I} has
 605 to be recorded in the attribute as @code{RV32I2P0} in which @code{2P0} stands
 606 for the default version of its base ISA.  On the other hand, the architecture
 607 @code{RV32G} has to be presented as @code{RV32I2P0_M2P0_A2P0_F2P0_D2P0} in
 608 which the abbreviation @code{G} is expanded to the @code{IMAFD} combination
 609 with default versions of the standard extensions.
 610
 611 @item Tag_RISCV_unaligned_access (6)
 612 Tag_RISCV_unaligned_access is 0 for files that do not allow any unaligned
 613 memory accesses, and 1 for files that do allow unaligned memory accesses.
 614
 615 @item Tag_RISCV_priv_spec (8)
 616 @item Tag_RISCV_priv_spec_minor (10)
 617 @item Tag_RISCV_priv_spec_revision (12)
 618 Tag_RISCV_priv_spec contains the major/minor/revision version information of
 619 the privileged specification.  It will report errors if object files of
 620 different privileged specification versions are merged.
 621
 622 @end table