gas/doc/c-riscv.texi

   1 @c Copyright (C) 2016-2021 Free Software Foundation, Inc.
   2 @c This is part of the GAS anual.
   3 @c For copying conditions, see the file as.texinfo
   4 @c man end
   5
   6 @ifset GENERIC
   7 @page
   8 @node RISC-V-Dependent
   9 @chapter RISC-V Dependent Features
  10 @end ifset
  11 @ifclear GENERIC
  12 @node Machine Dependencies
  13 @chapter RISC-V Dependent Features
  14 @end ifclear
  15
  16 @cindex RISC-V support
  17 @menu
  18 * RISC-V-Options::        RISC-V Options
  19 * RISC-V-Directives::     RISC-V Directives
  20 * RISC-V-Modifiers::      RISC-V Assembler Modifiers
  21 * RISC-V-Formats::        RISC-V Instruction Formats
  22 * RISC-V-ATTRIBUTE::      RISC-V Object Attribute
  23 @end menu
  24
  25 @node RISC-V-Options
  26 @section RISC-V Options
  27
  28 The following table lists all available RISC-V specific options.
  29
  30 @c man begin OPTIONS
  31 @table @gcctabopt
  32
  33 @cindex @samp{-fpic} option, RISC-V
  34 @item -fpic
  35 @itemx -fPIC
  36 Generate position-independent code
  37
  38 @cindex @samp{-fno-pic} option, RISC-V
  39 @item -fno-pic
  40 Don't generate position-independent code (default)
  41
  42 @cindex @samp{-march=ISA} option, RISC-V
  43 @item -march=ISA
  44 Select the base isa, as specified by ISA.  For example -march=rv32ima.
  45 If this option and the architecture attributes aren't set, then assembler
  46 will check the default configure setting --with-arch=ISA.
  47
  48 @cindex @samp{-misa-spec=ISAspec} option, RISC-V
  49 @item -misa-spec=ISAspec
  50 Select the default isa spec version.  If the version of ISA isn't set
  51 by -march, then assembler helps to set the version according to
  52 the default chosen spec.  If this option isn't set, then assembler will
  53 check the default configure setting --with-isa-spec=ISAspec.
  54
  55 @cindex @samp{-mpriv-spec=PRIVspec} option, RISC-V
  56 @item -mpriv-spec=PRIVspec
  57 Select the privileged spec version.  We can decide whether the CSR is valid or
  58 not according to the chosen spec.  If this option and the privilege attributes
  59 aren't set, then assembler will check the default configure setting
  60 --with-priv-spec=PRIVspec.
  61
  62 @cindex @samp{-mabi=ABI} option, RISC-V
  63 @item -mabi=ABI
  64 Selects the ABI, which is either "ilp32" or "lp64", optionally followed
  65 by "f", "d", or "q" to indicate single-precision, double-precision, or
  66 quad-precision floating-point calling convention, or none to indicate
  67 the soft-float calling convention.  Also, "ilp32" can optionally be followed
  68 by "e" to indicate the RVE ABI, which is always soft-float.
  69
  70 @cindex @samp{-mrelax} option, RISC-V
  71 @item -mrelax
  72 Take advantage of linker relaxations to reduce the number of instructions
  73 required to materialize symbol addresses. (default)
  74
  75 @cindex @samp{-mno-relax} option, RISC-V
  76 @item -mno-relax
  77 Don't do linker relaxations.
  78
  79 @cindex @samp{-march-attr} option, RISC-V
  80 @item -march-attr
  81 Generate the default contents for the riscv elf attribute section if the
  82 .attribute directives are not set.  This section is used to record the
  83 information that a linker or runtime loader needs to check compatibility.
  84 This information includes ISA string, stack alignment requirement, unaligned
  85 memory accesses, and the major, minor and revision version of privileged
  86 specification.
  87
  88 @cindex @samp{-mno-arch-attr} option, RISC-V
  89 @item -mno-arch-attr
  90 Don't generate the default riscv elf attribute section if the .attribute
  91 directives are not set.
  92
  93 @cindex @samp{-mcsr-check} option, RISC-V
  94 @item -mcsr-check
  95 Enable the CSR checking for the ISA-dependent CRS and the read-only CSR.
  96 The ISA-dependent CSR are only valid when the specific ISA is set.  The
  97 read-only CSR can not be written by the CSR instructions.
  98
  99 @cindex @samp{-mno-csr-check} option, RISC-V
 100 @item -mno-csr-check
 101 Don't do CSR checking.
 102
 103 @cindex @samp{-mlittle-endian} option, RISC-V
 104 @item -mlittle-endian
 105 Generate code for a little endian machine.
 106
 107 @cindex @samp{-mbig-endian} option, RISC-V
 108 @item -mbig-endian
 109 Generate code for a big endian machine.
 110 @end table
 111 @c man end
 112
 113 @node RISC-V-Directives
 114 @section RISC-V Directives
 115 @cindex machine directives, RISC-V
 116 @cindex RISC-V machine directives
 117
 118 The following table lists all available RISC-V specific directives.
 119
 120 @table @code
 121
 122 @cindex @code{align} directive
 123 @item .align @var{size-log-2}
 124 Align to the given boundary, with the size given as log2 the number of bytes to
 125 align to.
 126
 127 @cindex Data directives
 128 @item .half @var{value}
 129 @itemx .word @var{value}
 130 @itemx .dword @var{value}
 131 Emits a half-word, word, or double-word value at the current position.
 132
 133 @cindex DTP-relative data directives
 134 @item .dtprelword @var{value}
 135 @itemx .dtpreldword @var{value}
 136 Emits a DTP-relative word (or double-word) at the current position.  This is
 137 meant to be used by the compiler in shared libraries for DWARF debug info for
 138 thread local variables.
 139
 140 @cindex BSS directive
 141 @item .bss
 142 Sets the current section to the BSS section.
 143
 144 @cindex LEB128 directives
 145 @item .uleb128 @var{value}
 146 @itemx .sleb128 @var{value}
 147 Emits a signed or unsigned LEB128 value at the current position.  This only
 148 accepts constant expressions, because symbol addresses can change with
 149 relaxation, and we don't support relocations to modify LEB128 values at link
 150 time.
 151
 152 @cindex Option directive
 153 @cindex @code{option} directive
 154 @item .option @var{argument}
 155 Modifies RISC-V specific assembler options inline with the assembly code.
 156 This is used when particular instruction sequences must be assembled with a
 157 specific set of options.  For example, since we relax addressing sequences to
 158 shorter GP-relative sequences when possible the initial load of GP must not be
 159 relaxed and should be emitted as something like
 160
 161 @smallexample
 162         .option push
 163         .option norelax
 164         la gp, __global_pointer$
 165         .option pop
 166 @end smallexample
 167
 168 in order to produce after linker relaxation the expected
 169
 170 @smallexample
 171         auipc gp, %pcrel_hi(__global_pointer$)
 172         addi gp, gp, %pcrel_lo(__global_pointer$)
 173 @end smallexample
 174
 175 instead of just
 176
 177 @smallexample
 178         addi gp, gp, 0
 179 @end smallexample
 180
 181 It's not expected that options are changed in this manner during regular use,
 182 but there are a handful of esoteric cases like the one above where users need
 183 to disable particular features of the assembler for particular code sequences.
 184 The complete list of option arguments is shown below:
 185
 186 @table @code
 187 @item push
 188 @itemx pop
 189 Pushes or pops the current option stack.  These should be used whenever
 190 changing an option in line with assembly code in order to ensure the user's
 191 command-line options are respected for the bulk of the file being assembled.
 192
 193 @item rvc
 194 @itemx norvc
 195 Enables or disables the generation of compressed instructions.  Instructions
 196 are opportunistically compressed by the RISC-V assembler when possible, but
 197 sometimes this behavior is not desirable.
 198
 199 @item pic
 200 @itemx nopic
 201 Enables or disables position-independent code generation.  Unless you really
 202 know what you're doing, this should only be at the top of a file.
 203
 204 @item relax
 205 @itemx norelax
 206 Enables or disables relaxation.  The RISC-V assembler and linker
 207 opportunistically relax some code sequences, but sometimes this behavior is not
 208 desirable.
 209 @end table
 210
 211 @item csr-check
 212 @itemx no-csr-check
 213 Enables or disables the CSR checking.
 214
 215 @cindex INSN directives
 216 @item .insn @var{value}
 217 @itemx .insn @var{value}
 218 This directive permits the numeric representation of an instructions
 219 and makes the assembler insert the operands according to one of the
 220 instruction formats for @samp{.insn} (@ref{RISC-V-Formats}).
 221 For example, the instruction @samp{add a0, a1, a2} could be written as
 222 @samp{.insn r 0x33, 0, 0, a0, a1, a2}.
 223
 224 @cindex @code{.attribute} directive, RISC-V
 225 @item .attribute @var{tag}, @var{value}
 226 Set the object attribute @var{tag} to @var{value}.
 227
 228 The @var{tag} is either an attribute number, or one of the following:
 229 @code{Tag_RISCV_arch}, @code{Tag_RISCV_stack_align},
 230 @code{Tag_RISCV_unaligned_access}, @code{Tag_RISCV_priv_spec},
 231 @code{Tag_RISCV_priv_spec_minor}, @code{Tag_RISCV_priv_spec_revision}.
 232
 233 @end table
 234
 235 @node RISC-V-Modifiers
 236 @section RISC-V Assembler Modifiers
 237
 238 The RISC-V assembler supports following modifiers for relocatable addresses
 239 used in RISC-V instruction operands.  However, we also support some pseudo
 240 instructions that are easier to use than these modifiers.
 241
 242 @table @code
 243 @item %lo(@var{symbol})
 244 The low 12 bits of absolute address for @var{symbol}.
 245
 246 @item %hi(@var{symbol})
 247 The high 20 bits of absolute address for @var{symbol}.  This is usually
 248 used with the %lo modifier to represent a 32-bit absolute address.
 249
 250 @smallexample
 251         lui        a0, %hi(@var{symbol})     // R_RISCV_HI20
 252         addi       a0, a0, %lo(@var{symbol}) // R_RISCV_LO12_I
 253
 254         lui        a0, %hi(@var{symbol})     // R_RISCV_HI20
 255         load/store a0, %lo(@var{symbol})(a0) // R_RISCV_LO12_I/S
 256 @end smallexample
 257
 258 @item %pcrel_lo(@var{label})
 259 The low 12 bits of relative address between pc and @var{symbol}.
 260 The @var{symbol} is related to the high part instruction which is marked
 261 by @var{label}.
 262
 263 @item %pcrel_hi(@var{symbol})
 264 The high 20 bits of relative address between pc and @var{symbol}.
 265 This is usually used with the %pcrel_lo modifier to represent a +/-2GB
 266 pc-relative range.
 267
 268 @smallexample
 269 @var{label}:
 270         auipc      a0, %pcrel_hi(@var{symbol})    // R_RISCV_PCREL_HI20
 271         addi       a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I
 272
 273 @var{label}:
 274         auipc      a0, %pcrel_hi(@var{symbol})    // R_RISCV_PCREL_HI20
 275         load/store a0, %pcrel_lo(@var{label})(a0) // R_RISCV_PCREL_LO12_I/S
 276 @end smallexample
 277
 278 Or you can use the pseudo lla/lw/sw/... instruction to do this.
 279
 280 @smallexample
 281         lla  a0, @var{symbol}
 282 @end smallexample
 283
 284 @item %got_pcrel_hi(@var{symbol})
 285 The high 20 bits of relative address between pc and the GOT entry of
 286 @var{symbol}.  This is usually used with the %pcrel_lo modifier to access
 287 the GOT entry.
 288
 289 @smallexample
 290 @var{label}:
 291         auipc      a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20
 292         addi       a0, a0, %pcrel_lo(@var{label})  // R_RISCV_PCREL_LO12_I
 293
 294 @var{label}:
 295         auipc      a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20
 296         load/store a0, %pcrel_lo(@var{label})(a0)  // R_RISCV_PCREL_LO12_I/S
 297 @end smallexample
 298
 299 Also, the pseudo la instruction with PIC has similar behavior.
 300
 301 @item %tprel_add(@var{symbol})
 302 This is used purely to associate the R_RISCV_TPREL_ADD relocation for
 303 TLS relaxation.  This one is only valid as the fourth operand to the normally
 304 3 operand add instruction.
 305
 306 @item %tprel_lo(@var{symbol})
 307 The low 12 bits of relative address between tp and @var{symbol}.
 308
 309 @item %tprel_hi(@var{symbol})
 310 The high 20 bits of relative address between tp and @var{symbol}.  This is
 311 usually used with the %tprel_lo and %tprel_add modifiers to access the thread
 312 local variable @var{symbol} in TLS Local Exec.
 313
 314 @smallexample
 315         lui        a5, %tprel_hi(@var{symbol})          // R_RISCV_TPREL_HI20
 316         add        a5, a5, tp, %tprel_add(@var{symbol}) // R_RISCV_TPREL_ADD
 317         load/store t0, %tprel_lo(@var{symbol})(a5)      // R_RISCV_TPREL_LO12_I/S
 318 @end smallexample
 319
 320 @item %tls_ie_pcrel_hi(@var{symbol})
 321 The high 20 bits of relative address between pc and GOT entry.  It is
 322 usually used with the %pcrel_lo modifier to access the thread local
 323 variable @var{symbol} in TLS Initial Exec.
 324
 325 @smallexample
 326         la.tls.ie  a5, @var{symbol}
 327         add        a5, a5, tp
 328         load/store t0, 0(a5)
 329 @end smallexample
 330
 331 The pseudo la.tls.ie instruction can be expended to
 332
 333 @smallexample
 334 @var{label}:
 335         auipc a5, %tls_ie_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GOT_HI20
 336         load  a5, %pcrel_lo(@var{label})(a5)     // R_RISCV_PCREL_LO12_I
 337 @end smallexample
 338
 339 @item %tls_gd_pcrel_hi(@var{symbol})
 340 The high 20 bits of relative address between pc and GOT entry.  It is
 341 usually used with the %pcrel_lo modifier to access the thread local variable
 342 @var{symbol} in TLS Global Dynamic.
 343
 344 @smallexample
 345         la.tls.gd  a0, @var{symbol}
 346         call       __tls_get_addr@@plt
 347         mv         a5, a0
 348         load/store t0, 0(a5)
 349 @end smallexample
 350
 351 The pseudo la.tls.gd instruction can be expended to
 352
 353 @smallexample
 354 @var{label}:
 355         auipc a0, %tls_gd_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GD_HI20
 356         addi  a0, a0, %pcrel_lo(@var{label})     // R_RISCV_PCREL_LO12_I
 357 @end smallexample
 358
 359 @end table
 360
 361 @node RISC-V-Formats
 362 @section RISC-V Instruction Formats
 363 @cindex instruction formats, risc-v
 364 @cindex RISC-V instruction formats
 365
 366 The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 15
 367 instruction formats where some of the formats have multiple variants.
 368 For the @samp{.insn} pseudo directive the assembler recognizes some
 369 of the formats.
 370 Typically, the most general variant of the instruction format is used
 371 by the @samp{.insn} directive.
 372
 373 The following table lists the abbreviations used in the table of
 374 instruction formats:
 375
 376 @display
 377 @multitable @columnfractions .15 .40
 378 @item opcode @tab Unsigned immediate or opcode name for 7-bits opcode.
 379 @item opcode2 @tab Unsigned immediate or opcode name for 2-bits opcode.
 380 @item func7 @tab Unsigned immediate for 7-bits function code.
 381 @item func6 @tab Unsigned immediate for 6-bits function code.
 382 @item func4 @tab Unsigned immediate for 4-bits function code.
 383 @item func3 @tab Unsigned immediate for 3-bits function code.
 384 @item func2 @tab Unsigned immediate for 2-bits function code.
 385 @item rd @tab Destination register number for operand x, can be GPR or FPR.
 386 @item rd' @tab Destination register number for operand x,
 387 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
 388 @item rs1 @tab First source register number for operand x, can be GPR or FPR.
 389 @item rs1' @tab First source register number for operand x,
 390 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
 391 @item rs2 @tab Second source register number for operand x, can be GPR or FPR.
 392 @item rs2' @tab Second source register number for operand x,
 393 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
 394 @item simm12 @tab Sign-extended 12-bit immediate for operand x.
 395 @item simm20 @tab Sign-extended 20-bit immediate for operand x.
 396 @item simm6 @tab Sign-extended 6-bit immediate for operand x.
 397 @item uimm5 @tab Unsigned 5-bit immediate for operand x.
 398 @item uimm6 @tab Unsigned 6-bit immediate for operand x.
 399 @item uimm8 @tab Unsigned 8-bit immediate for operand x.
 400 @item symbol @tab Symbol or lable reference for operand x.
 401 @end multitable
 402 @end display
 403
 404 The following table lists all available opcode name:
 405
 406 @table @code
 407 @item C0
 408 @item C1
 409 @item C2
 410 Opcode space for compressed instructions.
 411
 412 @item LOAD
 413 Opcode space for load instructions.
 414
 415 @item LOAD_FP
 416 Opcode space for floating-point load instructions.
 417
 418 @item STORE
 419 Opcode space for store instructions.
 420
 421 @item STORE_FP
 422 Opcode space for floating-point store instructions.
 423
 424 @item AUIPC
 425 Opcode space for auipc instruction.
 426
 427 @item LUI
 428 Opcode space for lui instruction.
 429
 430 @item BRANCH
 431 Opcode space for branch instructions.
 432
 433 @item JAL
 434 Opcode space for jal instruction.
 435
 436 @item JALR
 437 Opcode space for jalr instruction.
 438
 439 @item OP
 440 Opcode space for ALU instructions.
 441
 442 @item OP_32
 443 Opcode space for 32-bits ALU instructions.
 444
 445 @item OP_IMM
 446 Opcode space for ALU with immediate instructions.
 447
 448 @item OP_IMM_32
 449 Opcode space for 32-bits ALU with immediate instructions.
 450
 451 @item OP_FP
 452 Opcode space for floating-point operation instructions.
 453
 454 @item MADD
 455 Opcode space for madd instruction.
 456
 457 @item MSUB
 458 Opcode space for msub instruction.
 459
 460 @item NMADD
 461 Opcode space for nmadd instruction.
 462
 463 @item NMSUB
 464 Opcode space for msub instruction.
 465
 466 @item AMO
 467 Opcode space for atomic memory operation instructions.
 468
 469 @item MISC_MEM
 470 Opcode space for misc instructions.
 471
 472 @item SYSTEM
 473 Opcode space for system instructions.
 474
 475 @item CUSTOM_0
 476 @item CUSTOM_1
 477 @item CUSTOM_2
 478 @item CUSTOM_3
 479 Opcode space for customize instructions.
 480
 481 @end table
 482
 483 An instruction is two or four bytes in length and must be aligned
 484 on a 2 byte boundary. The first two bits of the instruction specify the
 485 length of the instruction, 00, 01 and 10 indicates a two byte instruction,
 486 11 indicates a four byte instruction.
 487
 488 The following table lists the RISC-V instruction formats that are available
 489 with the @samp{.insn} pseudo directive:
 490
 491 @table @code
 492 @item R type: .insn r opcode6, func3, func7, rd, rs1, rs2
 493 @verbatim
 494 +-------+-----+-----+-------+----+---------+
 495 | func7 | rs2 | rs1 | func3 | rd | opcode6 |
 496 +-------+-----+-----+-------+----+---------+
 497 31      25    20    15      12   7        0
 498 @end verbatim
 499
 500 @item R type with 4 register operands: .insn r opcode6, func3, func2, rd, rs1, rs2, rs3
 501 @itemx R4 type: .insn r4 opcode6, func3, func2, rd, rs1, rs2, rs3
 502 @verbatim
 503 +-----+-------+-----+-----+-------+----+---------+
 504 | rs3 | func2 | rs2 | rs1 | func3 | rd | opcode6 |
 505 +-----+-------+-----+-----+-------+----+---------+
 506 31    27      25    20    15      12   7         0
 507 @end verbatim
 508
 509 @item I type: .insn i opcode6, func3, rd, rs1, simm12
 510 @itemx I type: .insn i opcode6, func3, rd, simm12(rs1)
 511 @verbatim
 512 +--------------+-----+-------+----+---------+
 513 | simm12[11:0] | rs1 | func3 | rd | opcode6 |
 514 +--------------+-----+-------+----+---------+
 515 31             20    15      12   7         0
 516 @end verbatim
 517
 518 @item S type: .insn s opcode6, func3, rs2, simm12(rs1)
 519 @verbatim
 520 +--------------+-----+-----+-------+-------------+---------+
 521 | simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode6 |
 522 +--------------+-----+-----+-------+-------------+---------+
 523 31             25    20    15      12            7         0
 524 @end verbatim
 525
 526 @item B type: .insn s opcode6, func3, rs1, rs2, symbol
 527 @itemx SB type: .insn sb opcode6, func3, rs1, rs2, symbol
 528 @verbatim
 529 +-----------------+-----+-----+-------+----------------+---------+
 530 | simm12[12|10:5] | rs2 | rs1 | func3 | simm12[4:1|11] | opcode6 |
 531 +-----------------+-----+-----+-------+----------------+---------+
 532 31                25    20    15      12               7         0
 533 @end verbatim
 534
 535 @item U type: .insn u opcode6, rd, simm20
 536 @verbatim
 537 +--------------------------+----+---------+
 538 | simm20[20|10:1|11|19:12] | rd | opcode6 |
 539 +--------------------------+----+---------+
 540 31                         12   7         0
 541 @end verbatim
 542
 543 @item J type: .insn j opcode6, rd, symbol
 544 @itemx UJ type: .insn uj opcode6, rd, symbol
 545 @verbatim
 546 +------------+--------------+------------+---------------+----+---------+
 547 | simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode6 |
 548 +------------+--------------+------------+---------------+----+---------+
 549 31           30             21           20              12   7         0
 550 @end verbatim
 551
 552 @item CR type: .insn cr opcode2, func4, rd, rs2
 553 @verbatim
 554 +-------+--------+-----+---------+
 555 | func4 | rd/rs1 | rs2 | opcode2 |
 556 +-------+--------+-----+---------+
 557 15      12       7     2        0
 558 @end verbatim
 559
 560 @item CI type: .insn ci opcode2, func3, rd, simm6
 561 @verbatim
 562 +-------+----------+--------+------------+---------+
 563 | func3 | simm6[5] | rd/rs1 | simm6[4:0] | opcode2 |
 564 +-------+----------+--------+------------+---------+
 565 15      13         12       7            2         0
 566 @end verbatim
 567
 568 @item CIW type: .insn ciw opcode2, func3, rd', uimm8
 569 @verbatim
 570 +-------+------------+-----+---------+
 571 | func3 | uimm8[7:0] | rd' | opcode2 |
 572 +-------+-------- ---+-----+---------+
 573 15      13           5     2         0
 574 @end verbatim
 575
 576 @item CSS type: .insn css opcode2, func3, rd, uimm6
 577 @verbatim
 578 +-------+------------+----+---------+
 579 | func3 | uimm6[5:0] | rd | opcode2 |
 580 +-------+------------+----+---------+
 581 15      13           7    2         0
 582 @end verbatim
 583
 584 @item CL type: .insn cl opcode2, func3, rd', uimm5(rs1')
 585 @verbatim
 586 +-------+------------+------+------------+------+---------+
 587 | func3 | uimm5[4:2] | rs1' | uimm5[1:0] |  rd' | opcode2 |
 588 +-------+------------+------+------------+------+---------+
 589 15      13           10     7            5      2         0
 590 @end verbatim
 591
 592 @item CS type: .insn cs opcode2, func3, rs2', uimm5(rs1')
 593 @verbatim
 594 +-------+------------+------+------------+------+---------+
 595 | func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rs2' | opcode2 |
 596 +-------+------------+------+------------+------+---------+
 597 15      13           10     7            5      2         0
 598 @end verbatim
 599
 600 @item CA type: .insn ca opcode2, func6, func2, rd', rs2'
 601 @verbatim
 602 +-- ----+----------+-------+------+---------+
 603 | func6 | rd'/rs1' | func2 | rs2' | opcode2 |
 604 +-------+----------+-------+------+---------+
 605 15      10         7       5      2         0
 606 @end verbatim
 607
 608 @item CB type: .insn cb opcode2, func3, rs1', symbol
 609 @verbatim
 610 +-------+--------------+------+------------------+---------+
 611 | func3 | simm8[8|4:3] | rs1' | simm8[7:6|2:1|5] | opcode2 |
 612 +-------+--------------+------+------------------+---------+
 613 15      13             10     7                  2         0
 614 @end verbatim
 615
 616 @item CJ type: .insn cj opcode2, symbol
 617 @verbatim
 618 +-------+-------------------------------+---------+
 619 | func3 | simm11[11|4|9:8|10|6|7|3:1|5] | opcode2 |
 620 +-------+-------------------------------+---------+
 621 15      13                              2         0
 622 @end verbatim
 623
 624
 625 @end table
 626
 627 For the complete list of all instruction format variants see
 628 The RISC-V Instruction Set Manual Volume I: User-Level ISA.
 629
 630 @node RISC-V-ATTRIBUTE
 631 @section RISC-V Object Attribute
 632 @cindex Object Attribute, RISC-V
 633
 634 RISC-V attributes have a string value if the tag number is odd and an integer
 635 value if the tag number is even.
 636
 637 @table @r
 638 @item Tag_RISCV_stack_align (4)
 639 Tag_RISCV_strict_align records the N-byte stack alignment for this object.  The
 640 default value is 16 for RV32I or RV64I, and 4 for RV32E.
 641
 642 The smallest value will be used if object files with different
 643 Tag_RISCV_stack_align values are merged.
 644
 645 @item Tag_RISCV_arch (5)
 646 Tag_RISCV_arch contains a string for the target architecture taken from the
 647 option @option{-march}.  Different architectures will be integrated into a
 648 superset when object files are merged.
 649
 650 Note that the version information of the target architecture must be presented
 651 explicitly in the attribute and abbreviations must be expanded.  The version
 652 information, if not given by @option{-march}, must be in accordance with the
 653 default specified by the tool.  For example, the architecture @code{RV32I} has
 654 to be recorded in the attribute as @code{RV32I2P0} in which @code{2P0} stands
 655 for the default version of its base ISA.  On the other hand, the architecture
 656 @code{RV32G} has to be presented as @code{RV32I2P0_M2P0_A2P0_F2P0_D2P0} in
 657 which the abbreviation @code{G} is expanded to the @code{IMAFD} combination
 658 with default versions of the standard extensions.
 659
 660 @item Tag_RISCV_unaligned_access (6)
 661 Tag_RISCV_unaligned_access is 0 for files that do not allow any unaligned
 662 memory accesses, and 1 for files that do allow unaligned memory accesses.
 663
 664 @item Tag_RISCV_priv_spec (8)
 665 @item Tag_RISCV_priv_spec_minor (10)
 666 @item Tag_RISCV_priv_spec_revision (12)
 667 Tag_RISCV_priv_spec contains the major/minor/revision version information of
 668 the privileged specification.  It will report errors if object files of
 669 different privileged specification versions are merged.
 670
 671 @end table