gas/doc/c-sh.texi

   1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001
   2 @c Free Software Foundation, Inc.
   3 @c This is part of the GAS manual.
   4 @c For copying conditions, see the file as.texinfo.
   5 @page
   6 @node SH-Dependent
   7 @chapter Renesas / SuperH SH Dependent Features
   8
   9 @cindex SH support
  10 @menu
  11 * SH Options::              Options
  12 * SH Syntax::               Syntax
  13 * SH Floating Point::       Floating Point
  14 * SH Directives::           SH Machine Directives
  15 * SH Opcodes::              Opcodes
  16 @end menu
  17
  18 @node SH Options
  19 @section Options
  20
  21 @cindex SH options
  22 @cindex options, SH
  23 @code{@value{AS}} has following command-line options for the Renesas
  24 (formerly Hitachi) / SuperH SH family.
  25
  26 @table @code
  27 @kindex -little
  28 @kindex -big
  29 @kindex -relax
  30 @kindex -small
  31 @kindex -dsp
  32
  33 @item -little
  34 Generate little endian code.
  35
  36 @item -big
  37 Generate big endian code.
  38
  39 @item -relax
  40 Alter jump instructions for long displacements.
  41
  42 @item -small
  43 Align sections to 4 byte boundaries, not 16.
  44
  45 @item -dsp
  46 Enable sh-dsp insns, and disable sh3e / sh4 insns.
  47
  48 @end table
  49
  50 @node SH Syntax
  51 @section Syntax
  52
  53 @menu
  54 * SH-Chars::                Special Characters
  55 * SH-Regs::                 Register Names
  56 * SH-Addressing::           Addressing Modes
  57 @end menu
  58
  59 @node SH-Chars
  60 @subsection Special Characters
  61
  62 @cindex line comment character, SH
  63 @cindex SH line comment character
  64 @samp{!} is the line comment character.
  65
  66 @cindex line separator, SH
  67 @cindex statement separator, SH
  68 @cindex SH line separator
  69 You can use @samp{;} instead of a newline to separate statements.
  70
  71 @cindex symbol names, @samp{$} in
  72 @cindex @code{$} in symbol names
  73 Since @samp{$} has no special meaning, you may use it in symbol names.
  74
  75 @node SH-Regs
  76 @subsection Register Names
  77
  78 @cindex SH registers
  79 @cindex registers, SH
  80 You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
  81 @samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
  82 @samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
  83 and @samp{r15} to refer to the SH registers.
  84
  85 The SH also has these control registers:
  86
  87 @table @code
  88 @item pr
  89 procedure register (holds return address)
  90
  91 @item pc
  92 program counter
  93
  94 @item mach
  95 @itemx macl
  96 high and low multiply accumulator registers
  97
  98 @item sr
  99 status register
 100
 101 @item gbr
 102 global base register
 103
 104 @item vbr
 105 vector base register (for interrupt vectors)
 106 @end table
 107
 108 @node SH-Addressing
 109 @subsection Addressing Modes
 110
 111 @cindex addressing modes, SH
 112 @cindex SH addressing modes
 113 @code{@value{AS}} understands the following addressing modes for the SH.
 114 @code{R@var{n}} in the following refers to any of the numbered
 115 registers, but @emph{not} the control registers.
 116
 117 @table @code
 118 @item R@var{n}
 119 Register direct
 120
 121 @item @@R@var{n}
 122 Register indirect
 123
 124 @item @@-R@var{n}
 125 Register indirect with pre-decrement
 126
 127 @item @@R@var{n}+
 128 Register indirect with post-increment
 129
 130 @item @@(@var{disp}, R@var{n})
 131 Register indirect with displacement
 132
 133 @item @@(R0, R@var{n})
 134 Register indexed
 135
 136 @item @@(@var{disp}, GBR)
 137 @code{GBR} offset
 138
 139 @item @@(R0, GBR)
 140 GBR indexed
 141
 142 @item @var{addr}
 143 @itemx @@(@var{disp}, PC)
 144 PC relative address (for branch or for addressing memory).  The
 145 @code{@value{AS}} implementation allows you to use the simpler form
 146 @var{addr} anywhere a PC relative address is called for; the alternate
 147 form is supported for compatibility with other assemblers.
 148
 149 @item #@var{imm}
 150 Immediate data
 151 @end table
 152
 153 @node SH Floating Point
 154 @section Floating Point
 155
 156 @cindex floating point, SH (@sc{ieee})
 157 @cindex SH floating point (@sc{ieee})
 158 The SH family has no hardware floating point, but the @code{.float}
 159 directive generates @sc{ieee} floating-point numbers for compatibility
 160 with other development tools.
 161
 162 @node SH Directives
 163 @section SH Machine Directives
 164
 165 @cindex SH machine directives
 166 @cindex machine directives, SH
 167 @cindex @code{uaword} directive, SH
 168 @cindex @code{ualong} directive, SH
 169
 170 @table @code
 171 @item uaword
 172 @itemx ualong
 173 @code{@value{AS}} will issue a warning when a misaligned @code{.word} or
 174 @code{.long} directive is used.  You may use @code{.uaword} or
 175 @code{.ualong} to indicate that the value is intentionally misaligned.
 176 @end table
 177
 178 @node SH Opcodes
 179 @section Opcodes
 180
 181 @cindex SH opcode summary
 182 @cindex opcode summary, SH
 183 @cindex mnemonics, SH
 184 @cindex instruction summary, SH
 185 For detailed information on the SH machine instruction set, see
 186 @cite{SH-Microcomputer User's Manual} (Renesas) or
 187 @cite{SH-4 32-bit CPU Core Architecture} (SuperH) and
 188 @cite{SuperH (SH) 64-Bit RISC Series} (SuperH).
 189
 190 @code{@value{AS}} implements all the standard SH opcodes.  No additional
 191 pseudo-instructions are needed on this family.  Note, however, that
 192 because @code{@value{AS}} supports a simpler form of PC-relative
 193 addressing, you may simply write (for example)
 194
 195 @example
 196 mov.l  bar,r0
 197 @end example
 198
 199 @noindent
 200 where other assemblers might require an explicit displacement to
 201 @code{bar} from the program counter:
 202
 203 @example
 204 mov.l  @@(@var{disp}, PC)
 205 @end example
 206
 207 @ifset SMALL
 208 @c this table, due to the multi-col faking and hardcoded order, looks silly
 209 @c except in smallbook.  See comments below "@set SMALL" near top of this file.
 210
 211 Here is a summary of SH opcodes:
 212
 213 @page
 214 @smallexample
 215 @i{Legend:}
 216 Rn        @r{a numbered register}
 217 Rm        @r{another numbered register}
 218 #imm      @r{immediate data}
 219 disp      @r{displacement}
 220 disp8     @r{8-bit displacement}
 221 disp12    @r{12-bit displacement}
 222
 223 add #imm,Rn                    lds.l @@Rn+,PR
 224 add Rm,Rn                      mac.w @@Rm+,@@Rn+
 225 addc Rm,Rn                     mov #imm,Rn
 226 addv Rm,Rn                     mov Rm,Rn
 227 and #imm,R0                    mov.b Rm,@@(R0,Rn)
 228 and Rm,Rn                      mov.b Rm,@@-Rn
 229 and.b #imm,@@(R0,GBR)           mov.b Rm,@@Rn
 230 bf disp8                       mov.b @@(disp,Rm),R0
 231 bra disp12                     mov.b @@(disp,GBR),R0
 232 bsr disp12                     mov.b @@(R0,Rm),Rn
 233 bt disp8                       mov.b @@Rm+,Rn
 234 clrmac                         mov.b @@Rm,Rn
 235 clrt                           mov.b R0,@@(disp,Rm)
 236 cmp/eq #imm,R0                 mov.b R0,@@(disp,GBR)
 237 cmp/eq Rm,Rn                   mov.l Rm,@@(disp,Rn)
 238 cmp/ge Rm,Rn                   mov.l Rm,@@(R0,Rn)
 239 cmp/gt Rm,Rn                   mov.l Rm,@@-Rn
 240 cmp/hi Rm,Rn                   mov.l Rm,@@Rn
 241 cmp/hs Rm,Rn                   mov.l @@(disp,Rn),Rm
 242 cmp/pl Rn                      mov.l @@(disp,GBR),R0
 243 cmp/pz Rn                      mov.l @@(disp,PC),Rn
 244 cmp/str Rm,Rn                  mov.l @@(R0,Rm),Rn
 245 div0s Rm,Rn                    mov.l @@Rm+,Rn
 246 div0u                          mov.l @@Rm,Rn
 247 div1 Rm,Rn                     mov.l R0,@@(disp,GBR)
 248 exts.b Rm,Rn                   mov.w Rm,@@(R0,Rn)
 249 exts.w Rm,Rn                   mov.w Rm,@@-Rn
 250 extu.b Rm,Rn                   mov.w Rm,@@Rn
 251 extu.w Rm,Rn                   mov.w @@(disp,Rm),R0
 252 jmp @@Rn                        mov.w @@(disp,GBR),R0
 253 jsr @@Rn                        mov.w @@(disp,PC),Rn
 254 ldc Rn,GBR                     mov.w @@(R0,Rm),Rn
 255 ldc Rn,SR                      mov.w @@Rm+,Rn
 256 ldc Rn,VBR                     mov.w @@Rm,Rn
 257 ldc.l @@Rn+,GBR                 mov.w R0,@@(disp,Rm)
 258 ldc.l @@Rn+,SR                  mov.w R0,@@(disp,GBR)
 259 ldc.l @@Rn+,VBR                 mova @@(disp,PC),R0
 260 lds Rn,MACH                    movt Rn
 261 lds Rn,MACL                    muls Rm,Rn
 262 lds Rn,PR                      mulu Rm,Rn
 263 lds.l @@Rn+,MACH                neg Rm,Rn
 264 lds.l @@Rn+,MACL                negc Rm,Rn
 265 @page
 266 nop                            stc VBR,Rn
 267 not Rm,Rn                      stc.l GBR,@@-Rn
 268 or #imm,R0                     stc.l SR,@@-Rn
 269 or Rm,Rn                       stc.l VBR,@@-Rn
 270 or.b #imm,@@(R0,GBR)            sts MACH,Rn
 271 rotcl Rn                       sts MACL,Rn
 272 rotcr Rn                       sts PR,Rn
 273 rotl Rn                        sts.l MACH,@@-Rn
 274 rotr Rn                        sts.l MACL,@@-Rn
 275 rte                            sts.l PR,@@-Rn
 276 rts                            sub Rm,Rn
 277 sett                           subc Rm,Rn
 278 shal Rn                        subv Rm,Rn
 279 shar Rn                        swap.b Rm,Rn
 280 shll Rn                        swap.w Rm,Rn
 281 shll16 Rn                      tas.b @@Rn
 282 shll2 Rn                       trapa #imm
 283 shll8 Rn                       tst #imm,R0
 284 shlr Rn                        tst Rm,Rn
 285 shlr16 Rn                      tst.b #imm,@@(R0,GBR)
 286 shlr2 Rn                       xor #imm,R0
 287 shlr8 Rn                       xor Rm,Rn
 288 sleep                          xor.b #imm,@@(R0,GBR)
 289 stc GBR,Rn                     xtrct Rm,Rn
 290 stc SR,Rn
 291 @end smallexample
 292 @end ifset
 293
 294 @ifset Renesas-all
 295 @ifclear GENERIC
 296 @raisesections
 297 @end ifclear
 298 @end ifset
 299