1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001
2 @c Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
7 @chapter Renesas SH Dependent Features
11 * SH Options:: Options
13 * SH Floating Point:: Floating Point
14 * SH Directives:: SH Machine Directives
15 * SH Opcodes:: Opcodes
23 @code{@value{AS}} has following command-line options for the Renesas
24 (formerly Hitachi) SH family.
34 Generate little endian code.
37 Generate big endian code.
40 Alter jump instructions for long displacements.
43 Align sections to 4 byte boundaries, not 16.
46 Enable sh-dsp insns, and disable sh3e / sh4 insns.
54 * SH-Chars:: Special Characters
55 * SH-Regs:: Register Names
56 * SH-Addressing:: Addressing Modes
60 @subsection Special Characters
62 @cindex line comment character, SH
63 @cindex SH line comment character
64 @samp{!} is the line comment character.
66 @cindex line separator, SH
67 @cindex statement separator, SH
68 @cindex SH line separator
69 You can use @samp{;} instead of a newline to separate statements.
71 @cindex symbol names, @samp{$} in
72 @cindex @code{$} in symbol names
73 Since @samp{$} has no special meaning, you may use it in symbol names.
76 @subsection Register Names
80 You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
81 @samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
82 @samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
83 and @samp{r15} to refer to the SH registers.
85 The SH also has these control registers:
89 procedure register (holds return address)
96 high and low multiply accumulator registers
105 vector base register (for interrupt vectors)
109 @subsection Addressing Modes
111 @cindex addressing modes, SH
112 @cindex SH addressing modes
113 @code{@value{AS}} understands the following addressing modes for the SH.
114 @code{R@var{n}} in the following refers to any of the numbered
115 registers, but @emph{not} the control registers.
125 Register indirect with pre-decrement
128 Register indirect with post-increment
130 @item @@(@var{disp}, R@var{n})
131 Register indirect with displacement
133 @item @@(R0, R@var{n})
136 @item @@(@var{disp}, GBR)
143 @itemx @@(@var{disp}, PC)
144 PC relative address (for branch or for addressing memory). The
145 @code{@value{AS}} implementation allows you to use the simpler form
146 @var{addr} anywhere a PC relative address is called for; the alternate
147 form is supported for compatibility with other assemblers.
153 @node SH Floating Point
154 @section Floating Point
156 @cindex floating point, SH (@sc{ieee})
157 @cindex SH floating point (@sc{ieee})
158 The SH family has no hardware floating point, but the @code{.float}
159 directive generates @sc{ieee} floating-point numbers for compatibility
160 with other development tools.
163 @section SH Machine Directives
165 @cindex SH machine directives
166 @cindex machine directives, SH
167 @cindex @code{uaword} directive, SH
168 @cindex @code{ualong} directive, SH
173 @code{@value{AS}} will issue a warning when a misaligned @code{.word} or
174 @code{.long} directive is used. You may use @code{.uaword} or
175 @code{.ualong} to indicate that the value is intentionally misaligned.
181 @cindex SH opcode summary
182 @cindex opcode summary, SH
183 @cindex mnemonics, SH
184 @cindex instruction summary, SH
185 For detailed information on the SH machine instruction set, see
186 @cite{SH-Microcomputer User's Manual} (Renesas).
188 @code{@value{AS}} implements all the standard SH opcodes. No additional
189 pseudo-instructions are needed on this family. Note, however, that
190 because @code{@value{AS}} supports a simpler form of PC-relative
191 addressing, you may simply write (for example)
198 where other assemblers might require an explicit displacement to
199 @code{bar} from the program counter:
202 mov.l @@(@var{disp}, PC)
206 @c this table, due to the multi-col faking and hardcoded order, looks silly
207 @c except in smallbook. See comments below "@set SMALL" near top of this file.
209 Here is a summary of SH opcodes:
214 Rn @r{a numbered register}
215 Rm @r{another numbered register}
216 #imm @r{immediate data}
217 disp @r{displacement}
218 disp8 @r{8-bit displacement}
219 disp12 @r{12-bit displacement}
221 add #imm,Rn lds.l @@Rn+,PR
222 add Rm,Rn mac.w @@Rm+,@@Rn+
223 addc Rm,Rn mov #imm,Rn
225 and #imm,R0 mov.b Rm,@@(R0,Rn)
226 and Rm,Rn mov.b Rm,@@-Rn
227 and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
228 bf disp8 mov.b @@(disp,Rm),R0
229 bra disp12 mov.b @@(disp,GBR),R0
230 bsr disp12 mov.b @@(R0,Rm),Rn
231 bt disp8 mov.b @@Rm+,Rn
233 clrt mov.b R0,@@(disp,Rm)
234 cmp/eq #imm,R0 mov.b R0,@@(disp,GBR)
235 cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn)
236 cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn)
237 cmp/gt Rm,Rn mov.l Rm,@@-Rn
238 cmp/hi Rm,Rn mov.l Rm,@@Rn
239 cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm
240 cmp/pl Rn mov.l @@(disp,GBR),R0
241 cmp/pz Rn mov.l @@(disp,PC),Rn
242 cmp/str Rm,Rn mov.l @@(R0,Rm),Rn
243 div0s Rm,Rn mov.l @@Rm+,Rn
245 div1 Rm,Rn mov.l R0,@@(disp,GBR)
246 exts.b Rm,Rn mov.w Rm,@@(R0,Rn)
247 exts.w Rm,Rn mov.w Rm,@@-Rn
248 extu.b Rm,Rn mov.w Rm,@@Rn
249 extu.w Rm,Rn mov.w @@(disp,Rm),R0
250 jmp @@Rn mov.w @@(disp,GBR),R0
251 jsr @@Rn mov.w @@(disp,PC),Rn
252 ldc Rn,GBR mov.w @@(R0,Rm),Rn
253 ldc Rn,SR mov.w @@Rm+,Rn
254 ldc Rn,VBR mov.w @@Rm,Rn
255 ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm)
256 ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR)
257 ldc.l @@Rn+,VBR mova @@(disp,PC),R0
259 lds Rn,MACL muls Rm,Rn
261 lds.l @@Rn+,MACH neg Rm,Rn
262 lds.l @@Rn+,MACL negc Rm,Rn
265 not Rm,Rn stc.l GBR,@@-Rn
266 or #imm,R0 stc.l SR,@@-Rn
267 or Rm,Rn stc.l VBR,@@-Rn
268 or.b #imm,@@(R0,GBR) sts MACH,Rn
271 rotl Rn sts.l MACH,@@-Rn
272 rotr Rn sts.l MACL,@@-Rn
283 shlr16 Rn tst.b #imm,@@(R0,GBR)
286 sleep xor.b #imm,@@(R0,GBR)
287 stc GBR,Rn xtrct Rm,Rn