1 @c Copyright 1997, 2002, 2003, 2006 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
6 @chapter v850 Dependent Features
10 * V850 Options:: Options
11 * V850 Syntax:: Syntax
12 * V850 Floating Point:: Floating Point
13 * V850 Directives:: V850 Machine Directives
14 * V850 Opcodes:: Opcodes
19 @cindex V850 options (none)
20 @cindex options for V850 (none)
21 @code{@value{AS}} supports the following additional command-line options
22 for the V850 processor family:
24 @cindex command line options, V850
25 @cindex V850 command line options
28 @cindex @code{-wsigned_overflow} command line option, V850
29 @item -wsigned_overflow
30 Causes warnings to be produced when signed immediate values overflow the
31 space available for then within their opcodes. By default this option
32 is disabled as it is possible to receive spurious warnings due to using
33 exact bit patterns as immediate constants.
35 @cindex @code{-wunsigned_overflow} command line option, V850
36 @item -wunsigned_overflow
37 Causes warnings to be produced when unsigned immediate values overflow
38 the space available for then within their opcodes. By default this
39 option is disabled as it is possible to receive spurious warnings due to
40 using exact bit patterns as immediate constants.
42 @cindex @code{-mv850} command line option, V850
44 Specifies that the assembled code should be marked as being targeted at
45 the V850 processor. This allows the linker to detect attempts to link
46 such code with code assembled for other processors.
48 @cindex @code{-mv850e} command line option, V850
50 Specifies that the assembled code should be marked as being targeted at
51 the V850E processor. This allows the linker to detect attempts to link
52 such code with code assembled for other processors.
54 @cindex @code{-mv850e1} command line option, V850
56 Specifies that the assembled code should be marked as being targeted at
57 the V850E1 processor. This allows the linker to detect attempts to link
58 such code with code assembled for other processors.
60 @cindex @code{-mv850any} command line option, V850
62 Specifies that the assembled code should be marked as being targeted at
63 the V850 processor but support instructions that are specific to the
64 extended variants of the process. This allows the production of
65 binaries that contain target specific code, but which are also intended
66 to be used in a generic fashion. For example libgcc.a contains generic
67 routines used by the code produced by GCC for all versions of the v850
68 architecture, together with support routines only used by the V850E
71 @cindex @code{-mv850e2} command line option, V850
73 Specifies that the assembled code should be marked as being targeted at
74 the V850E2 processor. This allows the linker to detect attempts to link
75 such code with code assembled for other processors.
77 @cindex @code{-mv850e2v3} command line option, V850
79 Specifies that the assembled code should be marked as being targeted at
80 the V850E2V3 processor. This allows the linker to detect attempts to link
81 such code with code assembled for other processors.
83 @cindex @code{-mrelax} command line option, V850
85 Enables relaxation. This allows the .longcall and .longjump pseudo
86 ops to be used in the assembler source code. These ops label sections
87 of code which are either a long function call or a long branch. The
88 assembler will then flag these sections of code and the linker will
89 attempt to relax them.
97 * V850-Chars:: Special Characters
98 * V850-Regs:: Register Names
102 @subsection Special Characters
104 @cindex line comment character, V850
105 @cindex V850 line comment character
106 @samp{#} is the line comment character.
108 @subsection Register Names
110 @cindex V850 register names
111 @cindex register names, V850
112 @code{@value{AS}} supports the following names for registers:
114 @cindex @code{zero} register, V850
115 @item general register 0
117 @item general register 1
119 @item general register 2
121 @cindex @code{sp} register, V850
122 @item general register 3
124 @cindex @code{gp} register, V850
125 @item general register 4
127 @cindex @code{tp} register, V850
128 @item general register 5
130 @item general register 6
132 @item general register 7
134 @item general register 8
136 @item general register 9
138 @item general register 10
140 @item general register 11
142 @item general register 12
144 @item general register 13
146 @item general register 14
148 @item general register 15
150 @item general register 16
152 @item general register 17
154 @item general register 18
156 @item general register 19
158 @item general register 20
160 @item general register 21
162 @item general register 22
164 @item general register 23
166 @item general register 24
168 @item general register 25
170 @item general register 26
172 @item general register 27
174 @item general register 28
176 @item general register 29
178 @cindex @code{ep} register, V850
179 @item general register 30
181 @cindex @code{lp} register, V850
182 @item general register 31
184 @cindex @code{eipc} register, V850
185 @item system register 0
187 @cindex @code{eipsw} register, V850
188 @item system register 1
190 @cindex @code{fepc} register, V850
191 @item system register 2
193 @cindex @code{fepsw} register, V850
194 @item system register 3
196 @cindex @code{ecr} register, V850
197 @item system register 4
199 @cindex @code{psw} register, V850
200 @item system register 5
202 @cindex @code{ctpc} register, V850
203 @item system register 16
205 @cindex @code{ctpsw} register, V850
206 @item system register 17
208 @cindex @code{dbpc} register, V850
209 @item system register 18
211 @cindex @code{dbpsw} register, V850
212 @item system register 19
214 @cindex @code{ctbp} register, V850
215 @item system register 20
219 @node V850 Floating Point
220 @section Floating Point
222 @cindex floating point, V850 (@sc{ieee})
223 @cindex V850 floating point (@sc{ieee})
224 The V850 family uses @sc{ieee} floating-point numbers.
226 @node V850 Directives
227 @section V850 Machine Directives
229 @cindex machine directives, V850
230 @cindex V850 machine directives
232 @cindex @code{offset} directive, V850
233 @item .offset @var{<expression>}
234 Moves the offset into the current section to the specified amount.
236 @cindex @code{section} directive, V850
237 @item .section "name", <type>
238 This is an extension to the standard .section directive. It sets the
239 current section to be <type> and creates an alias for this section
242 @cindex @code{.v850} directive, V850
244 Specifies that the assembled code should be marked as being targeted at
245 the V850 processor. This allows the linker to detect attempts to link
246 such code with code assembled for other processors.
248 @cindex @code{.v850e} directive, V850
250 Specifies that the assembled code should be marked as being targeted at
251 the V850E processor. This allows the linker to detect attempts to link
252 such code with code assembled for other processors.
254 @cindex @code{.v850e1} directive, V850
256 Specifies that the assembled code should be marked as being targeted at
257 the V850E1 processor. This allows the linker to detect attempts to link
258 such code with code assembled for other processors.
260 @cindex @code{.v850e2} directive, V850
262 Specifies that the assembled code should be marked as being targeted at
263 the V850E2 processor. This allows the linker to detect attempts to link
264 such code with code assembled for other processors.
266 @cindex @code{.v850e2v3} directive, V850
268 Specifies that the assembled code should be marked as being targeted at
269 the V850E2V3 processor. This allows the linker to detect attempts to link
270 such code with code assembled for other processors.
278 @cindex opcodes for V850
279 @code{@value{AS}} implements all the standard V850 opcodes.
281 @code{@value{AS}} also implements the following pseudo ops:
285 @cindex @code{hi0} pseudo-op, V850
287 Computes the higher 16 bits of the given expression and stores it into
288 the immediate operand field of the given instruction. For example:
290 @samp{mulhi hi0(here - there), r5, r6}
292 computes the difference between the address of labels 'here' and
293 'there', takes the upper 16 bits of this difference, shifts it down 16
294 bits and then multiplies it by the lower 16 bits in register 5, putting
295 the result into register 6.
297 @cindex @code{lo} pseudo-op, V850
299 Computes the lower 16 bits of the given expression and stores it into
300 the immediate operand field of the given instruction. For example:
302 @samp{addi lo(here - there), r5, r6}
304 computes the difference between the address of labels 'here' and
305 'there', takes the lower 16 bits of this difference and adds it to
306 register 5, putting the result into register 6.
308 @cindex @code{hi} pseudo-op, V850
310 Computes the higher 16 bits of the given expression and then adds the
311 value of the most significant bit of the lower 16 bits of the expression
312 and stores the result into the immediate operand field of the given
313 instruction. For example the following code can be used to compute the
314 address of the label 'here' and store it into register 6:
316 @samp{movhi hi(here), r0, r6}
317 @samp{movea lo(here), r6, r6}
319 The reason for this special behaviour is that movea performs a sign
320 extension on its immediate operand. So for example if the address of
321 'here' was 0xFFFFFFFF then without the special behaviour of the hi()
322 pseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the
323 movea instruction would takes its immediate operand, 0xFFFF, sign extend
324 it to 32 bits, 0xFFFFFFFF, and then add it into r6 giving 0xFFFEFFFF
325 which is wrong (the fifth nibble is E). With the hi() pseudo op adding
326 in the top bit of the lo() pseudo op, the movhi instruction actually
327 stores 0 into r6 (0xFFFF + 1 = 0x0000), so that the movea instruction
328 stores 0xFFFFFFFF into r6 - the right value.
330 @cindex @code{hilo} pseudo-op, V850
332 Computes the 32 bit value of the given expression and stores it into
333 the immediate operand field of the given instruction (which must be a
334 mov instruction). For example:
336 @samp{mov hilo(here), r6}
338 computes the absolute address of label 'here' and puts the result into
341 @cindex @code{sdaoff} pseudo-op, V850
343 Computes the offset of the named variable from the start of the Small
344 Data Area (whoes address is held in register 4, the GP register) and
345 stores the result as a 16 bit signed value in the immediate operand
346 field of the given instruction. For example:
348 @samp{ld.w sdaoff(_a_variable)[gp],r6}
350 loads the contents of the location pointed to by the label '_a_variable'
351 into register 6, provided that the label is located somewhere within +/-
352 32K of the address held in the GP register. [Note the linker assumes
353 that the GP register contains a fixed address set to the address of the
354 label called '__gp'. This can either be set up automatically by the
355 linker, or specifically set by using the @samp{--defsym __gp=<value>}
356 command line option].
358 @cindex @code{tdaoff} pseudo-op, V850
360 Computes the offset of the named variable from the start of the Tiny
361 Data Area (whoes address is held in register 30, the EP register) and
362 stores the result as a 4,5, 7 or 8 bit unsigned value in the immediate
363 operand field of the given instruction. For example:
365 @samp{sld.w tdaoff(_a_variable)[ep],r6}
367 loads the contents of the location pointed to by the label '_a_variable'
368 into register 6, provided that the label is located somewhere within +256
369 bytes of the address held in the EP register. [Note the linker assumes
370 that the EP register contains a fixed address set to the address of the
371 label called '__ep'. This can either be set up automatically by the
372 linker, or specifically set by using the @samp{--defsym __ep=<value>}
373 command line option].
375 @cindex @code{zdaoff} pseudo-op, V850
377 Computes the offset of the named variable from address 0 and stores the
378 result as a 16 bit signed value in the immediate operand field of the
379 given instruction. For example:
381 @samp{movea zdaoff(_a_variable),zero,r6}
383 puts the address of the label '_a_variable' into register 6, assuming
384 that the label is somewhere within the first 32K of memory. (Strictly
385 speaking it also possible to access the last 32K of memory as well, as
386 the offsets are signed).
388 @cindex @code{ctoff} pseudo-op, V850
390 Computes the offset of the named variable from the start of the Call
391 Table Area (whoes address is helg in system register 20, the CTBP
392 register) and stores the result a 6 or 16 bit unsigned value in the
393 immediate field of then given instruction or piece of data. For
396 @samp{callt ctoff(table_func1)}
398 will put the call the function whoes address is held in the call table
399 at the location labeled 'table_func1'.
401 @cindex @code{longcall} pseudo-op, V850
402 @item .longcall @code{name}
403 Indicates that the following sequence of instructions is a long call
404 to function @code{name}. The linker will attempt to shorten this call
405 sequence if @code{name} is within a 22bit offset of the call. Only
406 valid if the @code{-mrelax} command line switch has been enabled.
408 @cindex @code{longjump} pseudo-op, V850
409 @item .longjump @code{name}
410 Indicates that the following sequence of instructions is a long jump
411 to label @code{name}. The linker will attempt to shorten this code
412 sequence if @code{name} is within a 22bit offset of the jump. Only
413 valid if the @code{-mrelax} command line switch has been enabled.
418 For information on the V850 instruction set, see @cite{V850
419 Family 32-/16-Bit single-Chip Microcontroller Architecture Manual} from NEC.