gas/doc/c-v850.texi

   1 @c Copyright 1997-2013 Free Software Foundation, Inc.
   2 @c This is part of the GAS manual.
   3 @c For copying conditions, see the file as.texinfo.
   4
   5 @node V850-Dependent
   6 @chapter v850 Dependent Features
   7
   8 @cindex V850 support
   9 @menu
  10 * V850 Options::              Options
  11 * V850 Syntax::               Syntax
  12 * V850 Floating Point::       Floating Point
  13 * V850 Directives::           V850 Machine Directives
  14 * V850 Opcodes::              Opcodes
  15 @end menu
  16
  17 @node V850 Options
  18 @section Options
  19 @cindex V850 options (none)
  20 @cindex options for V850 (none)
  21 @code{@value{AS}} supports the following additional command-line options
  22 for the V850 processor family:
  23
  24 @cindex command line options, V850
  25 @cindex V850 command line options
  26 @table @code
  27
  28 @cindex @code{-wsigned_overflow} command line option, V850
  29 @item -wsigned_overflow
  30 Causes warnings to be produced when signed immediate values overflow the
  31 space available for then within their opcodes.  By default this option
  32 is disabled as it is possible to receive spurious warnings due to using
  33 exact bit patterns as immediate constants.
  34
  35 @cindex @code{-wunsigned_overflow} command line option, V850
  36 @item -wunsigned_overflow
  37 Causes warnings to be produced when unsigned immediate values overflow
  38 the space available for then within their opcodes.  By default this
  39 option is disabled as it is possible to receive spurious warnings due to
  40 using exact bit patterns as immediate constants.
  41
  42 @cindex @code{-mv850} command line option, V850
  43 @item -mv850
  44 Specifies that the assembled code should be marked as being targeted at
  45 the V850 processor.  This allows the linker to detect attempts to link
  46 such code with code assembled for other processors.
  47
  48 @cindex @code{-mv850e} command line option, V850
  49 @item -mv850e
  50 Specifies that the assembled code should be marked as being targeted at
  51 the V850E processor.  This allows the linker to detect attempts to link
  52 such code with code assembled for other processors.
  53
  54 @cindex @code{-mv850e1} command line option, V850
  55 @item -mv850e1
  56 Specifies that the assembled code should be marked as being targeted at
  57 the V850E1 processor.  This allows the linker to detect attempts to link
  58 such code with code assembled for other processors.
  59
  60 @cindex @code{-mv850any} command line option, V850
  61 @item -mv850any
  62 Specifies that the assembled code should be marked as being targeted at
  63 the V850 processor but support instructions that are specific to the
  64 extended variants of the process.  This allows the production of
  65 binaries that contain target specific code, but which are also intended
  66 to be used in a generic fashion.  For example libgcc.a contains generic
  67 routines used by the code produced by GCC for all versions of the v850
  68 architecture, together with support routines only used by the V850E
  69 architecture.
  70
  71 @cindex @code{-mv850e2} command line option, V850
  72 @item -mv850e2
  73 Specifies that the assembled code should be marked as being targeted at
  74 the V850E2 processor.  This allows the linker to detect attempts to link
  75 such code with code assembled for other processors.
  76
  77 @cindex @code{-mv850e2v3} command line option, V850
  78 @item -mv850e2v3
  79 Specifies that the assembled code should be marked as being targeted at
  80 the V850E2V3 processor.  This allows the linker to detect attempts to link
  81 such code with code assembled for other processors.
  82
  83 @cindex @code{-mv850e2v4} command line option, V850
  84 @item -mv850e2v4
  85 This is an alias for @option{-mv850e3v5}.
  86
  87 @cindex @code{-mv850e3v5} command line option, V850
  88 @item -mv850e3v5
  89 Specifies that the assembled code should be marked as being targeted at
  90 the V850E3V5 processor.  This allows the linker to detect attempts to link
  91 such code with code assembled for other processors.
  92
  93 @cindex @code{-mrelax} command line option, V850
  94 @item -mrelax
  95 Enables relaxation.  This allows the .longcall and .longjump pseudo
  96 ops to be used in the assembler source code.  These ops label sections
  97 of code which are either a long function call or a long branch.  The
  98 assembler will then flag these sections of code and the linker will
  99 attempt to relax them.
 100
 101 @cindex @code{-mgcc-abi} command line option, V850
 102 @item -mgcc-abi
 103 Marks the generated objecy file as supporting the old GCC ABI.
 104
 105 @cindex @code{-mrh850-abi} command line option, V850
 106 @item -mrh850-abi
 107 Marks the generated objecy file as supporting the RH850 ABI.  This is
 108 the default.
 109
 110 @cindex @code{-m8byte-align} command line option, V850
 111 @item -m8byte-align
 112 Marks the generated objecy file as supporting a maximum 64-bits of
 113 alignment for variables defined in the source code.
 114
 115 @cindex @code{-m4byte-align} command line option, V850
 116 @item -m4byte-align
 117 Marks the generated objecy file as supporting a maximum 32-bits of
 118 alignment for variables defined in the source code.  This is the
 119 default.
 120
 121 @end table
 122
 123 @node V850 Syntax
 124 @section Syntax
 125 @menu
 126 * V850-Chars::                Special Characters
 127 * V850-Regs::                 Register Names
 128 @end menu
 129
 130 @node V850-Chars
 131 @subsection Special Characters
 132
 133 @cindex line comment character, V850
 134 @cindex V850 line comment character
 135 @samp{#} is the line comment character.  If a @samp{#} appears as the
 136 first character of a line, the whole line is treated as a comment, but
 137 in this case the line can also be a logical line number directive
 138 (@pxref{Comments}) or a preprocessor control command
 139 (@pxref{Preprocessing}).
 140
 141 Two dashes (@samp{--}) can also be used to start a line comment.
 142
 143 @cindex line separator, V850
 144 @cindex statement separator, V850
 145 @cindex V850 line separator
 146
 147 The @samp{;} character can be used to separate statements on the same
 148 line.
 149
 150 @node V850-Regs
 151 @subsection Register Names
 152
 153 @cindex V850 register names
 154 @cindex register names, V850
 155 @code{@value{AS}} supports the following names for registers:
 156 @table @code
 157 @cindex @code{zero} register, V850
 158 @item general register 0
 159 r0, zero
 160 @item general register 1
 161 r1
 162 @item general register 2
 163 r2, hp
 164 @cindex @code{sp} register, V850
 165 @item general register 3
 166 r3, sp
 167 @cindex @code{gp} register, V850
 168 @item general register 4
 169 r4, gp
 170 @cindex @code{tp} register, V850
 171 @item general register 5
 172 r5, tp
 173 @item general register 6
 174 r6
 175 @item general register 7
 176 r7
 177 @item general register 8
 178 r8
 179 @item general register 9
 180 r9
 181 @item general register 10
 182 r10
 183 @item general register 11
 184 r11
 185 @item general register 12
 186 r12
 187 @item general register 13
 188 r13
 189 @item general register 14
 190 r14
 191 @item general register 15
 192 r15
 193 @item general register 16
 194 r16
 195 @item general register 17
 196 r17
 197 @item general register 18
 198 r18
 199 @item general register 19
 200 r19
 201 @item general register 20
 202 r20
 203 @item general register 21
 204 r21
 205 @item general register 22
 206 r22
 207 @item general register 23
 208 r23
 209 @item general register 24
 210 r24
 211 @item general register 25
 212 r25
 213 @item general register 26
 214 r26
 215 @item general register 27
 216 r27
 217 @item general register 28
 218 r28
 219 @item general register 29
 220 r29
 221 @cindex @code{ep} register, V850
 222 @item general register 30
 223 r30, ep
 224 @cindex @code{lp} register, V850
 225 @item general register 31
 226 r31, lp
 227 @cindex @code{eipc} register, V850
 228 @item system register 0
 229 eipc
 230 @cindex @code{eipsw} register, V850
 231 @item system register 1
 232 eipsw
 233 @cindex @code{fepc} register, V850
 234 @item system register 2
 235 fepc
 236 @cindex @code{fepsw} register, V850
 237 @item system register 3
 238 fepsw
 239 @cindex @code{ecr} register, V850
 240 @item system register 4
 241 ecr
 242 @cindex @code{psw} register, V850
 243 @item system register 5
 244 psw
 245 @cindex @code{ctpc} register, V850
 246 @item system register 16
 247 ctpc
 248 @cindex @code{ctpsw} register, V850
 249 @item system register 17
 250 ctpsw
 251 @cindex @code{dbpc} register, V850
 252 @item system register 18
 253 dbpc
 254 @cindex @code{dbpsw} register, V850
 255 @item system register 19
 256 dbpsw
 257 @cindex @code{ctbp} register, V850
 258 @item system register 20
 259 ctbp
 260 @end table
 261
 262 @node V850 Floating Point
 263 @section Floating Point
 264
 265 @cindex floating point, V850 (@sc{ieee})
 266 @cindex V850 floating point (@sc{ieee})
 267 The V850 family uses @sc{ieee} floating-point numbers.
 268
 269 @node V850 Directives
 270 @section V850 Machine Directives
 271
 272 @cindex machine directives, V850
 273 @cindex V850 machine directives
 274 @table @code
 275 @cindex @code{offset} directive, V850
 276 @item .offset @var{<expression>}
 277 Moves the offset into the current section to the specified amount.
 278
 279 @cindex @code{section} directive, V850
 280 @item .section "name", <type>
 281 This is an extension to the standard .section directive.  It sets the
 282 current section to be <type> and creates an alias for this section
 283 called "name".
 284
 285 @cindex @code{.v850} directive, V850
 286 @item .v850
 287 Specifies that the assembled code should be marked as being targeted at
 288 the V850 processor.  This allows the linker to detect attempts to link
 289 such code with code assembled for other processors.
 290
 291 @cindex @code{.v850e} directive, V850
 292 @item .v850e
 293 Specifies that the assembled code should be marked as being targeted at
 294 the V850E processor.  This allows the linker to detect attempts to link
 295 such code with code assembled for other processors.
 296
 297 @cindex @code{.v850e1} directive, V850
 298 @item .v850e1
 299 Specifies that the assembled code should be marked as being targeted at
 300 the V850E1 processor.  This allows the linker to detect attempts to link
 301 such code with code assembled for other processors.
 302
 303 @cindex @code{.v850e2} directive, V850
 304 @item .v850e2
 305 Specifies that the assembled code should be marked as being targeted at
 306 the V850E2 processor.  This allows the linker to detect attempts to link
 307 such code with code assembled for other processors.
 308
 309 @cindex @code{.v850e2v3} directive, V850
 310 @item .v850e2v3
 311 Specifies that the assembled code should be marked as being targeted at
 312 the V850E2V3 processor.  This allows the linker to detect attempts to link
 313 such code with code assembled for other processors.
 314
 315 @cindex @code{.v850e2v4} directive, V850
 316 @item .v850e2v4
 317 Specifies that the assembled code should be marked as being targeted at
 318 the V850E3V5 processor.  This allows the linker to detect attempts to link
 319 such code with code assembled for other processors.
 320
 321 @cindex @code{.v850e3v5} directive, V850
 322 @item .v850e3v5
 323 Specifies that the assembled code should be marked as being targeted at
 324 the V850E3V5 processor.  This allows the linker to detect attempts to link
 325 such code with code assembled for other processors.
 326
 327 @end table
 328
 329 @node V850 Opcodes
 330 @section Opcodes
 331
 332 @cindex V850 opcodes
 333 @cindex opcodes for V850
 334 @code{@value{AS}} implements all the standard V850 opcodes.
 335
 336 @code{@value{AS}} also implements the following pseudo ops:
 337
 338 @table @code
 339
 340 @cindex @code{hi0} pseudo-op, V850
 341 @item hi0()
 342 Computes the higher 16 bits of the given expression and stores it into
 343 the immediate operand field of the given instruction.  For example:
 344
 345     @samp{mulhi hi0(here - there), r5, r6}
 346
 347 computes the difference between the address of labels 'here' and
 348 'there', takes the upper 16 bits of this difference, shifts it down 16
 349 bits and then multiplies it by the lower 16 bits in register 5, putting
 350 the result into register 6.
 351
 352 @cindex @code{lo} pseudo-op, V850
 353 @item lo()
 354 Computes the lower 16 bits of the given expression and stores it into
 355 the immediate operand field of the given instruction.  For example:
 356
 357     @samp{addi lo(here - there), r5, r6}
 358
 359 computes the difference between the address of labels 'here' and
 360 'there', takes the lower 16 bits of this difference and adds it to
 361 register 5, putting the result into register 6.
 362
 363 @cindex @code{hi} pseudo-op, V850
 364 @item hi()
 365 Computes the higher 16 bits of the given expression and then adds the
 366 value of the most significant bit of the lower 16 bits of the expression
 367 and stores the result into the immediate operand field of the given
 368 instruction.  For example the following code can be used to compute the
 369 address of the label 'here' and store it into register 6:
 370
 371     @samp{movhi hi(here), r0, r6}
 372     @samp{movea lo(here), r6, r6}
 373
 374 The reason for this special behaviour is that movea performs a sign
 375 extension on its immediate operand.  So for example if the address of
 376 'here' was 0xFFFFFFFF then without the special behaviour of the hi()
 377 pseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the
 378 movea instruction would takes its immediate operand, 0xFFFF, sign extend
 379 it to 32 bits, 0xFFFFFFFF, and then add it into r6 giving 0xFFFEFFFF
 380 which is wrong (the fifth nibble is E).  With the hi() pseudo op adding
 381 in the top bit of the lo() pseudo op, the movhi instruction actually
 382 stores 0 into r6 (0xFFFF + 1 = 0x0000), so that the movea instruction
 383 stores 0xFFFFFFFF into r6 - the right value.
 384
 385 @cindex @code{hilo} pseudo-op, V850
 386 @item hilo()
 387 Computes the 32 bit value of the given expression and stores it into
 388 the immediate operand field of the given instruction (which must be a
 389 mov instruction).  For example:
 390
 391     @samp{mov hilo(here), r6}
 392
 393 computes the absolute address of label 'here' and puts the result into
 394 register 6.
 395
 396 @cindex @code{sdaoff} pseudo-op, V850
 397 @item sdaoff()
 398 Computes the offset of the named variable from the start of the Small
 399 Data Area (whoes address is held in register 4, the GP register) and
 400 stores the result as a 16 bit signed value in the immediate operand
 401 field of the given instruction.  For example:
 402
 403       @samp{ld.w sdaoff(_a_variable)[gp],r6}
 404
 405 loads the contents of the location pointed to by the label '_a_variable'
 406 into register 6, provided that the label is located somewhere within +/-
 407 32K of the address held in the GP register.  [Note the linker assumes
 408 that the GP register contains a fixed address set to the address of the
 409 label called '__gp'.  This can either be set up automatically by the
 410 linker, or specifically set by using the @samp{--defsym __gp=<value>}
 411 command line option].
 412
 413 @cindex @code{tdaoff} pseudo-op, V850
 414 @item tdaoff()
 415 Computes the offset of the named variable from the start of the Tiny
 416 Data Area (whoes address is held in register 30, the EP register) and
 417 stores the result as a 4,5, 7 or 8 bit unsigned value in the immediate
 418 operand field of the given instruction.  For example:
 419
 420       @samp{sld.w tdaoff(_a_variable)[ep],r6}
 421
 422 loads the contents of the location pointed to by the label '_a_variable'
 423 into register 6, provided that the label is located somewhere within +256
 424 bytes of the address held in the EP register.  [Note the linker assumes
 425 that the EP register contains a fixed address set to the address of the
 426 label called '__ep'.  This can either be set up automatically by the
 427 linker, or specifically set by using the @samp{--defsym __ep=<value>}
 428 command line option].
 429
 430 @cindex @code{zdaoff} pseudo-op, V850
 431 @item zdaoff()
 432 Computes the offset of the named variable from address 0 and stores the
 433 result as a 16 bit signed value in the immediate operand field of the
 434 given instruction.  For example:
 435
 436       @samp{movea zdaoff(_a_variable),zero,r6}
 437
 438 puts the address of the label '_a_variable' into register 6, assuming
 439 that the label is somewhere within the first 32K of memory.  (Strictly
 440 speaking it also possible to access the last 32K of memory as well, as
 441 the offsets are signed).
 442
 443 @cindex @code{ctoff} pseudo-op, V850
 444 @item ctoff()
 445 Computes the offset of the named variable from the start of the Call
 446 Table Area (whoes address is helg in system register 20, the CTBP
 447 register) and stores the result a 6 or 16 bit unsigned value in the
 448 immediate field of then given instruction or piece of data.  For
 449 example:
 450
 451      @samp{callt ctoff(table_func1)}
 452
 453 will put the call the function whoes address is held in the call table
 454 at the location labeled 'table_func1'.
 455
 456 @cindex @code{longcall} pseudo-op, V850
 457 @item .longcall @code{name}
 458 Indicates that the following sequence of instructions is a long call
 459 to function @code{name}.  The linker will attempt to shorten this call
 460 sequence if @code{name} is within a 22bit offset of the call.  Only
 461 valid if the @code{-mrelax} command line switch has been enabled.
 462
 463 @cindex @code{longjump} pseudo-op, V850
 464 @item .longjump @code{name}
 465 Indicates that the following sequence of instructions is a long jump
 466 to label @code{name}.  The linker will attempt to shorten this code
 467 sequence if @code{name} is within a 22bit offset of the jump.  Only
 468 valid if the @code{-mrelax} command line switch has been enabled.
 469
 470 @end table
 471
 472
 473 For information on the V850 instruction set, see @cite{V850
 474 Family 32-/16-Bit single-Chip Microcontroller Architecture Manual} from NEC.
 475 Ltd.