1 /* fp_cvt_ins.s Test file for AArch64 floating-point<->fixed-point
2 conversion and floating-point<->integer conversion instructions.
4 Copyright (C) 2011-2016 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the license, or
12 (at your option) any later version.
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
24 .macro do_cvtf fbits, reg
26 // Floating-point<->integer conversions
32 // Floating-point<->fixed-point conversions
34 SCVTF \reg\()7, W7, #\fbits
36 SCVTF \reg\()7, X7, #\fbits
38 UCVTF \reg\()7, W7, #\fbits
40 UCVTF \reg\()7, X7, #\fbits
55 // 64-bit with V reg element
61 .macro do_fcvt suffix, fbits, reg
63 // Floating-point<->integer conversions
64 FCVT\suffix W7, \reg\()7
65 FCVT\suffix X7, \reg\()7
67 // Floating-point<->fixed-point conversions
69 FCVT\suffix W7, \reg\()7, #\fbits
71 FCVT\suffix X7, \reg\()7, #\fbits
75 .macro fcvts_with_fbits fbits
79 // single-precision and double precision
80 do_fcvt NS, \fbits, \reg
81 do_fcvt NU, \fbits, \reg
82 do_fcvt PS, \fbits, \reg
83 do_fcvt PU, \fbits, \reg
84 do_fcvt MS, \fbits, \reg
85 do_fcvt MU, \fbits, \reg
86 do_fcvt ZS, \fbits, \reg
87 do_fcvt ZU, \fbits, \reg
89 do_fcvt AS, \fbits, \reg
90 do_fcvt AU, \fbits, \reg
95 // After ISA 2.06, only FCVTZ[US] and [US]CVTF are available
97 // single-precision and double precision
98 do_fcvt ZS, \fbits, \reg
99 do_fcvt ZU, \fbits, \reg
105 .macro fcvts_with_fbits_wrapper from=0, to=64
106 fcvts_with_fbits \from
108 fcvts_with_fbits_wrapper "(\from+1)", \to
113 // Generate fcvt instructions without fbits and
114 // with fbits from 1 to 64, also generate [us]cvtf
116 fcvts_with_fbits_wrapper from=0, to=64