aarch64: Fix MOVPRFX markup for bf16 conversions
[deliverable/binutils-gdb.git] / gas / testsuite / gas / aarch64 / sve-movprfx_28.d
1 #source: sve-movprfx_28.s
2 #warning_output: sve-movprfx_28.l
3 #as: -I$srcdir/$subdir --generate-missing-build-notes=no
4 #objdump: -Dr -M notes
5
6 .* file format .*
7
8 Disassembly of section .*:
9
10 0+ <.*>:
11 [^:]+: 04912420 movprfx z0\.s, p1/m, z1\.s
12 [^:]+: 658aa440 bfcvt z0\.h, p1/m, z2\.s
13 [^:]+: 04902420 movprfx z0\.s, p1/z, z1\.s
14 [^:]+: 658aa440 bfcvt z0\.h, p1/m, z2\.s
15 [^:]+: 04512420 movprfx z0\.h, p1/m, z1\.h
16 [^:]+: 658aa440 bfcvt z0\.h, p1/m, z2\.s // note: register size not compatible with previous `movprfx' at operand 1
17 [^:]+: 04502420 movprfx z0\.h, p1/z, z1\.h
18 [^:]+: 658aa440 bfcvt z0\.h, p1/m, z2\.s // note: register size not compatible with previous `movprfx' at operand 1
19 [^:]+: 0420bc20 movprfx z0, z1
20 [^:]+: 658aa440 bfcvt z0\.h, p1/m, z2\.s
21 [^:]+: 0420bc20 movprfx z0, z1
22 [^:]+: 648aa440 bfcvtnt z0\.h, p1/m, z2\.s // note: SVE `movprfx' compatible instruction expected
23 [^:]+: 04912420 movprfx z0\.s, p1/m, z1\.s
24 [^:]+: 648aa440 bfcvtnt z0\.h, p1/m, z2\.s // note: SVE `movprfx' compatible instruction expected
25 [^:]+: 04902420 movprfx z0\.s, p1/z, z1\.s
26 [^:]+: 648aa440 bfcvtnt z0\.h, p1/m, z2\.s // note: SVE `movprfx' compatible instruction expected
27 [^:]+: 04512420 movprfx z0\.h, p1/m, z1\.h
28 [^:]+: 648aa440 bfcvtnt z0\.h, p1/m, z2\.s // note: SVE `movprfx' compatible instruction expected
29 [^:]+: 04502420 movprfx z0\.h, p1/z, z1\.h
30 [^:]+: 648aa440 bfcvtnt z0\.h, p1/m, z2\.s // note: SVE `movprfx' compatible instruction expected
31 [^:]+: d65f03c0 ret
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