Add support to the ARC disassembler for selecting instruction classes.
[deliverable/binutils-gdb.git] / gas / testsuite / gas / arm / armv7e-m+fpv5-d16.s
1 .syntax unified
2 .text
3 .arch armv7e-m
4 .fpu fpv5-d16
5
6 .thumb
7 vseleq.f32 s0, s0, s0
8 vselvs.f32 s1, s1, s1
9 vselge.f32 s30, s30, s30
10 vselgt.f32 s31, s31, s31
11 vseleq.f64 d0, d0, d0
12 vselvs.f64 d8, d8, d8
13 vselge.f64 d15, d15, d15
14 vselgt.f64 d10, d10, d10
15 vmaxnm.f32 s0, s0, s0
16 vmaxnm.f32 s1, s1, s1
17 vmaxnm.f32 s30, s30, s30
18 vmaxnm.f32 s31, s31, s31
19 vmaxnm.f64 d0, d0, d0
20 vmaxnm.f64 d8, d8, d8
21 vmaxnm.f64 d15, d15, d15
22 vmaxnm.f64 d10, d10, d10
23 vminnm.f32 s0, s0, s0
24 vminnm.f32 s1, s1, s1
25 vminnm.f32 s30, s30, s30
26 vminnm.f32 s31, s31, s31
27 vminnm.f64 d0, d0, d0
28 vminnm.f64 d8, d8, d8
29 vminnm.f64 d15, d15, d15
30 vminnm.f64 d10, d10, d10
31 vcvta.s32.f32 s0, s0
32 vcvtn.s32.f32 s1, s1
33 vcvtp.u32.f32 s30, s30
34 vcvtm.u32.f32 s31, s31
35 vcvta.s32.f64 s0, d0
36 vcvtn.s32.f64 s1, d8
37 vcvtp.u32.f64 s30, d15
38 vcvtm.u32.f64 s31, d10
39 vrintz.f32 s0, s0
40 vrintx.f32 s1, s1
41 vrintr.f32 s30, s30
42 vrinta.f32 s0, s0
43 vrintn.f32 s1, s1
44 vrintp.f32 s30, s30
45 vrintm.f32 s31, s31
46 vrintz.f64 d0, d0
47 vrintx.f64 d1, d1
48 vrintr.f64 d10, d10
49 vrinta.f64 d0, d0
50 vrintn.f64 d1, d1
51 vrintp.f64 d10, d10
52 vrintm.f64 d10, d10
53 vcvtt.f16.f64 s0, d0
54 vcvtb.f16.f64 s1, d8
55 vcvtt.f16.f64 s30, d15
56 vcvtb.f16.f64 s31, d10
57 vcvtt.f64.f16 d0, s0
58 vcvtb.f64.f16 d8, s1
59 vcvtt.f64.f16 d15, s30
60 vcvtb.f64.f16 d10, s31
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