3 cdp p1, 4, cr1, cr2, cr3
4 cdpeq 4, 3, c1, c4, cr5, 5
7 ldcl 1, cr14, [r1, #32]
8 ldcmi 0, cr0, [r2, #1020]!
9 ldcpll p7, c1, [r3], #64
14 stcl 3, cr15, [r0, #8]
15 stceq p4, cr12, [r2, #100]!
16 stccc p6, c8, [r4], #48
21 mrcge p4, 5, r15, cr1, cr2, 7
23 mcr p7, 1, r5, cr1, cr1
24 mcrlt 5, 1, r8, cr2, cr9, 0
26 @ The following patterns test Addressing Mode 5 "Unindexed"
29 stc p14, c6, [r1], {1}
31 stc2 p6, c4, [r3], {3}
33 stcl p8, c2, [r5], {5}
34 @ using '9, 10, 11' below results in an invalid ldc2l/stc2l instruction.
35 ldc2l 12, c1, [r6], {6}
36 stc2l p12, c0, [r7], {7}
37 @ using '11' below results in an (invalid) Neon vldmia instruction.
38 ldcl 12, c8, [r8], {255}
39 stcl p12, c9, [r9], {254}
40 mrrc 13, 0, r7, r0, cr4
41 mcrr p14, 0, r7, r0, cr5
42 mrrc 15, 15, r7, r0, cr15
43 mcrr p14, 15, r7, r0, cr14
45 # Extra instructions to allow for code alignment in arm-aout target.
49 # UAL-syntax for MRC with APSR. Pre-UAL was PC
50 mrcge p4, 5, APSR_nzcv, cr1, cr2, 7