gas/testsuite/gas/arm/mve-vldr-bad-1.l

   1 [^:]*: Assembler messages:
   2 [^:]*:10: Error: bad element type for instruction -- `vldrb.16 q0,\[r0,q1\]'
   3 [^:]*:11: Error: bad element type for instruction -- `vldrb.p16 q0,\[r0,q1\]'
   4 [^:]*:12: Error: bad element type for instruction -- `vldrb.f16 q0,\[r0,q1\]'
   5 [^:]*:13: Error: bad element type for instruction -- `vldrb.32 q0,\[r0,q1\]'
   6 [^:]*:14: Error: bad element type for instruction -- `vldrb.f32 q0,\[r0,q1\]'
   7 [^:]*:15: Error: bad element type for instruction -- `vldrb.64 q0,\[r0,q1\]'
   8 [^:]*:16: Error: bad element type for instruction -- `vldrb.u64 q0,\[r0,q1\]'
   9 [^:]*:17: Error: bad element type for instruction -- `vldrb.s64 q0,\[r0,q1\]'
  10 [^:]*:18: Warning: instruction is UNPREDICTABLE with PC operand
  11 [^:]*:19: Error: destination register and offset register may not be the same -- `vldrb.u32 q0,\[r0,q0\]'
  12 [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
  13 [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
  14 [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
  15 [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
  16 [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
  17 [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
  18 [^:]*:22: Error: syntax error -- `vldrbeq.u32 q0,\[r0,q1\]'
  19 [^:]*:23: Error: syntax error -- `vldrbeq.u32 q0,\[r0,q1\]'
  20 [^:]*:25: Error: syntax error -- `vldrbeq.u32 q0,\[r0,q1\]'
  21 [^:]*:26: Error: vector predicated instruction should be in VPT/VPST block -- `vldrbt.u32 q0,\[r0,q1\]'
  22 [^:]*:28: Error: instruction missing MVE vector predication code -- `vldrb.u32 q0,\[r0,q1\]'
  23 [^:]*:30: Error: bad element type for instruction -- `vldrh.32 q0,\[r0,q1\]'
  24 [^:]*:31: Error: bad element type for instruction -- `vldrh.f32 q0,\[r0,q1\]'
  25 [^:]*:32: Error: bad element type for instruction -- `vldrh.64 q0,\[r0,q1\]'
  26 [^:]*:33: Error: bad element type for instruction -- `vldrh.u64 q0,\[r0,q1\]'
  27 [^:]*:34: Error: bad element type for instruction -- `vldrh.s64 q0,\[r0,q1\]'
  28 [^:]*:35: Warning: instruction is UNPREDICTABLE with PC operand
  29 [^:]*:36: Error: destination register and offset register may not be the same -- `vldrh.u32 q0,\[r0,q0\]'
  30 [^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
  31 [^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
  32 [^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
  33 [^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
  34 [^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
  35 [^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
  36 [^:]*:39: Error: syntax error -- `vldrheq.u32 q0,\[r0,q1\]'
  37 [^:]*:40: Error: syntax error -- `vldrheq.u32 q0,\[r0,q1\]'
  38 [^:]*:42: Error: syntax error -- `vldrheq.u32 q0,\[r0,q1\]'
  39 [^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vldrht.u32 q0,\[r0,q1\]'
  40 [^:]*:45: Error: instruction missing MVE vector predication code -- `vldrh.u32 q0,\[r0,q1\]'
  41 [^:]*:47: Error: bad element type for instruction -- `vldrw.64 q0,\[r0,q1\]'
  42 [^:]*:48: Error: bad element type for instruction -- `vldrw.u64 q0,\[r0,q1\]'
  43 [^:]*:49: Error: bad element type for instruction -- `vldrw.s64 q0,\[r0,q1\]'
  44 [^:]*:50: Warning: instruction is UNPREDICTABLE with PC operand
  45 [^:]*:51: Error: destination register and offset register may not be the same -- `vldrw.u32 q0,\[r0,q0\]'
  46 [^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block
  47 [^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block
  48 [^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block
  49 [^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block
  50 [^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block
  51 [^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block
  52 [^:]*:54: Error: syntax error -- `vldrweq.u32 q0,\[r0,q1\]'
  53 [^:]*:55: Error: syntax error -- `vldrweq.u32 q0,\[r0,q1\]'
  54 [^:]*:57: Error: syntax error -- `vldrweq.u32 q0,\[r0,q1\]'
  55 [^:]*:58: Error: vector predicated instruction should be in VPT/VPST block -- `vldrwt.u32 q0,\[r0,q1\]'
  56 [^:]*:60: Error: instruction missing MVE vector predication code -- `vldrw.u32 q0,\[r0,q1\]'
  57 [^:]*:69: Error: bad element type for instruction -- `vldrd.8 q0,\[r0,q1\]'
  58 [^:]*:70: Error: bad element type for instruction -- `vldrd.u8 q0,\[r0,q1\]'
  59 [^:]*:71: Error: bad element type for instruction -- `vldrd.s8 q0,\[r0,q1\]'
  60 [^:]*:72: Error: bad element type for instruction -- `vldrd.p8 q0,\[r0,q1\]'
  61 [^:]*:73: Error: bad element type for instruction -- `vldrd.16 q0,\[r0,q1\]'
  62 [^:]*:74: Error: bad element type for instruction -- `vldrd.u16 q0,\[r0,q1\]'
  63 [^:]*:75: Error: bad element type for instruction -- `vldrd.s16 q0,\[r0,q1\]'
  64 [^:]*:76: Error: bad element type for instruction -- `vldrd.p16 q0,\[r0,q1\]'
  65 [^:]*:77: Error: bad element type for instruction -- `vldrd.f16 q0,\[r0,q1\]'
  66 [^:]*:78: Error: bad element type for instruction -- `vldrd.32 q0,\[r0,q1\]'
  67 [^:]*:79: Error: bad element type for instruction -- `vldrd.u32 q0,\[r0,q1\]'
  68 [^:]*:80: Error: bad element type for instruction -- `vldrd.s32 q0,\[r0,q1\]'
  69 [^:]*:81: Error: bad element type for instruction -- `vldrd.f32 q0,\[r0,q1\]'
  70 [^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
  71 [^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
  72 [^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
  73 [^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
  74 [^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
  75 [^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
  76 [^:]*:84: Error: syntax error -- `vldrdeq.u64 q0,\[r0,q1\]'
  77 [^:]*:85: Error: syntax error -- `vldrdeq.u64 q0,\[r0,q1\]'
  78 [^:]*:87: Error: syntax error -- `vldrdeq.u64 q0,\[r0,q1\]'
  79 [^:]*:88: Error: vector predicated instruction should be in VPT/VPST block -- `vldrdt.u64 q0,\[r0,q1\]'
  80 [^:]*:90: Error: instruction missing MVE vector predication code -- `vldrd.u64 q0,\[r0,q1\]'
  81 [^:]*:92: Error: shift expression expected -- `vldrb.u8 q0,\[r0,q1,#0\]'
  82 [^:]*:93: Error: can not shift offsets when accessing less than half-word -- `vldrb.u8 q0,\[r0,q1,UXTW#1\]'
  83 [^:]*:94: Error: can not shift offsets when accessing less than half-word -- `vldrb.u16 q0,\[r0,q1,UXTW#1\]'
  84 [^:]*:95: Error: can not shift offsets when accessing less than half-word -- `vldrb.u32 q0,\[r0,q1,UXTW#1\]'
  85 [^:]*:96: Error: shift expression expected -- `vldrh.u16 q0,\[r0,q1,#1\]'
  86 [^:]*:97: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u16 q0,\[r0,q1,UXTW#2\]'
  87 [^:]*:98: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u32 q0,\[r0,q1,UXTW#2\]'
  88 [^:]*:99: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u16 q0,\[r0,q1,UXTW#3\]'
  89 [^:]*:100: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u32 q0,\[r0,q1,UXTW#3\]'
  90 [^:]*:101: Error: shift expression expected -- `vldrw.u32 q0,\[r0,q1,#2\]'
  91 [^:]*:102: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrw.u32 q0,\[r0,q1,UXTW#1\]'
  92 [^:]*:103: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrw.u32 q0,\[r0,q1,UXTW#3\]'
  93 [^:]*:104: Error: shift expression expected -- `vldrd.u64 q0,\[r0,q1,#3\]'
  94 [^:]*:105: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrd.u64 q0,\[r0,q1,UXTW#1\]'
  95 [^:]*:106: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrd.u64 q0,\[r0,q1,UXTW#2\]'
  96 [^:]*:107: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrd.u64 q0,\[r0,q1,UXTW#4\]'
  97
  98