gas/testsuite/gas/arm/mve-vldr-bad-2.l

   1 [^:]*: Assembler messages:
   2 [^:]*:10: Error: bad element type for instruction -- `vldrw.u16 q0,\[q1,#4\]'
   3 [^:]*:11: Error: bad element type for instruction -- `vldrw.u64 q0,\[q1,#-4\]'
   4 [^:]*:12: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#1\]'
   5 [^:]*:13: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#2\]'
   6 [^:]*:14: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#231\]'
   7 [^:]*:15: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#516\]'
   8 [^:]*:16: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#-516\]'
   9 [^:]*:17: Error: destination register and offset register may not be the same -- `vldrw.u32 q0,\[q0,#4\]'
  10 [^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
  11 [^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
  12 [^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
  13 [^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
  14 [^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
  15 [^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
  16 [^:]*:20: Error: syntax error -- `vldrweq.u32 q0,\[q1\]'
  17 [^:]*:21: Error: syntax error -- `vldrweq.u32 q0,\[q1\]'
  18 [^:]*:23: Error: syntax error -- `vldrweq.u32 q0,\[q1\]'
  19 [^:]*:24: Error: vector predicated instruction should be in VPT/VPST block -- `vldrwt.u32 q0,\[q1\]'
  20 [^:]*:26: Error: instruction missing MVE vector predication code -- `vldrw.u32 q0,\[q1\]'
  21 [^:]*:27: Error: bad element type for instruction -- `vldrd.u16 q0,\[q1,#8\]'
  22 [^:]*:28: Error: bad element type for instruction -- `vldrd.u32 q0,\[q1,#-8\]'
  23 [^:]*:29: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#1\]'
  24 [^:]*:30: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#4\]'
  25 [^:]*:31: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#7\]'
  26 [^:]*:32: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#228\]'
  27 [^:]*:33: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#1024\]'
  28 [^:]*:34: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#-1024\]'
  29 [^:]*:35: Error: destination register and offset register may not be the same -- `vldrd.u64 q0,\[q0,#8\]'
  30 [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
  31 [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
  32 [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
  33 [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
  34 [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
  35 [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
  36 [^:]*:38: Error: syntax error -- `vldrdeq.u64 q0,\[q1\]'
  37 [^:]*:39: Error: syntax error -- `vldrdeq.u64 q0,\[q1\]'
  38 [^:]*:41: Error: syntax error -- `vldrdeq.u64 q0,\[q1\]'
  39 [^:]*:42: Error: vector predicated instruction should be in VPT/VPST block -- `vldrdt.u64 q0,\[q1\]'
  40 [^:]*:44: Error: instruction missing MVE vector predication code -- `vldrd.u64 q0,\[q1\]'
  41