gas/testsuite/gas/arm/mve-vrmlaldavh-bad.l

   1 [^:]*: Assembler messages:
   2 [^:]*:10: Error: bad type in SIMD instruction -- `vrmlaldavh.s16 r0,r1,q2,q3'
   3 [^:]*:11: Error: bad type in SIMD instruction -- `vrmlaldavh.i32 r0,r1,q2,q3'
   4 [^:]*:12: Error: bad type in SIMD instruction -- `vrmlaldavha.s16 r0,r1,q2,q3'
   5 [^:]*:13: Error: bad type in SIMD instruction -- `vrmlaldavha.i32 r0,r1,q2,q3'
   6 [^:]*:14: Error: bad type in SIMD instruction -- `vrmlalvh.s16 r0,r1,q2,q3'
   7 [^:]*:15: Error: bad type in SIMD instruction -- `vrmlalvh.i32 r0,r1,q2,q3'
   8 [^:]*:16: Error: bad type in SIMD instruction -- `vrmlalvha.s16 r0,r1,q2,q3'
   9 [^:]*:17: Error: bad type in SIMD instruction -- `vrmlalvha.i32 r0,r1,q2,q3'
  10 [^:]*:18: Error: bad type in SIMD instruction -- `vrmlaldavhx.u32 r0,r1,q2,q3'
  11 [^:]*:19: Error: bad type in SIMD instruction -- `vrmlaldavhax.u32 r0,r1,q2,q3'
  12 [^:]*:20: Error: bad type in SIMD instruction -- `vrmlaldavhx.i32 r0,r1,q2,q3'
  13 [^:]*:21: Error: bad type in SIMD instruction -- `vrmlaldavhax.i32 r0,r1,q2,q3'
  14 [^:]*:22: Error: bad type in SIMD instruction -- `vrmlsldavh.s16 r0,r1,q2,q3'
  15 [^:]*:23: Error: bad type in SIMD instruction -- `vrmlsldavh.u32 r0,r1,q2,q3'
  16 [^:]*:24: Error: bad type in SIMD instruction -- `vrmlsldavha.s16 r0,r1,q2,q3'
  17 [^:]*:25: Error: bad type in SIMD instruction -- `vrmlsldavha.u32 r0,r1,q2,q3'
  18 [^:]*:26: Error: bad type in SIMD instruction -- `vrmlsldavhx.s16 r0,r1,q2,q3'
  19 [^:]*:27: Error: bad type in SIMD instruction -- `vrmlsldavhx.u32 r0,r1,q2,q3'
  20 [^:]*:28: Error: bad type in SIMD instruction -- `vrmlsldavhax.s16 r0,r1,q2,q3'
  21 [^:]*:29: Error: bad type in SIMD instruction -- `vrmlsldavhax.u32 r0,r1,q2,q3'
  22 [^:]*:30: Error: Odd register not allowed here -- `vrmlaldavh.s32 r1,r1,q2,q3'
  23 [^:]*:31: Error: Even register not allowed here -- `vrmlaldavh.s32 r0,r0,q2,q3'
  24 [^:]*:32: Error: r13 not allowed here -- `vrmlaldavh.s32 r0,sp,q2,q3'
  25 [^:]*:33: Error: r15 not allowed here -- `vrmlaldavh.s32 r0,pc,q2,q3'
  26 [^:]*:34: Error: Odd register not allowed here -- `vrmlaldavha.s32 r1,r1,q2,q3'
  27 [^:]*:35: Error: Even register not allowed here -- `vrmlaldavha.s32 r0,r0,q2,q3'
  28 [^:]*:36: Error: r13 not allowed here -- `vrmlaldavha.s32 r0,sp,q2,q3'
  29 [^:]*:37: Error: r15 not allowed here -- `vrmlaldavha.s32 r0,pc,q2,q3'
  30 [^:]*:38: Error: Odd register not allowed here -- `vrmlaldavhx.s32 r1,r1,q2,q3'
  31 [^:]*:39: Error: Even register not allowed here -- `vrmlaldavhx.s32 r0,r0,q2,q3'
  32 [^:]*:40: Error: r13 not allowed here -- `vrmlaldavhx.s32 r0,sp,q2,q3'
  33 [^:]*:41: Error: r15 not allowed here -- `vrmlaldavhx.s32 r0,pc,q2,q3'
  34 [^:]*:42: Error: Odd register not allowed here -- `vrmlaldavhax.s32 r1,r1,q2,q3'
  35 [^:]*:43: Error: Even register not allowed here -- `vrmlaldavhax.s32 r0,r0,q2,q3'
  36 [^:]*:44: Error: r13 not allowed here -- `vrmlaldavhax.s32 r0,sp,q2,q3'
  37 [^:]*:45: Error: r15 not allowed here -- `vrmlaldavhax.s32 r0,pc,q2,q3'
  38 [^:]*:46: Error: Odd register not allowed here -- `vrmlalvh.s32 r1,r1,q2,q3'
  39 [^:]*:47: Error: Even register not allowed here -- `vrmlalvh.s32 r0,r0,q2,q3'
  40 [^:]*:48: Error: r13 not allowed here -- `vrmlalvh.s32 r0,sp,q2,q3'
  41 [^:]*:49: Error: r15 not allowed here -- `vrmlalvh.s32 r0,pc,q2,q3'
  42 [^:]*:50: Error: Odd register not allowed here -- `vrmlalvha.s32 r1,r1,q2,q3'
  43 [^:]*:51: Error: Even register not allowed here -- `vrmlalvha.s32 r0,r0,q2,q3'
  44 [^:]*:52: Error: r13 not allowed here -- `vrmlalvha.s32 r0,sp,q2,q3'
  45 [^:]*:53: Error: r15 not allowed here -- `vrmlalvha.s32 r0,pc,q2,q3'
  46 [^:]*:54: Error: Odd register not allowed here -- `vrmlsldavh.s32 r1,r1,q2,q3'
  47 [^:]*:55: Error: Even register not allowed here -- `vrmlsldavh.s32 r0,r0,q2,q3'
  48 [^:]*:56: Warning: instruction is UNPREDICTABLE with SP operand
  49 [^:]*:57: Error: r15 not allowed here -- `vrmlsldavh.s32 r0,pc,q2,q3'
  50 [^:]*:58: Error: Odd register not allowed here -- `vrmlsldavha.s32 r1,r1,q2,q3'
  51 [^:]*:59: Error: Even register not allowed here -- `vrmlsldavha.s32 r0,r0,q2,q3'
  52 [^:]*:60: Warning: instruction is UNPREDICTABLE with SP operand
  53 [^:]*:61: Error: r15 not allowed here -- `vrmlsldavha.s32 r0,pc,q2,q3'
  54 [^:]*:62: Error: Odd register not allowed here -- `vrmlsldavhx.s32 r1,r1,q2,q3'
  55 [^:]*:63: Error: Even register not allowed here -- `vrmlsldavhx.s32 r0,r0,q2,q3'
  56 [^:]*:64: Warning: instruction is UNPREDICTABLE with SP operand
  57 [^:]*:65: Error: r15 not allowed here -- `vrmlsldavhx.s32 r0,pc,q2,q3'
  58 [^:]*:66: Error: Odd register not allowed here -- `vrmlsldavhax.s32 r1,r1,q2,q3'
  59 [^:]*:67: Error: Even register not allowed here -- `vrmlsldavhax.s32 r0,r0,q2,q3'
  60 [^:]*:68: Warning: instruction is UNPREDICTABLE with SP operand
  61 [^:]*:69: Error: r15 not allowed here -- `vrmlsldavhax.s32 r0,pc,q2,q3'
  62 [^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block
  63 [^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block
  64 [^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block
  65 [^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block
  66 [^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block
  67 [^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block
  68 [^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block
  69 [^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block
  70 [^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block
  71 [^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block
  72 [^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block
  73 [^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block
  74 [^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block
  75 [^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block
  76 [^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block
  77 [^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block
  78 [^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block
  79 [^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block
  80 [^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block
  81 [^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block
  82 [^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block
  83 [^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block
  84 [^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block
  85 [^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block
  86 [^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
  87 [^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
  88 [^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
  89 [^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
  90 [^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
  91 [^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
  92 [^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block
  93 [^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block
  94 [^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block
  95 [^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block
  96 [^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block
  97 [^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block
  98 [^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
  99 [^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
 100 [^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
 101 [^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
 102 [^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
 103 [^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
 104 [^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
 105 [^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
 106 [^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
 107 [^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
 108 [^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
 109 [^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
 110 [^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block
 111 [^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block
 112 [^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block
 113 [^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block
 114 [^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block
 115 [^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block
 116 [^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block
 117 [^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block
 118 [^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block
 119 [^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block
 120 [^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block
 121 [^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block
 122 [^:]*:81: Error: syntax error -- `vrmlaldavheq.s32 r0,r1,q2,q3'
 123 [^:]*:82: Error: syntax error -- `vrmlaldavheq.s32 r0,r1,q2,q3'
 124 [^:]*:84: Error: syntax error -- `vrmlaldavheq.s32 r0,r1,q2,q3'
 125 [^:]*:85: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlaldavht.s32 r0,r1,q2,q3'
 126 [^:]*:87: Error: instruction missing MVE vector predication code -- `vrmlaldavh.s32 r0,r1,q2,q3'
 127 [^:]*:89: Error: syntax error -- `vrmlaldavhaeq.s32 r0,r1,q2,q3'
 128 [^:]*:90: Error: syntax error -- `vrmlaldavhaeq.s32 r0,r1,q2,q3'
 129 [^:]*:92: Error: syntax error -- `vrmlaldavhaeq.s32 r0,r1,q2,q3'
 130 [^:]*:93: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlaldavhat.s32 r0,r1,q2,q3'
 131 [^:]*:95: Error: instruction missing MVE vector predication code -- `vrmlaldavha.s32 r0,r1,q2,q3'
 132 [^:]*:97: Error: syntax error -- `vrmlaldavhxeq.s32 r0,r1,q2,q3'
 133 [^:]*:98: Error: syntax error -- `vrmlaldavhxeq.s32 r0,r1,q2,q3'
 134 [^:]*:100: Error: syntax error -- `vrmlaldavhxeq.s32 r0,r1,q2,q3'
 135 [^:]*:101: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlaldavhxt.s32 r0,r1,q2,q3'
 136 [^:]*:103: Error: instruction missing MVE vector predication code -- `vrmlaldavhx.s32 r0,r1,q2,q3'
 137 [^:]*:105: Error: syntax error -- `vrmlaldavhaxeq.s32 r0,r1,q2,q3'
 138 [^:]*:106: Error: syntax error -- `vrmlaldavhaxeq.s32 r0,r1,q2,q3'
 139 [^:]*:108: Error: syntax error -- `vrmlaldavhaxeq.s32 r0,r1,q2,q3'
 140 [^:]*:109: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlaldavhaxt.s32 r0,r1,q2,q3'
 141 [^:]*:111: Error: instruction missing MVE vector predication code -- `vrmlaldavhax.s32 r0,r1,q2,q3'
 142 [^:]*:113: Error: syntax error -- `vrmlalvheq.s32 r0,r1,q2,q3'
 143 [^:]*:114: Error: syntax error -- `vrmlalvheq.s32 r0,r1,q2,q3'
 144 [^:]*:116: Error: syntax error -- `vrmlalvheq.s32 r0,r1,q2,q3'
 145 [^:]*:117: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlalvht.s32 r0,r1,q2,q3'
 146 [^:]*:119: Error: instruction missing MVE vector predication code -- `vrmlalvh.s32 r0,r1,q2,q3'
 147 [^:]*:121: Error: syntax error -- `vrmlalvhaeq.s32 r0,r1,q2,q3'
 148 [^:]*:122: Error: syntax error -- `vrmlalvhaeq.s32 r0,r1,q2,q3'
 149 [^:]*:124: Error: syntax error -- `vrmlalvhaeq.s32 r0,r1,q2,q3'
 150 [^:]*:125: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlalvhat.s32 r0,r1,q2,q3'
 151 [^:]*:127: Error: instruction missing MVE vector predication code -- `vrmlalvha.s32 r0,r1,q2,q3'
 152 [^:]*:129: Error: syntax error -- `vrmlsldavheq.s32 r0,r1,q2,q3'
 153 [^:]*:130: Error: syntax error -- `vrmlsldavheq.s32 r0,r1,q2,q3'
 154 [^:]*:132: Error: syntax error -- `vrmlsldavheq.s32 r0,r1,q2,q3'
 155 [^:]*:133: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlsldavht.s32 r0,r1,q2,q3'
 156 [^:]*:135: Error: instruction missing MVE vector predication code -- `vrmlsldavh.s32 r0,r1,q2,q3'
 157 [^:]*:137: Error: syntax error -- `vrmlsldavhaeq.s32 r0,r1,q2,q3'
 158 [^:]*:138: Error: syntax error -- `vrmlsldavhaeq.s32 r0,r1,q2,q3'
 159 [^:]*:140: Error: syntax error -- `vrmlsldavhaeq.s32 r0,r1,q2,q3'
 160 [^:]*:141: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlsldavhat.s32 r0,r1,q2,q3'
 161 [^:]*:143: Error: instruction missing MVE vector predication code -- `vrmlsldavha.s32 r0,r1,q2,q3'
 162 [^:]*:145: Error: syntax error -- `vrmlsldavhxeq.s32 r0,r1,q2,q3'
 163 [^:]*:146: Error: syntax error -- `vrmlsldavhxeq.s32 r0,r1,q2,q3'
 164 [^:]*:148: Error: syntax error -- `vrmlsldavhxeq.s32 r0,r1,q2,q3'
 165 [^:]*:149: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlsldavhxt.s32 r0,r1,q2,q3'
 166 [^:]*:151: Error: instruction missing MVE vector predication code -- `vrmlsldavhx.s32 r0,r1,q2,q3'
 167 [^:]*:153: Error: syntax error -- `vrmlsldavhaxeq.s32 r0,r1,q2,q3'
 168 [^:]*:154: Error: syntax error -- `vrmlsldavhaxeq.s32 r0,r1,q2,q3'
 169 [^:]*:156: Error: syntax error -- `vrmlsldavhaxeq.s32 r0,r1,q2,q3'
 170 [^:]*:157: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlsldavhaxt.s32 r0,r1,q2,q3'
 171 [^:]*:159: Error: instruction missing MVE vector predication code -- `vrmlsldavhax.s32 r0,r1,q2,q3'