[PATCH 27/57][Arm][GAS] Add support for MVE instructions: vqdmladh, vqrdmladh, vqdmls...
[deliverable/binutils-gdb.git] / gas / testsuite / gas / arm / mve-vsbc-bad.l
1 [^:]*: Assembler messages:
2 [^:]*:10: Error: bad type in SIMD instruction -- `vsbc.i16 q0,q1,q2'
3 [^:]*:11: Error: bad type in SIMD instruction -- `vsbci.i16 q0,q1,q2'
4 [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
5 [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
6 [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
7 [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
8 [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
9 [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
10 [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
11 [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
12 [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
13 [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
14 [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
15 [^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
16 [^:]*:15: Error: syntax error -- `vsbceq.i32 q0,q1,q2'
17 [^:]*:16: Error: syntax error -- `vsbceq.i32 q0,q1,q2'
18 [^:]*:18: Error: syntax error -- `vsbceq.i32 q0,q1,q2'
19 [^:]*:20: Error: instruction missing MVE vector predication code -- `vsbc.i32 q0,q1,q2'
20 [^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vsbct.i32 q0,q1,q2'
21 [^:]*:23: Error: syntax error -- `vsbcieq.i32 q0,q1,q2'
22 [^:]*:24: Error: syntax error -- `vsbcieq.i32 q0,q1,q2'
23 [^:]*:26: Error: syntax error -- `vsbcieq.i32 q0,q1,q2'
24 [^:]*:28: Error: instruction missing MVE vector predication code -- `vsbci.i32 q0,q1,q2'
25 [^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vsbcit.i32 q0,q1,q2'
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