gas/testsuite/gas/arm/mve-vshr-bad.l

   1 [^:]*: Assembler messages:
   2 [^:]*:10: Error: bad type in SIMD instruction -- `vshr.s64 q0,q1,#1'
   3 [^:]*:11: Error: bad type in SIMD instruction -- `vshr.i32 q0,q1,#1'
   4 [^:]*:12: Error: bad type in SIMD instruction -- `vrshr.u64 q0,q1,#1'
   5 [^:]*:13: Error: bad type in SIMD instruction -- `vrshr.i32 q0,q1,#1'
   6 [^:]*:14: Error: immediate out of range for shift -- `vshr.s8 q0,q1,#9'
   7 [^:]*:15: Error: immediate out of range for shift -- `vshr.u8 q0,q1,#9'
   8 [^:]*:16: Error: immediate out of range for shift -- `vshr.s16 q0,q1,#17'
   9 [^:]*:17: Error: immediate out of range for shift -- `vshr.u16 q0,q1,#17'
  10 [^:]*:18: Error: immediate out of range for shift -- `vshr.s32 q0,q1,#33'
  11 [^:]*:19: Error: immediate out of range for shift -- `vshr.u32 q0,q1,#33'
  12 [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
  13 [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
  14 [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
  15 [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
  16 [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
  17 [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
  18 [^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
  19 [^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
  20 [^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
  21 [^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
  22 [^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
  23 [^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
  24 [^:]*:23: Error: syntax error -- `vshreq.s32 q0,q1,#1'
  25 [^:]*:24: Error: syntax error -- `vshreq.s32 q0,q1,#1'
  26 [^:]*:26: Error: syntax error -- `vshreq.s32 q0,q1,#1'
  27 [^:]*:27: Error: vector predicated instruction should be in VPT/VPST block -- `vshrt.s32 q0,q1,#1'
  28 [^:]*:29: Error: instruction missing MVE vector predication code -- `vshr.s32 q0,q1,#1'
  29 [^:]*:31: Error: syntax error -- `vrshreq.s32 q0,q1,#1'
  30 [^:]*:32: Error: syntax error -- `vrshreq.s32 q0,q1,#1'
  31 [^:]*:34: Error: syntax error -- `vrshreq.s32 q0,q1,#1'
  32 [^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vrshrt.s32 q0,q1,#1'
  33 [^:]*:37: Error: instruction missing MVE vector predication code -- `vrshr.s32 q0,q1,#1'