1 @ Neon tests. Basic bitfield tests, using zero for as many registers/fields as
2 @ possible, but without causing instructions to be badly-formed.
8 .macro regs3_1 op opq vtype
14 .macro dregs3_1 op vtype
18 .macro regn3_1 op operand2 vtype
19 \op\vtype d0,q0,\operand2
22 .macro regl3_1 op operand2 vtype
23 \op\vtype q0,d0,\operand2
26 .macro regw3_1 op operand2 vtype
27 \op\vtype q0,q0,\operand2
30 .macro regs2_1 op opq vtype
36 .macro regs3_su_32 op opq
45 regs3_su_32 vaba vabaq
46 regs3_su_32 vhadd vhaddq
47 regs3_su_32 vrhadd vrhaddq
48 regs3_su_32 vhsub vhsubq
50 .macro regs3_su_64 op opq
61 regs3_su_64 vqadd vqaddq
62 regs3_su_64 vqsub vqsubq
63 regs3_su_64 vrshl vrshlq
64 regs3_su_64 vqrshl vqrshlq
66 regs3_su_64 vshl vshlq
67 regs3_su_64 vqshl vqshlq
69 .macro regs2i_1 op opq imm vtype
75 .macro regs2i_su_64 op opq imm
76 regs2i_1 \op \opq \imm .s8
77 regs2i_1 \op \opq \imm .s16
78 regs2i_1 \op \opq \imm .s32
79 regs2i_1 \op \opq \imm .s64
80 regs2i_1 \op \opq \imm .u8
81 regs2i_1 \op \opq \imm .u16
82 regs2i_1 \op \opq \imm .u32
83 regs2i_1 \op \opq \imm .u64
86 .macro regs2i_i_64 op opq imm
87 regs2i_1 \op \opq \imm .i8
88 regs2i_1 \op \opq \imm .i16
89 regs2i_1 \op \opq \imm .i32
90 regs2i_1 \op \opq \imm .s32
91 regs2i_1 \op \opq \imm .u32
92 regs2i_1 \op \opq \imm .i64
95 regs2i_i_64 vshl vshlq 0
96 regs2i_su_64 vqshl vqshlq 0
98 .macro regs3_ntyp op opq
102 regs3_ntyp vand vandq
103 regs3_ntyp vbic vbicq
104 regs3_ntyp vorr vorrq
105 regs3_ntyp vorn vornq
106 regs3_ntyp veor veorq
108 .macro logic_imm_1 op opq imm vtype
114 .macro logic_imm op opq
115 logic_imm_1 \op \opq 0x000000a5000000a5 .i64
116 logic_imm_1 \op \opq 0x0000a5000000a500 .i64
117 logic_imm_1 \op \opq 0x00a5000000a50000 .i64
118 logic_imm_1 \op \opq 0xa5000000a5000000 .i64
119 logic_imm_1 \op \opq 0x00a500a500a500a5 .i64
120 logic_imm_1 \op \opq 0xa500a500a500a500 .i64
121 logic_imm_1 \op \opq 0x000000ff .i32
122 logic_imm_1 \op \opq 0x000000ff .s32
123 logic_imm_1 \op \opq 0x000000ff .u32
124 logic_imm_1 \op \opq 0x0000ff00 .i32
125 logic_imm_1 \op \opq 0x00ff0000 .i32
126 logic_imm_1 \op \opq 0xff000000 .i32
127 logic_imm_1 \op \opq 0x00a500a5 .i32
128 logic_imm_1 \op \opq 0xa500a500 .i32
129 logic_imm_1 \op \opq 0x00ff .i16
130 logic_imm_1 \op \opq 0xff00 .i16
131 logic_imm_1 \op \opq 0x00 .i8
137 .macro logic_inv_imm op opq
138 logic_imm_1 \op \opq 0xffffff5affffff5a .i64
139 logic_imm_1 \op \opq 0xffff5affffff5aff .i64
140 logic_imm_1 \op \opq 0xff5affffff5affff .i64
141 logic_imm_1 \op \opq 0x5affffff5affffff .i64
142 logic_imm_1 \op \opq 0xff5aff5aff5aff5a .i64
143 logic_imm_1 \op \opq 0x5aff5aff5aff5aff .i64
144 logic_imm_1 \op \opq 0xffffff00 .i32
145 logic_imm_1 \op \opq 0xffffff00 .s32
146 logic_imm_1 \op \opq 0xffffff00 .u32
147 logic_imm_1 \op \opq 0xffff00ff .i32
148 logic_imm_1 \op \opq 0xff00ffff .i32
149 logic_imm_1 \op \opq 0x00ffffff .i32
150 logic_imm_1 \op \opq 0xff5aff5a .i32
151 logic_imm_1 \op \opq 0x5aff5aff .i32
152 logic_imm_1 \op \opq 0xff00 .i16
153 logic_imm_1 \op \opq 0x00ff .i16
154 logic_imm_1 \op \opq 0xff .i8
157 logic_inv_imm vand vandq
158 logic_inv_imm vorn vornq
160 regs3_ntyp vbsl vbslq
161 regs3_ntyp vbit vbitq
162 regs3_ntyp vbif vbifq
164 .macro regs3_suf_32 op opq
166 regs3_1 \op \opq .s16
167 regs3_1 \op \opq .s32
169 regs3_1 \op \opq .u16
170 regs3_1 \op \opq .u32
171 regs3_1 \op \opq .f32
174 .macro regs3_if_32 op opq
176 regs3_1 \op \opq .i16
177 regs3_1 \op \opq .i32
178 regs3_1 \op \opq .s32
179 regs3_1 \op \opq .u32
180 regs3_1 \op \opq .f32
183 regs3_suf_32 vabd vabdq
184 regs3_suf_32 vmax vmaxq
185 regs3_suf_32 vmin vminq
187 regs3_suf_32 vcge vcgeq
188 regs3_suf_32 vcgt vcgtq
189 regs3_suf_32 vcle vcleq
190 regs3_suf_32 vclt vcltq
192 regs3_if_32 vceq vceqq
194 .macro regs2i_sf_0 op opq
195 regs2i_1 \op \opq 0 .s8
196 regs2i_1 \op \opq 0 .s16
197 regs2i_1 \op \opq 0 .s32
198 regs2i_1 \op \opq 0 .f32
201 regs2i_sf_0 vcge vcgeq
202 regs2i_sf_0 vcgt vcgtq
203 regs2i_sf_0 vcle vcleq
204 regs2i_sf_0 vclt vcltq
206 .macro regs2i_if_0 op opq
207 regs2i_1 \op \opq 0 .i8
208 regs2i_1 \op \opq 0 .i16
209 regs2i_1 \op \opq 0 .i32
210 regs2i_1 \op \opq 0 .s32
211 regs2i_1 \op \opq 0 .u32
212 regs2i_1 \op \opq 0 .f32
215 regs2i_if_0 vceq vceqq
217 .macro dregs3_suf_32 op
230 .macro sregs3_1 op opq vtype
236 .macro sclr21_1 op opq vtype
237 \op\vtype q0,q0,d0[0]
238 \opq\vtype q0,q0,d0[0]
239 \op\vtype d0,d0,d0[0]
242 .macro mul_incl_scalar op opq
244 regs3_1 \op \opq .i16
245 regs3_1 \op \opq .i32
246 regs3_1 \op \opq .s32
247 regs3_1 \op \opq .u32
248 regs3_1 \op \opq .f32
249 sclr21_1 \op \opq .i16
250 sclr21_1 \op \opq .i32
251 sclr21_1 \op \opq .s32
252 sclr21_1 \op \opq .u32
253 sclr21_1 \op \opq .f32
256 mul_incl_scalar vmla vmlaq
257 mul_incl_scalar vmls vmlsq
259 .macro dregs3_if_32 op
270 .macro regs3_if_64 op opq
272 regs3_1 \op \opq .i16
273 regs3_1 \op \opq .i32
274 regs3_1 \op \opq .s32
275 regs3_1 \op \opq .u32
276 regs3_1 \op \opq .i64
277 regs3_1 \op \opq .f32
280 regs3_if_64 vadd vaddq
281 regs3_if_64 vsub vsubq
283 .macro regs3_sz_32 op opq
289 regs3_sz_32 vtst vtstq
291 .macro regs3_ifp_32 op opq
293 regs3_1 \op \opq .i16
294 regs3_1 \op \opq .i32
295 regs3_1 \op \opq .s32
296 regs3_1 \op \opq .u32
297 regs3_1 \op \opq .f32
301 regs3_ifp_32 vmul vmulq
303 .macro dqmulhs op opq
304 regs3_1 \op \opq .s16
305 regs3_1 \op \opq .s32
306 sclr21_1 \op \opq .s16
307 sclr21_1 \op \opq .s32
310 dqmulhs vqdmulh vqdmulhq
311 dqmulhs vqrdmulh vqrdmulhq
313 regs3_1 vacge vacgeq .f32
314 regs3_1 vacgt vacgtq .f32
315 regs3_1 vacle vacleq .f32
316 regs3_1 vaclt vacltq .f32
317 regs3_1 vrecps vrecpsq .f32
318 regs3_1 vrsqrts vrsqrtsq .f32
320 .macro regs2_sf_32 op opq
322 regs2_1 \op \opq .s16
323 regs2_1 \op \opq .s32
324 regs2_1 \op \opq .f32
327 regs2_sf_32 vabs vabsq
328 regs2_sf_32 vneg vnegq
330 .macro rshift_imm op opq
331 regs2i_1 \op \opq 7 .s8
332 regs2i_1 \op \opq 15 .s16
333 regs2i_1 \op \opq 31 .s32
334 regs2i_1 \op \opq 63 .s64
335 regs2i_1 \op \opq 7 .u8
336 regs2i_1 \op \opq 15 .u16
337 regs2i_1 \op \opq 31 .u32
338 regs2i_1 \op \opq 63 .u64
341 rshift_imm vshr vshrq
342 rshift_imm vrshr vrshrq
343 rshift_imm vsra vsraq
344 rshift_imm vrsra vrsraq
346 regs2i_1 vsli vsliq 0 .8
347 regs2i_1 vsli vsliq 0 .16
348 regs2i_1 vsli vsliq 0 .32
349 regs2i_1 vsli vsliq 0 .64
351 regs2i_1 vsri vsriq 7 .8
352 regs2i_1 vsri vsriq 15 .16
353 regs2i_1 vsri vsriq 31 .32
354 regs2i_1 vsri vsriq 63 .64
356 regs2i_1 vqshlu vqshluq 0 .s8
357 regs2i_1 vqshlu vqshluq 0 .s16
358 regs2i_1 vqshlu vqshluq 0 .s32
359 regs2i_1 vqshlu vqshluq 0 .s64
361 .macro qrshift_imm op
370 .macro qrshiftu_imm op
376 .macro qrshifti_imm op
387 qrshiftu_imm vqrshrun
400 regl3_1 vshll 16 .i16
401 regl3_1 vshll 32 .i32
402 regl3_1 vshll 32 .s32
403 regl3_1 vshll 32 .u32
405 .macro convert op opr arg="" t1=".s32.f32" t2=".u32.f32" t3=".f32.s32" t4=".f32.u32"
416 convert vcvtq q0 ",1"
432 .macro mov_imm op imm vtype
437 mov_imm vmov 0x00000077 .i32
438 mov_imm vmov 0x00000077 .s32
439 mov_imm vmov 0x00000077 .u32
440 mov_imm vmvn 0x00000077 .i32
441 mov_imm vmvn 0x00000077 .s32
442 mov_imm vmvn 0x00000077 .u32
443 mov_imm vmov 0x00007700 .i32
444 mov_imm vmvn 0x00007700 .i32
445 mov_imm vmov 0x00770000 .i32
446 mov_imm vmvn 0x00770000 .i32
447 mov_imm vmov 0x77000000 .i32
448 mov_imm vmvn 0x77000000 .i32
449 mov_imm vmov 0x0077 .i16
450 mov_imm vmvn 0x0077 .i16
451 mov_imm vmov 0x7700 .i16
452 mov_imm vmvn 0x7700 .i16
453 mov_imm vmov 0x000077ff .i32
454 mov_imm vmvn 0x000077ff .i32
455 mov_imm vmov 0x0077ffff .i32
456 mov_imm vmvn 0x0077ffff .i32
457 mov_imm vmov 0x77 .i8
458 mov_imm vmov 0xff0000ff000000ff .i64
459 mov_imm vmov 4.25 .f32
461 mov_imm vmov 0xa5a5 .i16
462 mov_imm vmvn 0xa5a5 .i16
463 mov_imm vmov 0xa5a5a5a5 .i32
464 mov_imm vmvn 0xa5a5a5a5 .i32
465 mov_imm vmov 0x00a500a5 .i32
466 mov_imm vmov 0xa500a500 .i32
467 mov_imm vmov 0xa5a5a5a5a5a5a5a5 .i64
468 mov_imm vmvn 0xa5a5a5a5a5a5a5a5 .i64
469 mov_imm vmov 0x00a500a500a500a5 .i64
470 mov_imm vmov 0xa500a500a500a500 .i64
471 mov_imm vmov 0x000000a5000000a5 .i64
472 mov_imm vmov 0x0000a5000000a500 .i64
473 mov_imm vmov 0x00a5000000a50000 .i64
474 mov_imm vmov 0xa5000000a5000000 .i64
475 mov_imm vmov 0x0000a5ff0000a5ff .i64
476 mov_imm vmov 0x00a5ffff00a5ffff .i64
477 mov_imm vmov 0xa5ffffffa5ffffff .i64
504 regl3_1 \op "d0[0]" .s16
505 regl3_1 \op "d0[0]" .s32
506 regl3_1 \op "d0[0]" .u16
507 regl3_1 \op "d0[0]" .u32
541 regl3_1 \op "d0[0]" .s16
542 regl3_1 \op "d0[0]" .s32
550 regl3_1 vmull d0 .s16
551 regl3_1 vmull d0 .s32
553 regl3_1 vmull d0 .u16
554 regl3_1 vmull d0 .u32
556 regl3_1 vmull "d0[0]" .s16
557 regl3_1 vmull "d0[0]" .s32
558 regl3_1 vmull "d0[0]" .u16
559 regl3_1 vmull "d0[0]" .u32
566 .macro revs op opq vtype
572 revs vrev64 vrev64q .8
573 revs vrev64 vrev64q .16
574 revs vrev64 vrev64q .32
575 revs vrev32 vrev32q .8
576 revs vrev32 vrev32q .16
577 revs vrev16 vrev16q .8
579 .macro dups op opq vtype
592 .macro binop_3typ op op1 op2 t1 t2 t3
598 binop_3typ vmovl q0 d0 .s8 .s16 .s32
599 binop_3typ vmovl q0 d0 .u8 .u16 .u32
600 binop_3typ vmovn d0 q0 .i16 .i32 .i64
603 binop_3typ vqmovn d0 q0 .s16 .s32 .s64
604 binop_3typ vqmovn d0 q0 .u16 .u32 .u64
605 binop_3typ vqmovun d0 q0 .s16 .s32 .s64
607 .macro binops op opq vtype="" rhs="0"
613 .macro regs2_sz_32 op opq
615 binops \op \opq .16 1
616 binops \op \opq .32 1
619 regs2_sz_32 vzip vzipq
620 regs2_sz_32 vuzp vuzpq
622 .macro regs2_s_32 op opq
628 regs2_s_32 vqabs vqabsq
629 regs2_s_32 vqneg vqnegq
631 .macro regs2_su_32 op opq
638 regs2_su_32 vpadal vpadalq
639 regs2_su_32 vpaddl vpaddlq
641 binops vrecpe vrecpeq .u32
642 binops vrecpe vrecpeq .f32
643 binops vrsqrte vrsqrteq .u32
644 binops vrsqrte vrsqrteq .f32
646 regs2_s_32 vcls vclsq
648 .macro regs2_i_32 op opq
656 regs2_i_32 vclz vclzq
660 binops vswp vswpq "" 1
662 regs2_sz_32 vtrn vtrnq