gas/testsuite/gas/arm/vfp-neon-syntax-inc.s

   1 @ VFP with Neon-style syntax
   2         .syntax unified
   3
   4         .include "itblock.s"
   5
   6 func:
   7         .macro testvmov cond="" f32=".f32" f64=".f64"
   8         itblock 4 \cond
   9         vmov\cond\f32 s0,s1
  10         vmov\cond\f64 d0,d1
  11         vmov\cond\f32 s0,#0.25
  12         vmov\cond\f64 d0,#1
  13         itblock 4 \cond
  14         vmov\cond r0,s1
  15         vmov\cond s0,r1
  16         vmov\cond r0,r1,s2,s3
  17         vmov\cond s0,s1,r2,r4
  18         .endm
  19
  20         @ Test VFP vmov variants. These can all be conditional.
  21         testvmov
  22         testvmov eq
  23
  24         .macro monadic op cond="" f32=".f32" f64=".f64"
  25         itblock 2 \cond
  26         \op\cond\f32 s0,s1
  27         \op\cond\f64 d0,d1
  28         .endm
  29
  30         .macro monadic_c op
  31         monadic \op
  32         monadic \op eq
  33         .endm
  34
  35         .macro dyadic op cond="" f32=".f32" f64=".f64"
  36         itblock 2 \cond
  37         \op\cond\f32 s0,s1,s2
  38         \op\cond\f64 d0,d1,d2
  39         .endm
  40
  41         .macro dyadic_c op
  42         dyadic \op
  43         dyadic \op eq
  44         .endm
  45
  46         .macro dyadicz op cond="" f32=".f32" f64=".f64"
  47         itblock 2 \cond
  48         \op\cond\f32 s0,#0
  49         \op\cond\f64 d0,#0
  50         .endm
  51
  52         .macro dyadicz_c op
  53         dyadicz \op
  54         dyadicz \op eq
  55         .endm
  56
  57         monadic_c vsqrt
  58         monadic_c vabs
  59         monadic_c vneg
  60         monadic_c vcmp
  61         monadic_c vcmpe
  62
  63         dyadic_c vnmul
  64         dyadic_c vnmla
  65         dyadic_c vnmls
  66
  67         dyadic_c vmul
  68         dyadic_c vmla
  69         dyadic_c vmls
  70
  71         dyadic_c vadd
  72         dyadic_c vsub
  73
  74         dyadic_c vdiv
  75
  76         dyadicz_c vcmp
  77         dyadicz_c vcmpe
  78
  79         .macro cvtz cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64"
  80         itblock 4 \cond
  81         vcvtz\cond\s32\f32 s0,s1
  82         vcvtz\cond\u32\f32 s0,s1
  83         vcvtz\cond\s32\f64 s0,d1
  84         vcvtz\cond\u32\f64 s0,d1
  85         .endm
  86
  87         cvtz
  88         cvtz eq
  89
  90         .macro cvt cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64"
  91         itblock 4 \cond
  92         vcvt\cond\s32\f32 s0,s1
  93         vcvt\cond\u32\f32 s0,s1
  94         vcvt\cond\f32\s32 s0,s1
  95         vcvt\cond\f32\u32 s0,s1
  96         itblock 4 \cond
  97         vcvt\cond\f32\f64 s0,d1
  98         vcvt\cond\f64\f32 d0,s1
  99         vcvt\cond\s32\f64 s0,d1
 100         vcvt\cond\u32\f64 s0,d1
 101         itblock 2 \cond
 102         vcvt\cond\f64\s32 d0,s1
 103         vcvt\cond\f64\u32 d0,s1
 104         .endm
 105
 106         cvt
 107         cvt eq
 108
 109         .macro cvti cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" s16=".s16" u16=".u16"
 110         itblock 4 \cond
 111         vcvt\cond\s32\f32 s0,s0,#1
 112         vcvt\cond\u32\f32 s0,s0,#1
 113         vcvt\cond\f32\s32 s0,s0,#1
 114         vcvt\cond\f32\u32 s0,s0,#1
 115         itblock 4 \cond
 116         vcvt\cond\s32\f64 d0,d0,#1
 117         vcvt\cond\u32\f64 d0,d0,#1
 118         vcvt\cond\f64\s32 d0,d0,#1
 119         vcvt\cond\f64\u32 d0,d0,#1
 120         itblock 4 \cond
 121         vcvt\cond\f32\s16 s0,s0,#1
 122         vcvt\cond\f32\u16 s0,s0,#1
 123         vcvt\cond\f64\s16 d0,d0,#1
 124         vcvt\cond\f64\u16 d0,d0,#1
 125         itblock 4 \cond
 126         vcvt\cond\s16\f32 s0,s0,#1
 127         vcvt\cond\u16\f32 s0,s0,#1
 128         vcvt\cond\s16\f64 d0,d0,#1
 129         vcvt\cond\u16\f64 d0,d0,#1
 130         .endm
 131
 132         cvti
 133         cvti eq
 134
 135         .macro multi op cond="" n="" ia="ia" db="db"
 136         itblock 4 \cond
 137         \op\n\cond r0,{s3-s6}
 138         \op\ia\cond r0,{s3-s6}
 139         \op\ia\cond r0!,{s3-s6}
 140         \op\db\cond r0!,{s3-s6}
 141         itblock 4 \cond
 142         \op\n\cond r0,{d3-d6}
 143         \op\ia\cond r0,{d3-d6}
 144         \op\ia\cond r0!,{d3-d6}
 145         \op\db\cond r0!,{d3-d6}
 146         .endm
 147
 148         multi vldm
 149         multi vldm eq
 150         multi vstm
 151         multi vstm eq
 152
 153         .macro single op cond=""
 154         itblock 2 \cond
 155         \op\cond s0,[r0,#4]
 156         \op\cond d0,[r0,#4]
 157         .endm
 158
 159         single vldr
 160         single vldr eq
 161         single vstr
 162         single vstr eq