i386: Also check R12-R15 registers when optimizing testq to testb
[deliverable/binutils-gdb.git] / gas / testsuite / gas / i386 / avx512dq-rcigru-intel.d
1 #as: -mevexrcig=ru
2 #objdump: -dw -Mintel
3 #name: i386 AVX512DQ rcig insns (Intel disassembly)
4 #source: avx512dq-rcig.s
5
6 .*: +file format .*
7
8
9 Disassembly of section \.text:
10
11 00000000 <_start>:
12 [ ]*[a-f0-9]+:[ ]*62 f3 d5 58 50 f4 ab[ ]*vrangepd zmm6,zmm5,zmm4,\{sae\},0xab
13 [ ]*[a-f0-9]+:[ ]*62 f3 d5 58 50 f4 7b[ ]*vrangepd zmm6,zmm5,zmm4,\{sae\},0x7b
14 [ ]*[a-f0-9]+:[ ]*62 f3 55 58 50 f4 ab[ ]*vrangeps zmm6,zmm5,zmm4,\{sae\},0xab
15 [ ]*[a-f0-9]+:[ ]*62 f3 55 58 50 f4 7b[ ]*vrangeps zmm6,zmm5,zmm4,\{sae\},0x7b
16 [ ]*[a-f0-9]+:[ ]*62 f3 d5 5f 51 f4 ab[ ]*vrangesd xmm6\{k7\},xmm5,xmm4,\{sae\},0xab
17 [ ]*[a-f0-9]+:[ ]*62 f3 d5 5f 51 f4 7b[ ]*vrangesd xmm6\{k7\},xmm5,xmm4,\{sae\},0x7b
18 [ ]*[a-f0-9]+:[ ]*62 f3 55 5f 51 f4 ab[ ]*vrangess xmm6\{k7\},xmm5,xmm4,\{sae\},0xab
19 [ ]*[a-f0-9]+:[ ]*62 f3 55 5f 51 f4 7b[ ]*vrangess xmm6\{k7\},xmm5,xmm4,\{sae\},0x7b
20 [ ]*[a-f0-9]+:[ ]*62 f3 fd 58 56 f5 ab[ ]*vreducepd zmm6,zmm5,\{sae\},0xab
21 [ ]*[a-f0-9]+:[ ]*62 f3 fd 58 56 f5 7b[ ]*vreducepd zmm6,zmm5,\{sae\},0x7b
22 [ ]*[a-f0-9]+:[ ]*62 f3 7d 58 56 f5 ab[ ]*vreduceps zmm6,zmm5,\{sae\},0xab
23 [ ]*[a-f0-9]+:[ ]*62 f3 7d 58 56 f5 7b[ ]*vreduceps zmm6,zmm5,\{sae\},0x7b
24 [ ]*[a-f0-9]+:[ ]*62 f3 d5 5f 57 f4 ab[ ]*vreducesd xmm6\{k7\},xmm5,xmm4,\{sae\},0xab
25 [ ]*[a-f0-9]+:[ ]*62 f3 d5 5f 57 f4 7b[ ]*vreducesd xmm6\{k7\},xmm5,xmm4,\{sae\},0x7b
26 [ ]*[a-f0-9]+:[ ]*62 f3 55 5f 57 f4 ab[ ]*vreducess xmm6\{k7\},xmm5,xmm4,\{sae\},0xab
27 [ ]*[a-f0-9]+:[ ]*62 f3 55 5f 57 f4 7b[ ]*vreducess xmm6\{k7\},xmm5,xmm4,\{sae\},0x7b
28 [ ]*[a-f0-9]+:[ ]*62 f1 fd 58 7a f5[ ]*vcvttpd2qq zmm6,zmm5,\{sae\}
29 [ ]*[a-f0-9]+:[ ]*62 f1 fd 58 78 f5[ ]*vcvttpd2uqq zmm6,zmm5,\{sae\}
30 [ ]*[a-f0-9]+:[ ]*62 f1 7d 5f 7a f5[ ]*vcvttps2qq zmm6\{k7\},ymm5,\{sae\}
31 [ ]*[a-f0-9]+:[ ]*62 f1 7d 5f 78 f5[ ]*vcvttps2uqq zmm6\{k7\},ymm5,\{sae\}
32 [ ]*[a-f0-9]+:[ ]*62 f3 d5 58 50 f4 ab[ ]*vrangepd zmm6,zmm5,zmm4,\{sae\},0xab
33 [ ]*[a-f0-9]+:[ ]*62 f3 d5 58 50 f4 7b[ ]*vrangepd zmm6,zmm5,zmm4,\{sae\},0x7b
34 [ ]*[a-f0-9]+:[ ]*62 f3 55 58 50 f4 ab[ ]*vrangeps zmm6,zmm5,zmm4,\{sae\},0xab
35 [ ]*[a-f0-9]+:[ ]*62 f3 55 58 50 f4 7b[ ]*vrangeps zmm6,zmm5,zmm4,\{sae\},0x7b
36 [ ]*[a-f0-9]+:[ ]*62 f3 d5 5f 51 f4 ab[ ]*vrangesd xmm6\{k7\},xmm5,xmm4,\{sae\},0xab
37 [ ]*[a-f0-9]+:[ ]*62 f3 d5 5f 51 f4 7b[ ]*vrangesd xmm6\{k7\},xmm5,xmm4,\{sae\},0x7b
38 [ ]*[a-f0-9]+:[ ]*62 f3 55 5f 51 f4 ab[ ]*vrangess xmm6\{k7\},xmm5,xmm4,\{sae\},0xab
39 [ ]*[a-f0-9]+:[ ]*62 f3 55 5f 51 f4 7b[ ]*vrangess xmm6\{k7\},xmm5,xmm4,\{sae\},0x7b
40 [ ]*[a-f0-9]+:[ ]*62 f3 fd 58 56 f5 ab[ ]*vreducepd zmm6,zmm5,\{sae\},0xab
41 [ ]*[a-f0-9]+:[ ]*62 f3 fd 58 56 f5 7b[ ]*vreducepd zmm6,zmm5,\{sae\},0x7b
42 [ ]*[a-f0-9]+:[ ]*62 f3 7d 58 56 f5 ab[ ]*vreduceps zmm6,zmm5,\{sae\},0xab
43 [ ]*[a-f0-9]+:[ ]*62 f3 7d 58 56 f5 7b[ ]*vreduceps zmm6,zmm5,\{sae\},0x7b
44 [ ]*[a-f0-9]+:[ ]*62 f3 d5 5f 57 f4 ab[ ]*vreducesd xmm6\{k7\},xmm5,xmm4,\{sae\},0xab
45 [ ]*[a-f0-9]+:[ ]*62 f3 d5 5f 57 f4 7b[ ]*vreducesd xmm6\{k7\},xmm5,xmm4,\{sae\},0x7b
46 [ ]*[a-f0-9]+:[ ]*62 f3 55 5f 57 f4 ab[ ]*vreducess xmm6\{k7\},xmm5,xmm4,\{sae\},0xab
47 [ ]*[a-f0-9]+:[ ]*62 f3 55 5f 57 f4 7b[ ]*vreducess xmm6\{k7\},xmm5,xmm4,\{sae\},0x7b
48 [ ]*[a-f0-9]+:[ ]*62 f1 fd 58 7a f5[ ]*vcvttpd2qq zmm6,zmm5,\{sae\}
49 [ ]*[a-f0-9]+:[ ]*62 f1 fd 58 78 f5[ ]*vcvttpd2uqq zmm6,zmm5,\{sae\}
50 [ ]*[a-f0-9]+:[ ]*62 f1 7d 5f 7a f5[ ]*vcvttps2qq zmm6\{k7\},ymm5,\{sae\}
51 [ ]*[a-f0-9]+:[ ]*62 f1 7d 5f 78 f5[ ]*vcvttps2uqq zmm6\{k7\},ymm5,\{sae\}
52 #pass
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