Add -mevexrcig={rne|rd|ru|rz} option to x86 assembler.
[deliverable/binutils-gdb.git] / gas / testsuite / gas / i386 / avx512er-rcigru.d
1 #as: -mevexrcig=ru
2 #objdump: -dw
3 #name: i386 AVX512ER rcig insns
4 #source: avx512er-rcig.s
5
6 .*: +file format .*
7
8
9 Disassembly of section \.text:
10
11 00000000 <_start>:
12 [ ]*[a-f0-9]+:[ ]*62 f2 7d 58 c8 f5[ ]*vexp2ps \{sae\},%zmm5,%zmm6
13 [ ]*[a-f0-9]+:[ ]*62 f2 fd 58 c8 f5[ ]*vexp2pd \{sae\},%zmm5,%zmm6
14 [ ]*[a-f0-9]+:[ ]*62 f2 7d 58 ca f5[ ]*vrcp28ps \{sae\},%zmm5,%zmm6
15 [ ]*[a-f0-9]+:[ ]*62 f2 fd 58 ca f5[ ]*vrcp28pd \{sae\},%zmm5,%zmm6
16 [ ]*[a-f0-9]+:[ ]*62 f2 55 5f cb f4[ ]*vrcp28ss \{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
17 [ ]*[a-f0-9]+:[ ]*62 f2 d5 5f cb f4[ ]*vrcp28sd \{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
18 [ ]*[a-f0-9]+:[ ]*62 f2 7d 58 cc f5[ ]*vrsqrt28ps \{sae\},%zmm5,%zmm6
19 [ ]*[a-f0-9]+:[ ]*62 f2 fd 58 cc f5[ ]*vrsqrt28pd \{sae\},%zmm5,%zmm6
20 [ ]*[a-f0-9]+:[ ]*62 f2 55 5f cd f4[ ]*vrsqrt28ss \{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
21 [ ]*[a-f0-9]+:[ ]*62 f2 d5 5f cd f4[ ]*vrsqrt28sd \{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
22 [ ]*[a-f0-9]+:[ ]*62 f2 7d 58 c8 f5[ ]*vexp2ps \{sae\},%zmm5,%zmm6
23 [ ]*[a-f0-9]+:[ ]*62 f2 fd 58 c8 f5[ ]*vexp2pd \{sae\},%zmm5,%zmm6
24 [ ]*[a-f0-9]+:[ ]*62 f2 7d 58 ca f5[ ]*vrcp28ps \{sae\},%zmm5,%zmm6
25 [ ]*[a-f0-9]+:[ ]*62 f2 fd 58 ca f5[ ]*vrcp28pd \{sae\},%zmm5,%zmm6
26 [ ]*[a-f0-9]+:[ ]*62 f2 55 5f cb f4[ ]*vrcp28ss \{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
27 [ ]*[a-f0-9]+:[ ]*62 f2 d5 5f cb f4[ ]*vrcp28sd \{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
28 [ ]*[a-f0-9]+:[ ]*62 f2 7d 58 cc f5[ ]*vrsqrt28ps \{sae\},%zmm5,%zmm6
29 [ ]*[a-f0-9]+:[ ]*62 f2 fd 58 cc f5[ ]*vrsqrt28pd \{sae\},%zmm5,%zmm6
30 [ ]*[a-f0-9]+:[ ]*62 f2 55 5f cd f4[ ]*vrsqrt28ss \{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
31 [ ]*[a-f0-9]+:[ ]*62 f2 d5 5f cd f4[ ]*vrsqrt28sd \{sae\},%xmm4,%xmm5,%xmm6\{%k7\}
32 #pass
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