x86/Intel: improve diagnostics for ambiguous VCVT* operands
[deliverable/binutils-gdb.git] / gas / testsuite / gas / i386 / x86-64-avx512_4vnniw.d
1 #objdump: -dw
2 #name: x86_64 AVX512/4VNNIW insns
3 #source: x86-64-avx512_4vnniw.s
4
5 .*: +file format .*
6
7
8 Disassembly of section \.text:
9
10 0+ <_start>:
11 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 09[ ]*vp4dpwssd \(%rcx\),%zmm8,%zmm1
12 [ ]*[a-f0-9]+:[ ]*62 f2 3f 4f 52 09[ ]*vp4dpwssd \(%rcx\),%zmm8,%zmm1\{%k7\}
13 [ ]*[a-f0-9]+:[ ]*62 f2 3f cf 52 09[ ]*vp4dpwssd \(%rcx\),%zmm8,%zmm1\{%k7\}\{z\}
14 [ ]*[a-f0-9]+:[ ]*62 b2 3f 48 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%rax,%r14,8\),%zmm8,%zmm1
15 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%rdx\),%zmm8,%zmm1
16 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%rdx\),%zmm8,%zmm1
17 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%rdx\),%zmm8,%zmm1
18 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%rdx\),%zmm8,%zmm1
19 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 09[ ]*vp4dpwssds \(%rcx\),%zmm8,%zmm1
20 [ ]*[a-f0-9]+:[ ]*62 f2 3f 4f 53 09[ ]*vp4dpwssds \(%rcx\),%zmm8,%zmm1\{%k7\}
21 [ ]*[a-f0-9]+:[ ]*62 f2 3f cf 53 09[ ]*vp4dpwssds \(%rcx\),%zmm8,%zmm1\{%k7\}\{z\}
22 [ ]*[a-f0-9]+:[ ]*62 b2 3f 48 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%rax,%r14,8\),%zmm8,%zmm1
23 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%rdx\),%zmm8,%zmm1
24 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%rdx\),%zmm8,%zmm1
25 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%rdx\),%zmm8,%zmm1
26 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%rdx\),%zmm8,%zmm1
27 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 09[ ]*vp4dpwssd \(%rcx\),%zmm8,%zmm1
28 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 09[ ]*vp4dpwssd \(%rcx\),%zmm8,%zmm1
29 [ ]*[a-f0-9]+:[ ]*62 f2 3f 4f 52 09[ ]*vp4dpwssd \(%rcx\),%zmm8,%zmm1\{%k7\}
30 [ ]*[a-f0-9]+:[ ]*62 f2 3f cf 52 09[ ]*vp4dpwssd \(%rcx\),%zmm8,%zmm1\{%k7\}\{z\}
31 [ ]*[a-f0-9]+:[ ]*62 b2 3f 48 52 8c f0 c0 1d fe ff[ ]*vp4dpwssd -0x1e240\(%rax,%r14,8\),%zmm8,%zmm1
32 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a e0 0f 00 00[ ]*vp4dpwssd 0xfe0\(%rdx\),%zmm8,%zmm1
33 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a 00 10 00 00[ ]*vp4dpwssd 0x1000\(%rdx\),%zmm8,%zmm1
34 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a 00 f0 ff ff[ ]*vp4dpwssd -0x1000\(%rdx\),%zmm8,%zmm1
35 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 52 8a e0 ef ff ff[ ]*vp4dpwssd -0x1020\(%rdx\),%zmm8,%zmm1
36 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 09[ ]*vp4dpwssds \(%rcx\),%zmm8,%zmm1
37 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 09[ ]*vp4dpwssds \(%rcx\),%zmm8,%zmm1
38 [ ]*[a-f0-9]+:[ ]*62 f2 3f 4f 53 09[ ]*vp4dpwssds \(%rcx\),%zmm8,%zmm1\{%k7\}
39 [ ]*[a-f0-9]+:[ ]*62 f2 3f cf 53 09[ ]*vp4dpwssds \(%rcx\),%zmm8,%zmm1\{%k7\}\{z\}
40 [ ]*[a-f0-9]+:[ ]*62 b2 3f 48 53 8c f0 c0 1d fe ff[ ]*vp4dpwssds -0x1e240\(%rax,%r14,8\),%zmm8,%zmm1
41 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a e0 0f 00 00[ ]*vp4dpwssds 0xfe0\(%rdx\),%zmm8,%zmm1
42 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a 00 10 00 00[ ]*vp4dpwssds 0x1000\(%rdx\),%zmm8,%zmm1
43 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a 00 f0 ff ff[ ]*vp4dpwssds -0x1000\(%rdx\),%zmm8,%zmm1
44 [ ]*[a-f0-9]+:[ ]*62 f2 3f 48 53 8a e0 ef ff ff[ ]*vp4dpwssds -0x1020\(%rdx\),%zmm8,%zmm1
45 #pass
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