i386: Also check R12-R15 registers when optimizing testq to testb
[deliverable/binutils-gdb.git] / gas / testsuite / gas / i386 / x86-64-avx512_bf16.s
1 # Check 64bit AVX512_BF16 instructions
2
3 .allow_index_reg
4 .text
5 _start:
6 vcvtne2ps2bf16 %zmm28, %zmm29, %zmm30 #AVX512_BF16
7 vcvtne2ps2bf16 0x10000000(%rbp, %r14, 8), %zmm29, %zmm30{%k7} #AVX512_BF16 MASK_ENABLING
8 vcvtne2ps2bf16 (%r9){1to16}, %zmm29, %zmm30 #AVX512_BF16 BROADCAST_EN
9 vcvtne2ps2bf16 8128(%rcx), %zmm29, %zmm30 #AVX512_BF16 Disp8
10 vcvtne2ps2bf16 -8192(%rdx){1to16}, %zmm29, %zmm30{%k7}{z} #AVX512_BF16 Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
11 vcvtneps2bf16 %zmm29, %ymm30 #AVX512_BF16
12 vcvtneps2bf16 0x10000000(%rbp, %r14, 8), %ymm30{%k7} #AVX512_BF16 MASK_ENABLING
13 vcvtneps2bf16 (%r9){1to16}, %ymm30 #AVX512_BF16 BROADCAST_EN
14 vcvtneps2bf16 8128(%rcx), %ymm30 #AVX512_BF16 Disp8
15 vcvtneps2bf16 -8192(%rdx){1to16}, %ymm30{%k7}{z} #AVX512_BF16 Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
16 vdpbf16ps %zmm28, %zmm29, %zmm30 #AVX512_BF16
17 vdpbf16ps 0x10000000(%rbp, %r14, 8), %zmm29, %zmm30{%k7} #AVX512_BF16 MASK_ENABLING
18 vdpbf16ps (%r9){1to16}, %zmm29, %zmm30 #AVX512_BF16 BROADCAST_EN
19 vdpbf16ps 8128(%rcx), %zmm29, %zmm30 #AVX512_BF16 Disp8
20 vdpbf16ps -8192(%rdx){1to16}, %zmm29, %zmm30{%k7}{z} #AVX512_BF16 Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
21
22 .intel_syntax noprefix
23 vcvtne2ps2bf16 zmm30, zmm29, zmm28 #AVX512_BF16
24 vcvtne2ps2bf16 zmm30{k7}, zmm29, ZMMWORD PTR [rbp+r14*8+0x10000000] #AVX512_BF16 MASK_ENABLING
25 vcvtne2ps2bf16 zmm30, zmm29, DWORD PTR [r9]{1to16} #AVX512_BF16 BROADCAST_EN
26 vcvtne2ps2bf16 zmm30, zmm29, ZMMWORD PTR [rcx+8128] #AVX512_BF16 Disp8
27 vcvtne2ps2bf16 zmm30{k7}{z}, zmm29, DWORD PTR [rdx-8192]{1to16} #AVX512_BF16 Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
28 vcvtneps2bf16 ymm30, zmm29 #AVX512_BF16
29 vcvtneps2bf16 ymm30{k7}, ZMMWORD PTR [rbp+r14*8+0x10000000] #AVX512_BF16 MASK_ENABLING
30 vcvtneps2bf16 ymm30, DWORD PTR [r9]{1to16} #AVX512_BF16 BROADCAST_EN
31 vcvtneps2bf16 ymm30, ZMMWORD PTR [rcx+8128] #AVX512_BF16 Disp8
32 vcvtneps2bf16 ymm30{k7}{z}, DWORD PTR [rdx-8192]{1to16} #AVX512_BF16 Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
33 vdpbf16ps zmm30, zmm29, zmm28 #AVX512_BF16
34 vdpbf16ps zmm30{k7}, zmm29, ZMMWORD PTR [rbp+r14*8+0x10000000] #AVX512_BF16 MASK_ENABLING
35 vdpbf16ps zmm30, zmm29, DWORD PTR [r9]{1to16} #AVX512_BF16 BROADCAST_EN
36 vdpbf16ps zmm30, zmm29, ZMMWORD PTR [rcx+8128] #AVX512_BF16 Disp8
37 vdpbf16ps zmm30{k7}{z}, zmm29, DWORD PTR [rdx-8192]{1to16} #AVX512_BF16 Disp8 BROADCAST_EN MASK_ENABLING ZEROCTL
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