Enable Intel VPCLMULQDQ instruction.
[deliverable/binutils-gdb.git] / gas / testsuite / gas / i386 / x86-64-avx512f_vpclmulqdq-intel.d
1 #as:
2 #objdump: -dw -Mintel
3 #name: x86_64 AVX512F/VPCLMULQDQ insns (Intel disassembly)
4 #source: x86-64-avx512f_vpclmulqdq.s
5
6 .*: +file format .*
7
8
9 Disassembly of section \.text:
10
11 0+ <_start>:
12 [ ]*[a-f0-9]+:[ ]*62 03 45 40 44 d0 ab[ ]*vpclmulqdq zmm26,zmm23,zmm24,0xab
13 [ ]*[a-f0-9]+:[ ]*62 23 45 40 44 94 f0 23 01 00 00 7b[ ]*vpclmulqdq zmm26,zmm23,ZMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
14 [ ]*[a-f0-9]+:[ ]*62 63 45 40 44 52 7f 7b[ ]*vpclmulqdq zmm26,zmm23,ZMMWORD PTR \[rdx\+0x1fc0\],0x7b
15 [ ]*[a-f0-9]+:[ ]*62 83 55 40 44 eb ab[ ]*vpclmulqdq zmm21,zmm21,zmm27,0xab
16 [ ]*[a-f0-9]+:[ ]*62 a3 55 40 44 ac f0 34 12 00 00 7b[ ]*vpclmulqdq zmm21,zmm21,ZMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
17 [ ]*[a-f0-9]+:[ ]*62 e3 55 40 44 6a 7f 7b[ ]*vpclmulqdq zmm21,zmm21,ZMMWORD PTR \[rdx\+0x1fc0\],0x7b
18 #pass
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