i386: Also check R12-R15 registers when optimizing testq to testb
[deliverable/binutils-gdb.git] / gas / testsuite / gas / i386 / x86-64-avx_gfni-intel.d
1 #as:
2 #objdump: -dw -Mintel
3 #name: x86_64 AVX/GFNI insns (Intel disassembly)
4 #source: x86-64-avx_gfni.s
5
6 .*: +file format .*
7
8
9 Disassembly of section \.text:
10
11 0+ <_start>:
12 [ ]*[a-f0-9]+:[ ]*c4 e2 55 cf f4[ ]*vgf2p8mulb ymm6,ymm5,ymm4
13 [ ]*[a-f0-9]+:[ ]*c4 a2 55 cf b4 f0 c0 1d fe ff[ ]*vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\]
14 [ ]*[a-f0-9]+:[ ]*c4 e2 55 cf 72 7e[ ]*vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx\+0x7e\]
15 [ ]*[a-f0-9]+:[ ]*c4 e3 d5 ce f4 ab[ ]*vgf2p8affineqb ymm6,ymm5,ymm4,0xab
16 [ ]*[a-f0-9]+:[ ]*c4 a3 d5 ce b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
17 [ ]*[a-f0-9]+:[ ]*c4 e3 d5 ce 72 7e 7b[ ]*vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x7e\],0x7b
18 [ ]*[a-f0-9]+:[ ]*c4 e3 d5 cf f4 ab[ ]*vgf2p8affineinvqb ymm6,ymm5,ymm4,0xab
19 [ ]*[a-f0-9]+:[ ]*c4 a3 d5 cf b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
20 [ ]*[a-f0-9]+:[ ]*c4 e3 d5 cf 72 7e 7b[ ]*vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x7e\],0x7b
21 [ ]*[a-f0-9]+:[ ]*c4 e2 51 cf f4[ ]*vgf2p8mulb xmm6,xmm5,xmm4
22 [ ]*[a-f0-9]+:[ ]*c4 a2 51 cf b4 f0 c0 1d fe ff[ ]*vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
23 [ ]*[a-f0-9]+:[ ]*c4 e2 51 cf 72 7e[ ]*vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7e\]
24 [ ]*[a-f0-9]+:[ ]*c4 e3 d1 ce f4 ab[ ]*vgf2p8affineqb xmm6,xmm5,xmm4,0xab
25 [ ]*[a-f0-9]+:[ ]*c4 a3 d1 ce b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
26 [ ]*[a-f0-9]+:[ ]*c4 e3 d1 ce 72 7e 7b[ ]*vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7e\],0x7b
27 [ ]*[a-f0-9]+:[ ]*c4 e3 d1 cf f4 ab[ ]*vgf2p8affineinvqb xmm6,xmm5,xmm4,0xab
28 [ ]*[a-f0-9]+:[ ]*c4 a3 d1 cf b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
29 [ ]*[a-f0-9]+:[ ]*c4 e3 d1 cf 72 7e 7b[ ]*vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7e\],0x7b
30 [ ]*[a-f0-9]+:[ ]*c4 e2 55 cf f4[ ]*vgf2p8mulb ymm6,ymm5,ymm4
31 [ ]*[a-f0-9]+:[ ]*c4 a2 55 cf b4 f0 c0 1d fe ff[ ]*vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\]
32 [ ]*[a-f0-9]+:[ ]*c4 e2 55 cf 72 7e[ ]*vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx\+0x7e\]
33 [ ]*[a-f0-9]+:[ ]*c4 e3 d5 ce f4 ab[ ]*vgf2p8affineqb ymm6,ymm5,ymm4,0xab
34 [ ]*[a-f0-9]+:[ ]*c4 a3 d5 ce b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
35 [ ]*[a-f0-9]+:[ ]*c4 e3 d5 ce 72 7e 7b[ ]*vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x7e\],0x7b
36 [ ]*[a-f0-9]+:[ ]*c4 e3 d5 cf f4 ab[ ]*vgf2p8affineinvqb ymm6,ymm5,ymm4,0xab
37 [ ]*[a-f0-9]+:[ ]*c4 a3 d5 cf b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
38 [ ]*[a-f0-9]+:[ ]*c4 e3 d5 cf 72 7e 7b[ ]*vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x7e\],0x7b
39 [ ]*[a-f0-9]+:[ ]*c4 e2 51 cf f4[ ]*vgf2p8mulb xmm6,xmm5,xmm4
40 [ ]*[a-f0-9]+:[ ]*c4 a2 51 cf b4 f0 c0 1d fe ff[ ]*vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
41 [ ]*[a-f0-9]+:[ ]*c4 e2 51 cf 72 7e[ ]*vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7e\]
42 [ ]*[a-f0-9]+:[ ]*c4 e3 d1 ce f4 ab[ ]*vgf2p8affineqb xmm6,xmm5,xmm4,0xab
43 [ ]*[a-f0-9]+:[ ]*c4 a3 d1 ce b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
44 [ ]*[a-f0-9]+:[ ]*c4 e3 d1 ce 72 7e 7b[ ]*vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7e\],0x7b
45 [ ]*[a-f0-9]+:[ ]*c4 e3 d1 cf f4 ab[ ]*vgf2p8affineinvqb xmm6,xmm5,xmm4,0xab
46 [ ]*[a-f0-9]+:[ ]*c4 a3 d1 cf b4 f0 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
47 [ ]*[a-f0-9]+:[ ]*c4 e3 d1 cf 72 7e 7b[ ]*vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7e\],0x7b
48 #pass
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