1 #source: x86-64-lfence-ret.s
2 #as: -mlfence-before-ret=not
3 #warning_output: x86-64-lfence-ret.e
4 #objdump: -dw -Mintel64
5 #name: x86-64 -mlfence-before-ret=not
10 Disassembly of section .text:
13 +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
14 +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
15 +[a-f0-9]+: 0f ae e8 lfence
16 +[a-f0-9]+: 66 c3 data16 retq
17 +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
18 +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
19 +[a-f0-9]+: 0f ae e8 lfence
20 +[a-f0-9]+: 66 c2 14 00 data16 retq \$0x14
21 +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
22 +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
23 +[a-f0-9]+: 0f ae e8 lfence
25 +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
26 +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
27 +[a-f0-9]+: 0f ae e8 lfence
28 +[a-f0-9]+: c2 1e 00 retq \$0x1e
29 +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
30 +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
31 +[a-f0-9]+: 0f ae e8 lfence
32 +[a-f0-9]+: 66 48 c3 data16 rex.W retq
33 +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
34 +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
35 +[a-f0-9]+: 0f ae e8 lfence
36 +[a-f0-9]+: 66 48 c2 28 00 data16 rex.W retq \$0x28
37 +[a-f0-9]+: 66 f7 14 24 notw \(%rsp\)
38 +[a-f0-9]+: 66 f7 14 24 notw \(%rsp\)
39 +[a-f0-9]+: 0f ae e8 lfence
40 +[a-f0-9]+: 66 cb lretw
41 +[a-f0-9]+: 66 f7 14 24 notw \(%rsp\)
42 +[a-f0-9]+: 66 f7 14 24 notw \(%rsp\)
43 +[a-f0-9]+: 0f ae e8 lfence
44 +[a-f0-9]+: 66 ca 28 00 lretw \$0x28
45 +[a-f0-9]+: f7 14 24 notl \(%rsp\)
46 +[a-f0-9]+: f7 14 24 notl \(%rsp\)
47 +[a-f0-9]+: 0f ae e8 lfence
49 +[a-f0-9]+: f7 14 24 notl \(%rsp\)
50 +[a-f0-9]+: f7 14 24 notl \(%rsp\)
51 +[a-f0-9]+: 0f ae e8 lfence
52 +[a-f0-9]+: ca 28 00 lret \$0x28
53 +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
54 +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
55 +[a-f0-9]+: 0f ae e8 lfence
56 +[a-f0-9]+: 48 cb lretq
57 +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
58 +[a-f0-9]+: 48 f7 14 24 notq \(%rsp\)
59 +[a-f0-9]+: 0f ae e8 lfence
60 +[a-f0-9]+: 48 ca 28 00 lretq \$0x28