gas/testsuite/gas/mips/mips16-pcrel-addend-n32-8.d

   1 #objdump: -dr --prefix-addresses --show-raw-insn
   2 #name: MIPS16 PC-relative relocation with addend 8 (n32)
   3 #as: -n32
   4 #source: mips16-pcrel-addend-8.s
   5
   6 .*: +file format .*mips.*
   7
   8 Disassembly of section \.text:
   9         \.\.\.
  10 [0-9a-f]+ <[^>]*> f000 6a00     li      v0,0
  11 [       ]*[0-9a-f]+: R_MIPS16_HI16      bar
  12 [0-9a-f]+ <[^>]*> f400 3240     sll     v0,16
  13 [0-9a-f]+ <[^>]*> f000 4a00     addiu   v0,0
  14 [       ]*[0-9a-f]+: R_MIPS16_LO16      bar
  15 [0-9a-f]+ <[^>]*> f000 6a00     li      v0,0
  16 [       ]*[0-9a-f]+: R_MIPS16_HI16      bar
  17 [0-9a-f]+ <[^>]*> f400 3240     sll     v0,16
  18 [0-9a-f]+ <[^>]*> f000 9a40     lw      v0,0\(v0\)
  19 [       ]*[0-9a-f]+: R_MIPS16_LO16      bar
  20 [0-9a-f]+ <[^>]*> f000 6a00     li      v0,0
  21 [       ]*[0-9a-f]+: R_MIPS16_HI16      bar\+0x2468
  22 [0-9a-f]+ <[^>]*> f400 3240     sll     v0,16
  23 [0-9a-f]+ <[^>]*> f000 4a00     addiu   v0,0
  24 [       ]*[0-9a-f]+: R_MIPS16_LO16      bar\+0x2468
  25 [0-9a-f]+ <[^>]*> f000 6a00     li      v0,0
  26 [       ]*[0-9a-f]+: R_MIPS16_HI16      bar\+0x2468
  27 [0-9a-f]+ <[^>]*> f400 3240     sll     v0,16
  28 [0-9a-f]+ <[^>]*> f000 9a40     lw      v0,0\(v0\)
  29 [       ]*[0-9a-f]+: R_MIPS16_LO16      bar\+0x2468
  30 [0-9a-f]+ <[^>]*> f000 6a00     li      v0,0
  31 [       ]*[0-9a-f]+: R_MIPS16_HI16      bar\+0x12345678
  32 [0-9a-f]+ <[^>]*> f400 3240     sll     v0,16
  33 [0-9a-f]+ <[^>]*> f000 4a00     addiu   v0,0
  34 [       ]*[0-9a-f]+: R_MIPS16_LO16      bar\+0x12345678
  35 [0-9a-f]+ <[^>]*> f000 6a00     li      v0,0
  36 [       ]*[0-9a-f]+: R_MIPS16_HI16      bar\+0x12345678
  37 [0-9a-f]+ <[^>]*> f400 3240     sll     v0,16
  38 [0-9a-f]+ <[^>]*> f000 9a40     lw      v0,0\(v0\)
  39 [       ]*[0-9a-f]+: R_MIPS16_LO16      bar\+0x12345678
  40 [0-9a-f]+ <[^>]*> f000 6a00     li      v0,0
  41 [       ]*[0-9a-f]+: R_MIPS16_HI16      bar\+0x2468ace0
  42 [0-9a-f]+ <[^>]*> f400 3240     sll     v0,16
  43 [0-9a-f]+ <[^>]*> f000 4a00     addiu   v0,0
  44 [       ]*[0-9a-f]+: R_MIPS16_LO16      bar\+0x2468ace0
  45 [0-9a-f]+ <[^>]*> f000 6a00     li      v0,0
  46 [       ]*[0-9a-f]+: R_MIPS16_HI16      bar\+0x2468ace0
  47 [0-9a-f]+ <[^>]*> f400 3240     sll     v0,16
  48 [0-9a-f]+ <[^>]*> f000 9a40     lw      v0,0\(v0\)
  49 [       ]*[0-9a-f]+: R_MIPS16_LO16      bar\+0x2468ace0
  50 [0-9a-f]+ <[^>]*> 6500          nop
  51         \.\.\.