gas/testsuite/gas/mips/mips32.s

   1 # source file to test assembly of mips32 instructions
   2
   3         .set noreorder
   4       .set noat
   5
   6       .text
   7 text_label:
   8
   9       # unprivileged CPU instructions
  10
  11       clo     $1, $2
  12       clz     $3, $4
  13         .ifndef r6
  14       madd    $5, $6
  15       maddu   $7, $8
  16       msub    $9, $10
  17       msubu   $11, $12
  18         .endif
  19       mul     $13, $14, $15
  20       pref    4, ($16)
  21         .ifndef r6
  22       pref    4, 2047($17)
  23       pref    4, -2048($18)
  24         .endif
  25       ssnop
  26
  27
  28       # privileged instructions
  29
  30       cache   5, ($1)
  31         .ifndef r6
  32       cache   5, 2047($2)
  33       cache   5, -2048($3)
  34       .set at
  35       cache   5, 32768($4)
  36       cache   5, -32769($5)
  37       cache   5, 32768
  38       cache   5, -32769
  39       .set noat
  40         .endif
  41       eret
  42       tlbp
  43       tlbr
  44       tlbwi
  45       tlbwr
  46       wait
  47       wait    0                       # disassembles without code
  48       wait    0x345
  49
  50       # For a while break for the mips32 ISA interpreted a single argument
  51       # as a 20-bit code, placing it in the opcode differently to
  52       # traditional ISAs.  This turned out to cause problems, so it has
  53       # been removed.  This test is to assure consistent interpretation.
  54       break
  55       break   0                       # disassembles without code
  56       break   0x345
  57       break   0x48,0x345              # this still specifies a 20-bit code
  58
  59       # Instructions in previous ISAs or CPUs which are now slightly
  60       # different.
  61       sdbbp
  62       sdbbp   0                       # disassembles without code
  63       sdbbp   0x345
  64
  65 # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
  66       .space  8