1 # source file to test assembly of mips32 instructions
9 # unprivileged CPU instructions
28 # privileged instructions
47 wait 0 # disassembles without code
50 # For a while break for the mips32 ISA interpreted a single argument
51 # as a 20-bit code, placing it in the opcode differently to
52 # traditional ISAs. This turned out to cause problems, so it has
53 # been removed. This test is to assure consistent interpretation.
55 break 0 # disassembles without code
57 break 0x48,0x345 # this still specifies a 20-bit code
59 # Instructions in previous ISAs or CPUs which are now slightly
62 sdbbp 0 # disassembles without code
65 # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...