31 # The c.lt.s instruction of R5900 has the same opcode as c.olt.s of MIPS I.
35 # The c.le.s instruction of R5900 has the same opcode as c.ole.s of MIPS I.
45 # The cvt.w.s instruction of the R5900 does the same as trunc.w.s in MIPS I.
46 # The cvt.w.s instruction of MIPS I doesn't exist in the R5900 CPU.
47 # For compatibilty the instruction trunc.w.s uses the opcode of cvt.w.s.
48 # cvt.w.s should not be used on R5900.
52 # 128 bit store instruction.
58 # 128 bit load instruction.
70 # Preformance counter registers
95 # Parallel instructions operating on 128 bit registers:
128 # NOP should be inserted in branch delay.
129 bne $3, $0, short_loop1