35 # test mips4 instructions.
42 bc1fl $fcc1,text_label
44 bc1tl $fcc2,text_label
49 madd.d $f0,$f2,$f4,$f6
50 madd.s $f0,$f2,$f4,$f6
63 msub.d $f0,$f2,$f4,$f6
64 msub.s $f0,$f2,$f4,$f6
65 nmadd.d $f0,$f2,$f4,$f6
66 nmadd.s $f0,$f2,$f4,$f6
67 nmsub.d $f0,$f2,$f4,$f6
68 nmsub.s $f0,$f2,$f4,$f6
70 # We don't test pref because currently the disassembler will
71 # disassemble it as lwc3. lwc3 is correct for mips1 to mips3,
72 # while pref is correct for mips4. Unfortunately, the
73 # disassembler does not know which architecture it is
85 # test mips5 instructions.
91 alnv.ps $f6, $f8, $f10, $3
93 c.eq.ps $fcc2, $f10, $f12
95 c.f.ps $fcc2, $f10, $f12
97 c.le.ps $fcc2, $f10, $f12
99 c.lt.ps $fcc2, $f10, $f12
101 c.nge.ps $fcc2, $f10, $f12
103 c.ngl.ps $fcc2, $f10, $f12
105 c.ngle.ps $fcc2, $f10, $f12
107 c.ngt.ps $fcc2, $f10, $f12
109 c.ole.ps $fcc2, $f10, $f12
111 c.olt.ps $fcc2, $f10, $f12
113 c.seq.ps $fcc2, $f10, $f12
115 c.sf.ps $fcc2, $f10, $f12
117 c.ueq.ps $fcc2, $f10, $f12
119 c.ule.ps $fcc2, $f10, $f12
121 c.ult.ps $fcc2, $f10, $f12
123 c.un.ps $fcc2, $f10, $f12
124 cvt.ps.s $f12, $f14, $f16
128 madd.ps $f20, $f22, $f24, $f26
130 movf.ps $f26, $f28, $fcc2
131 movn.ps $f26, $f28, $3
132 movt.ps $f28, $f30, $fcc4
133 movz.ps $f28, $f30, $5
134 msub.ps $f30, $f0, $f2, $f4
137 nmadd.ps $f6, $f8, $f10, $f12
138 nmsub.ps $f6, $f8, $f10, $f12
139 pll.ps $f10, $f12, $f14
140 plu.ps $f14, $f16, $f18
141 pul.ps $f16, $f18, $f20
142 puu.ps $f20, $f22, $f24
143 sub.ps $f22, $f24, $f26
146 c.eq.ps $fcc3, $f10, $f12 # warns
147 movf.ps $f26, $f28, $fcc3 # warns
149 # test assembly of mips32 instructions
153 # unprivileged CPU instructions
167 # unprivileged coprocessor instructions.
168 # these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
178 # XXX other BCzCond encodings not currently expressable
180 cop2 0x1234567 # disassembles as c2 ...
183 mfc2 $4, $5, 0 # disassembles without sel
186 mtc2 $7, $8, 0 # disassembles without sel
189 # privileged instructions
200 wait 0 # disassembles without code
203 # For a while break for the mips32 ISA interpreted a single argument
204 # as a 20-bit code, placing it in the opcode differently to
205 # traditional ISAs. This turned out to cause problems, so it has
206 # been removed. This test is to assure consistent interpretation.
208 break 0 # disassembles without code
210 break 0x48,0x345 # this still specifies a 20-bit code
212 # Instructions in previous ISAs or CPUs which are now slightly
215 sdbbp 0 # disassembles without code
218 # test assembly of mips32r2 instructions
222 # unprivileged CPU instructions
235 # Note, further testing of rdhwr is done in hwr-names-mips32r2.d
243 # This file checks that in fact HW rotate will
244 # be used for this arch, and checks assembly
245 # of the official MIPS mnemonics. (Note that disassembly
246 # uses the traditional "ror" and "rorv" mnemonics.)
247 # Additional rotate tests are done by rol-hw.d.
279 # FPU (cp1) instructions
281 # Even registers are supported w/ 32-bit FPU, odd
282 # registers supported only for 64-bit FPU.
283 # Only the 32-bit FPU instructions are tested here.
295 # test assembly of mips64 instructions
297 # unprivileged CPU instructions
302 # unprivileged coprocessor instructions.
303 # these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
306 dmfc2 $4, $5, 0 # disassembles without sel
309 dmtc2 $7, $8, 0 # disassembles without sel
319 # Include mflos to check for nop insertion.
341 /* Integer instructions. */
362 dror $4,$5,57 /* Should expand to dror32 $4,$5,25. */
366 /* Debug instructions. */
373 /* Coprocessor 0 instructions, minus standard ISA 3 ones.
374 That leaves just the performance monitoring registers. */
381 /* Multimedia instructions. */
384 /* Test each form of each vector opcode. */
388 .if 0 /* Which is right?? */
389 /* Test negative numbers in immediate-value slot. */
392 /* Test that it's recognized as an unsigned field. */
398 /* Test each form of each vector opcode. */
402 .if 0 /* Which is right?? */
403 /* Test negative numbers in immediate-value slot. */
406 /* Test that it's recognized as an unsigned field. */
430 /* ALNI, SHFL: Vector only. */
431 alni.ob $f0,$f2,$f4,5
432 shfl.mixh.ob $f0,$f2,$f4
433 shfl.mixl.ob $f0,$f2,$f4
434 shfl.pach.ob $f0,$f2,$f4
435 shfl.pacl.ob $f0,$f2,$f4
437 /* SLL,SRL: Scalar or immediate. */
438 sll.ob $f2,$f4,$f6[3]
440 srl.ob $f2,$f4,$f6[3]
443 /* RZU: Immediate, must be 0, 8, or 16. */
461 /* Prefetch instructions. */
462 # We don't test pref because currently the disassembler will
463 # disassemble it as lwc3. lwc3 is correct for mips1 to mips3,
464 # while pref is correct for mips4. Unfortunately, the
465 # disassembler does not know which architecture it is
471 /* Miscellaneous instructions. */
474 wait 0 # disassembles without code
492 # make objdump print ...