1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2020 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
28 #include "reggroups.h"
30 #include "arch-utils.h"
32 #include "frame-unwind.h"
33 #include "frame-base.h"
34 #include "trad-frame.h"
37 #include "dwarf2-frame.h"
39 #include "prologue-value.h"
40 #include "target-descriptions.h"
41 #include "user-regs.h"
43 #include "gdbsupport/selftest.h"
45 #include "aarch64-tdep.h"
46 #include "aarch64-ravenscar-thread.h"
49 #include "record-full.h"
50 #include "arch/aarch64-insn.h"
53 #include "opcode/aarch64.h"
56 #define submask(x) ((1L << ((x) + 1)) - 1)
57 #define bit(obj,st) (((obj) >> (st)) & 1)
58 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
60 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
62 #define HA_MAX_NUM_FLDS 4
64 /* All possible aarch64 target descriptors. */
65 struct target_desc
*tdesc_aarch64_list
[AARCH64_MAX_SVE_VQ
+ 1][2/*pauth*/];
67 /* The standard register names, and all the valid aliases for them. */
70 const char *const name
;
72 } aarch64_register_aliases
[] =
74 /* 64-bit register names. */
75 {"fp", AARCH64_FP_REGNUM
},
76 {"lr", AARCH64_LR_REGNUM
},
77 {"sp", AARCH64_SP_REGNUM
},
79 /* 32-bit register names. */
80 {"w0", AARCH64_X0_REGNUM
+ 0},
81 {"w1", AARCH64_X0_REGNUM
+ 1},
82 {"w2", AARCH64_X0_REGNUM
+ 2},
83 {"w3", AARCH64_X0_REGNUM
+ 3},
84 {"w4", AARCH64_X0_REGNUM
+ 4},
85 {"w5", AARCH64_X0_REGNUM
+ 5},
86 {"w6", AARCH64_X0_REGNUM
+ 6},
87 {"w7", AARCH64_X0_REGNUM
+ 7},
88 {"w8", AARCH64_X0_REGNUM
+ 8},
89 {"w9", AARCH64_X0_REGNUM
+ 9},
90 {"w10", AARCH64_X0_REGNUM
+ 10},
91 {"w11", AARCH64_X0_REGNUM
+ 11},
92 {"w12", AARCH64_X0_REGNUM
+ 12},
93 {"w13", AARCH64_X0_REGNUM
+ 13},
94 {"w14", AARCH64_X0_REGNUM
+ 14},
95 {"w15", AARCH64_X0_REGNUM
+ 15},
96 {"w16", AARCH64_X0_REGNUM
+ 16},
97 {"w17", AARCH64_X0_REGNUM
+ 17},
98 {"w18", AARCH64_X0_REGNUM
+ 18},
99 {"w19", AARCH64_X0_REGNUM
+ 19},
100 {"w20", AARCH64_X0_REGNUM
+ 20},
101 {"w21", AARCH64_X0_REGNUM
+ 21},
102 {"w22", AARCH64_X0_REGNUM
+ 22},
103 {"w23", AARCH64_X0_REGNUM
+ 23},
104 {"w24", AARCH64_X0_REGNUM
+ 24},
105 {"w25", AARCH64_X0_REGNUM
+ 25},
106 {"w26", AARCH64_X0_REGNUM
+ 26},
107 {"w27", AARCH64_X0_REGNUM
+ 27},
108 {"w28", AARCH64_X0_REGNUM
+ 28},
109 {"w29", AARCH64_X0_REGNUM
+ 29},
110 {"w30", AARCH64_X0_REGNUM
+ 30},
113 {"ip0", AARCH64_X0_REGNUM
+ 16},
114 {"ip1", AARCH64_X0_REGNUM
+ 17}
117 /* The required core 'R' registers. */
118 static const char *const aarch64_r_register_names
[] =
120 /* These registers must appear in consecutive RAW register number
121 order and they must begin with AARCH64_X0_REGNUM! */
122 "x0", "x1", "x2", "x3",
123 "x4", "x5", "x6", "x7",
124 "x8", "x9", "x10", "x11",
125 "x12", "x13", "x14", "x15",
126 "x16", "x17", "x18", "x19",
127 "x20", "x21", "x22", "x23",
128 "x24", "x25", "x26", "x27",
129 "x28", "x29", "x30", "sp",
133 /* The FP/SIMD 'V' registers. */
134 static const char *const aarch64_v_register_names
[] =
136 /* These registers must appear in consecutive RAW register number
137 order and they must begin with AARCH64_V0_REGNUM! */
138 "v0", "v1", "v2", "v3",
139 "v4", "v5", "v6", "v7",
140 "v8", "v9", "v10", "v11",
141 "v12", "v13", "v14", "v15",
142 "v16", "v17", "v18", "v19",
143 "v20", "v21", "v22", "v23",
144 "v24", "v25", "v26", "v27",
145 "v28", "v29", "v30", "v31",
150 /* The SVE 'Z' and 'P' registers. */
151 static const char *const aarch64_sve_register_names
[] =
153 /* These registers must appear in consecutive RAW register number
154 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
155 "z0", "z1", "z2", "z3",
156 "z4", "z5", "z6", "z7",
157 "z8", "z9", "z10", "z11",
158 "z12", "z13", "z14", "z15",
159 "z16", "z17", "z18", "z19",
160 "z20", "z21", "z22", "z23",
161 "z24", "z25", "z26", "z27",
162 "z28", "z29", "z30", "z31",
164 "p0", "p1", "p2", "p3",
165 "p4", "p5", "p6", "p7",
166 "p8", "p9", "p10", "p11",
167 "p12", "p13", "p14", "p15",
171 static const char *const aarch64_pauth_register_names
[] =
173 /* Authentication mask for data pointer. */
175 /* Authentication mask for code pointer. */
179 /* AArch64 prologue cache structure. */
180 struct aarch64_prologue_cache
182 /* The program counter at the start of the function. It is used to
183 identify this frame as a prologue frame. */
186 /* The program counter at the time this frame was created; i.e. where
187 this function was called from. It is used to identify this frame as a
191 /* The stack pointer at the time this frame was created; i.e. the
192 caller's stack pointer when this function was called. It is used
193 to identify this frame. */
196 /* Is the target available to read from? */
199 /* The frame base for this frame is just prev_sp - frame size.
200 FRAMESIZE is the distance from the frame pointer to the
201 initial stack pointer. */
204 /* The register used to hold the frame pointer for this frame. */
207 /* Saved register offsets. */
208 struct trad_frame_saved_reg
*saved_regs
;
212 show_aarch64_debug (struct ui_file
*file
, int from_tty
,
213 struct cmd_list_element
*c
, const char *value
)
215 fprintf_filtered (file
, _("AArch64 debugging is %s.\n"), value
);
220 /* Abstract instruction reader. */
222 class abstract_instruction_reader
225 /* Read in one instruction. */
226 virtual ULONGEST
read (CORE_ADDR memaddr
, int len
,
227 enum bfd_endian byte_order
) = 0;
230 /* Instruction reader from real target. */
232 class instruction_reader
: public abstract_instruction_reader
235 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
238 return read_code_unsigned_integer (memaddr
, len
, byte_order
);
244 /* If address signing is enabled, mask off the signature bits from the link
245 register, which is passed by value in ADDR, using the register values in
249 aarch64_frame_unmask_lr (struct gdbarch_tdep
*tdep
,
250 struct frame_info
*this_frame
, CORE_ADDR addr
)
252 if (tdep
->has_pauth ()
253 && frame_unwind_register_unsigned (this_frame
,
254 tdep
->pauth_ra_state_regnum
))
256 int cmask_num
= AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
);
257 CORE_ADDR cmask
= frame_unwind_register_unsigned (this_frame
, cmask_num
);
258 addr
= addr
& ~cmask
;
260 /* Record in the frame that the link register required unmasking. */
261 set_frame_previous_pc_masked (this_frame
);
267 /* Implement the "get_pc_address_flags" gdbarch method. */
270 aarch64_get_pc_address_flags (frame_info
*frame
, CORE_ADDR pc
)
272 if (pc
!= 0 && get_frame_pc_masked (frame
))
278 /* Analyze a prologue, looking for a recognizable stack frame
279 and frame pointer. Scan until we encounter a store that could
280 clobber the stack frame unexpectedly, or an unknown instruction. */
283 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
284 CORE_ADDR start
, CORE_ADDR limit
,
285 struct aarch64_prologue_cache
*cache
,
286 abstract_instruction_reader
& reader
)
288 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
290 /* Track X registers and D registers in prologue. */
291 pv_t regs
[AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
];
293 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
; i
++)
294 regs
[i
] = pv_register (i
, 0);
295 pv_area
stack (AARCH64_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
297 for (; start
< limit
; start
+= 4)
302 insn
= reader
.read (start
, 4, byte_order_for_code
);
304 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
307 if (inst
.opcode
->iclass
== addsub_imm
308 && (inst
.opcode
->op
== OP_ADD
309 || strcmp ("sub", inst
.opcode
->name
) == 0))
311 unsigned rd
= inst
.operands
[0].reg
.regno
;
312 unsigned rn
= inst
.operands
[1].reg
.regno
;
314 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 3);
315 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd_SP
);
316 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn_SP
);
317 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_AIMM
);
319 if (inst
.opcode
->op
== OP_ADD
)
321 regs
[rd
] = pv_add_constant (regs
[rn
],
322 inst
.operands
[2].imm
.value
);
326 regs
[rd
] = pv_add_constant (regs
[rn
],
327 -inst
.operands
[2].imm
.value
);
330 else if (inst
.opcode
->iclass
== pcreladdr
331 && inst
.operands
[1].type
== AARCH64_OPND_ADDR_ADRP
)
333 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
334 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
336 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
338 else if (inst
.opcode
->iclass
== branch_imm
)
340 /* Stop analysis on branch. */
343 else if (inst
.opcode
->iclass
== condbranch
)
345 /* Stop analysis on branch. */
348 else if (inst
.opcode
->iclass
== branch_reg
)
350 /* Stop analysis on branch. */
353 else if (inst
.opcode
->iclass
== compbranch
)
355 /* Stop analysis on branch. */
358 else if (inst
.opcode
->op
== OP_MOVZ
)
360 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
361 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
363 else if (inst
.opcode
->iclass
== log_shift
364 && strcmp (inst
.opcode
->name
, "orr") == 0)
366 unsigned rd
= inst
.operands
[0].reg
.regno
;
367 unsigned rn
= inst
.operands
[1].reg
.regno
;
368 unsigned rm
= inst
.operands
[2].reg
.regno
;
370 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
371 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn
);
372 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_Rm_SFT
);
374 if (inst
.operands
[2].shifter
.amount
== 0
375 && rn
== AARCH64_SP_REGNUM
)
381 debug_printf ("aarch64: prologue analysis gave up "
382 "addr=%s opcode=0x%x (orr x register)\n",
383 core_addr_to_string_nz (start
), insn
);
388 else if (inst
.opcode
->op
== OP_STUR
)
390 unsigned rt
= inst
.operands
[0].reg
.regno
;
391 unsigned rn
= inst
.operands
[1].addr
.base_regno
;
392 int size
= aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
);
394 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
395 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
);
396 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_ADDR_SIMM9
);
397 gdb_assert (!inst
.operands
[1].addr
.offset
.is_reg
);
400 (pv_add_constant (regs
[rn
], inst
.operands
[1].addr
.offset
.imm
),
403 else if ((inst
.opcode
->iclass
== ldstpair_off
404 || (inst
.opcode
->iclass
== ldstpair_indexed
405 && inst
.operands
[2].addr
.preind
))
406 && strcmp ("stp", inst
.opcode
->name
) == 0)
408 /* STP with addressing mode Pre-indexed and Base register. */
411 unsigned rn
= inst
.operands
[2].addr
.base_regno
;
412 int32_t imm
= inst
.operands
[2].addr
.offset
.imm
;
413 int size
= aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
);
415 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
416 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
417 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rt2
418 || inst
.operands
[1].type
== AARCH64_OPND_Ft2
);
419 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_ADDR_SIMM7
);
420 gdb_assert (!inst
.operands
[2].addr
.offset
.is_reg
);
422 /* If recording this store would invalidate the store area
423 (perhaps because rn is not known) then we should abandon
424 further prologue analysis. */
425 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
)))
428 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
+ 8)))
431 rt1
= inst
.operands
[0].reg
.regno
;
432 rt2
= inst
.operands
[1].reg
.regno
;
433 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
435 rt1
+= AARCH64_X_REGISTER_COUNT
;
436 rt2
+= AARCH64_X_REGISTER_COUNT
;
439 stack
.store (pv_add_constant (regs
[rn
], imm
), size
, regs
[rt1
]);
440 stack
.store (pv_add_constant (regs
[rn
], imm
+ size
), size
, regs
[rt2
]);
442 if (inst
.operands
[2].addr
.writeback
)
443 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
446 else if ((inst
.opcode
->iclass
== ldst_imm9
/* Signed immediate. */
447 || (inst
.opcode
->iclass
== ldst_pos
/* Unsigned immediate. */
448 && (inst
.opcode
->op
== OP_STR_POS
449 || inst
.opcode
->op
== OP_STRF_POS
)))
450 && inst
.operands
[1].addr
.base_regno
== AARCH64_SP_REGNUM
451 && strcmp ("str", inst
.opcode
->name
) == 0)
453 /* STR (immediate) */
454 unsigned int rt
= inst
.operands
[0].reg
.regno
;
455 int32_t imm
= inst
.operands
[1].addr
.offset
.imm
;
456 unsigned int rn
= inst
.operands
[1].addr
.base_regno
;
457 int size
= aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
);
458 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
459 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
461 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
462 rt
+= AARCH64_X_REGISTER_COUNT
;
464 stack
.store (pv_add_constant (regs
[rn
], imm
), size
, regs
[rt
]);
465 if (inst
.operands
[1].addr
.writeback
)
466 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
468 else if (inst
.opcode
->iclass
== testbranch
)
470 /* Stop analysis on branch. */
473 else if (inst
.opcode
->iclass
== ic_system
)
475 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
476 int ra_state_val
= 0;
478 if (insn
== 0xd503233f /* paciasp. */
479 || insn
== 0xd503237f /* pacibsp. */)
481 /* Return addresses are mangled. */
484 else if (insn
== 0xd50323bf /* autiasp. */
485 || insn
== 0xd50323ff /* autibsp. */)
487 /* Return addresses are not mangled. */
493 debug_printf ("aarch64: prologue analysis gave up addr=%s"
494 " opcode=0x%x (iclass)\n",
495 core_addr_to_string_nz (start
), insn
);
499 if (tdep
->has_pauth () && cache
!= nullptr)
500 trad_frame_set_value (cache
->saved_regs
,
501 tdep
->pauth_ra_state_regnum
,
508 debug_printf ("aarch64: prologue analysis gave up addr=%s"
510 core_addr_to_string_nz (start
), insn
);
519 if (pv_is_register (regs
[AARCH64_FP_REGNUM
], AARCH64_SP_REGNUM
))
521 /* Frame pointer is fp. Frame size is constant. */
522 cache
->framereg
= AARCH64_FP_REGNUM
;
523 cache
->framesize
= -regs
[AARCH64_FP_REGNUM
].k
;
525 else if (pv_is_register (regs
[AARCH64_SP_REGNUM
], AARCH64_SP_REGNUM
))
527 /* Try the stack pointer. */
528 cache
->framesize
= -regs
[AARCH64_SP_REGNUM
].k
;
529 cache
->framereg
= AARCH64_SP_REGNUM
;
533 /* We're just out of luck. We don't know where the frame is. */
534 cache
->framereg
= -1;
535 cache
->framesize
= 0;
538 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
542 if (stack
.find_reg (gdbarch
, i
, &offset
))
543 cache
->saved_regs
[i
].addr
= offset
;
546 for (i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
548 int regnum
= gdbarch_num_regs (gdbarch
);
551 if (stack
.find_reg (gdbarch
, i
+ AARCH64_X_REGISTER_COUNT
,
553 cache
->saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
= offset
;
560 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
561 CORE_ADDR start
, CORE_ADDR limit
,
562 struct aarch64_prologue_cache
*cache
)
564 instruction_reader reader
;
566 return aarch64_analyze_prologue (gdbarch
, start
, limit
, cache
,
572 namespace selftests
{
574 /* Instruction reader from manually cooked instruction sequences. */
576 class instruction_reader_test
: public abstract_instruction_reader
579 template<size_t SIZE
>
580 explicit instruction_reader_test (const uint32_t (&insns
)[SIZE
])
581 : m_insns (insns
), m_insns_size (SIZE
)
584 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
587 SELF_CHECK (len
== 4);
588 SELF_CHECK (memaddr
% 4 == 0);
589 SELF_CHECK (memaddr
/ 4 < m_insns_size
);
591 return m_insns
[memaddr
/ 4];
595 const uint32_t *m_insns
;
600 aarch64_analyze_prologue_test (void)
602 struct gdbarch_info info
;
604 gdbarch_info_init (&info
);
605 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
607 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
608 SELF_CHECK (gdbarch
!= NULL
);
610 struct aarch64_prologue_cache cache
;
611 cache
.saved_regs
= trad_frame_alloc_saved_regs (gdbarch
);
613 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
615 /* Test the simple prologue in which frame pointer is used. */
617 static const uint32_t insns
[] = {
618 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
619 0x910003fd, /* mov x29, sp */
620 0x97ffffe6, /* bl 0x400580 */
622 instruction_reader_test
reader (insns
);
624 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
625 SELF_CHECK (end
== 4 * 2);
627 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
628 SELF_CHECK (cache
.framesize
== 272);
630 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
632 if (i
== AARCH64_FP_REGNUM
)
633 SELF_CHECK (cache
.saved_regs
[i
].addr
== -272);
634 else if (i
== AARCH64_LR_REGNUM
)
635 SELF_CHECK (cache
.saved_regs
[i
].addr
== -264);
637 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
640 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
642 int regnum
= gdbarch_num_regs (gdbarch
);
644 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
649 /* Test a prologue in which STR is used and frame pointer is not
652 static const uint32_t insns
[] = {
653 0xf81d0ff3, /* str x19, [sp, #-48]! */
654 0xb9002fe0, /* str w0, [sp, #44] */
655 0xf90013e1, /* str x1, [sp, #32]*/
656 0xfd000fe0, /* str d0, [sp, #24] */
657 0xaa0203f3, /* mov x19, x2 */
658 0xf94013e0, /* ldr x0, [sp, #32] */
660 instruction_reader_test
reader (insns
);
662 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
663 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
665 SELF_CHECK (end
== 4 * 5);
667 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
668 SELF_CHECK (cache
.framesize
== 48);
670 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
673 SELF_CHECK (cache
.saved_regs
[i
].addr
== -16);
675 SELF_CHECK (cache
.saved_regs
[i
].addr
== -48);
677 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
680 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
682 int regnum
= gdbarch_num_regs (gdbarch
);
685 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
688 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
693 /* Test a prologue in which there is a return address signing instruction. */
694 if (tdep
->has_pauth ())
696 static const uint32_t insns
[] = {
697 0xd503233f, /* paciasp */
698 0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */
699 0x910003fd, /* mov x29, sp */
700 0xf801c3f3, /* str x19, [sp, #28] */
701 0xb9401fa0, /* ldr x19, [x29, #28] */
703 instruction_reader_test
reader (insns
);
705 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
706 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
,
709 SELF_CHECK (end
== 4 * 4);
710 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
711 SELF_CHECK (cache
.framesize
== 48);
713 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
716 SELF_CHECK (cache
.saved_regs
[i
].addr
== -20);
717 else if (i
== AARCH64_FP_REGNUM
)
718 SELF_CHECK (cache
.saved_regs
[i
].addr
== -48);
719 else if (i
== AARCH64_LR_REGNUM
)
720 SELF_CHECK (cache
.saved_regs
[i
].addr
== -40);
722 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
725 if (tdep
->has_pauth ())
727 SELF_CHECK (trad_frame_value_p (cache
.saved_regs
,
728 tdep
->pauth_ra_state_regnum
));
729 SELF_CHECK (cache
.saved_regs
[tdep
->pauth_ra_state_regnum
].addr
== 1);
733 } // namespace selftests
734 #endif /* GDB_SELF_TEST */
736 /* Implement the "skip_prologue" gdbarch method. */
739 aarch64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
741 CORE_ADDR func_addr
, limit_pc
;
743 /* See if we can determine the end of the prologue via the symbol
744 table. If so, then return either PC, or the PC after the
745 prologue, whichever is greater. */
746 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
748 CORE_ADDR post_prologue_pc
749 = skip_prologue_using_sal (gdbarch
, func_addr
);
751 if (post_prologue_pc
!= 0)
752 return std::max (pc
, post_prologue_pc
);
755 /* Can't determine prologue from the symbol table, need to examine
758 /* Find an upper limit on the function prologue using the debug
759 information. If the debug information could not be used to
760 provide that bound, then use an arbitrary large number as the
762 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
764 limit_pc
= pc
+ 128; /* Magic. */
766 /* Try disassembling prologue. */
767 return aarch64_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
770 /* Scan the function prologue for THIS_FRAME and populate the prologue
774 aarch64_scan_prologue (struct frame_info
*this_frame
,
775 struct aarch64_prologue_cache
*cache
)
777 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
778 CORE_ADDR prologue_start
;
779 CORE_ADDR prologue_end
;
780 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
781 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
783 cache
->prev_pc
= prev_pc
;
785 /* Assume we do not find a frame. */
786 cache
->framereg
= -1;
787 cache
->framesize
= 0;
789 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
792 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
796 /* No line info so use the current PC. */
797 prologue_end
= prev_pc
;
799 else if (sal
.end
< prologue_end
)
801 /* The next line begins after the function end. */
802 prologue_end
= sal
.end
;
805 prologue_end
= std::min (prologue_end
, prev_pc
);
806 aarch64_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
812 frame_loc
= get_frame_register_unsigned (this_frame
, AARCH64_FP_REGNUM
);
816 cache
->framereg
= AARCH64_FP_REGNUM
;
817 cache
->framesize
= 16;
818 cache
->saved_regs
[29].addr
= 0;
819 cache
->saved_regs
[30].addr
= 8;
823 /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
824 function may throw an exception if the inferior's registers or memory is
828 aarch64_make_prologue_cache_1 (struct frame_info
*this_frame
,
829 struct aarch64_prologue_cache
*cache
)
831 CORE_ADDR unwound_fp
;
834 aarch64_scan_prologue (this_frame
, cache
);
836 if (cache
->framereg
== -1)
839 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
843 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
845 /* Calculate actual addresses of saved registers using offsets
846 determined by aarch64_analyze_prologue. */
847 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
848 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
849 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
851 cache
->func
= get_frame_func (this_frame
);
853 cache
->available_p
= 1;
856 /* Allocate and fill in *THIS_CACHE with information about the prologue of
857 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
858 Return a pointer to the current aarch64_prologue_cache in
861 static struct aarch64_prologue_cache
*
862 aarch64_make_prologue_cache (struct frame_info
*this_frame
, void **this_cache
)
864 struct aarch64_prologue_cache
*cache
;
866 if (*this_cache
!= NULL
)
867 return (struct aarch64_prologue_cache
*) *this_cache
;
869 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
870 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
875 aarch64_make_prologue_cache_1 (this_frame
, cache
);
877 catch (const gdb_exception_error
&ex
)
879 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
886 /* Implement the "stop_reason" frame_unwind method. */
888 static enum unwind_stop_reason
889 aarch64_prologue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
892 struct aarch64_prologue_cache
*cache
893 = aarch64_make_prologue_cache (this_frame
, this_cache
);
895 if (!cache
->available_p
)
896 return UNWIND_UNAVAILABLE
;
898 /* Halt the backtrace at "_start". */
899 if (cache
->prev_pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
900 return UNWIND_OUTERMOST
;
902 /* We've hit a wall, stop. */
903 if (cache
->prev_sp
== 0)
904 return UNWIND_OUTERMOST
;
906 return UNWIND_NO_REASON
;
909 /* Our frame ID for a normal frame is the current function's starting
910 PC and the caller's SP when we were called. */
913 aarch64_prologue_this_id (struct frame_info
*this_frame
,
914 void **this_cache
, struct frame_id
*this_id
)
916 struct aarch64_prologue_cache
*cache
917 = aarch64_make_prologue_cache (this_frame
, this_cache
);
919 if (!cache
->available_p
)
920 *this_id
= frame_id_build_unavailable_stack (cache
->func
);
922 *this_id
= frame_id_build (cache
->prev_sp
, cache
->func
);
925 /* Implement the "prev_register" frame_unwind method. */
927 static struct value
*
928 aarch64_prologue_prev_register (struct frame_info
*this_frame
,
929 void **this_cache
, int prev_regnum
)
931 struct aarch64_prologue_cache
*cache
932 = aarch64_make_prologue_cache (this_frame
, this_cache
);
934 /* If we are asked to unwind the PC, then we need to return the LR
935 instead. The prologue may save PC, but it will point into this
936 frame's prologue, not the next frame's resume location. */
937 if (prev_regnum
== AARCH64_PC_REGNUM
)
940 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
941 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
943 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
945 if (tdep
->has_pauth ()
946 && trad_frame_value_p (cache
->saved_regs
,
947 tdep
->pauth_ra_state_regnum
))
948 lr
= aarch64_frame_unmask_lr (tdep
, this_frame
, lr
);
950 return frame_unwind_got_constant (this_frame
, prev_regnum
, lr
);
953 /* SP is generally not saved to the stack, but this frame is
954 identified by the next frame's stack pointer at the time of the
955 call. The value was already reconstructed into PREV_SP. */
968 if (prev_regnum
== AARCH64_SP_REGNUM
)
969 return frame_unwind_got_constant (this_frame
, prev_regnum
,
972 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
976 /* AArch64 prologue unwinder. */
977 struct frame_unwind aarch64_prologue_unwind
=
980 aarch64_prologue_frame_unwind_stop_reason
,
981 aarch64_prologue_this_id
,
982 aarch64_prologue_prev_register
,
984 default_frame_sniffer
987 /* Allocate and fill in *THIS_CACHE with information about the prologue of
988 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
989 Return a pointer to the current aarch64_prologue_cache in
992 static struct aarch64_prologue_cache
*
993 aarch64_make_stub_cache (struct frame_info
*this_frame
, void **this_cache
)
995 struct aarch64_prologue_cache
*cache
;
997 if (*this_cache
!= NULL
)
998 return (struct aarch64_prologue_cache
*) *this_cache
;
1000 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
1001 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1002 *this_cache
= cache
;
1006 cache
->prev_sp
= get_frame_register_unsigned (this_frame
,
1008 cache
->prev_pc
= get_frame_pc (this_frame
);
1009 cache
->available_p
= 1;
1011 catch (const gdb_exception_error
&ex
)
1013 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
1020 /* Implement the "stop_reason" frame_unwind method. */
1022 static enum unwind_stop_reason
1023 aarch64_stub_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1026 struct aarch64_prologue_cache
*cache
1027 = aarch64_make_stub_cache (this_frame
, this_cache
);
1029 if (!cache
->available_p
)
1030 return UNWIND_UNAVAILABLE
;
1032 return UNWIND_NO_REASON
;
1035 /* Our frame ID for a stub frame is the current SP and LR. */
1038 aarch64_stub_this_id (struct frame_info
*this_frame
,
1039 void **this_cache
, struct frame_id
*this_id
)
1041 struct aarch64_prologue_cache
*cache
1042 = aarch64_make_stub_cache (this_frame
, this_cache
);
1044 if (cache
->available_p
)
1045 *this_id
= frame_id_build (cache
->prev_sp
, cache
->prev_pc
);
1047 *this_id
= frame_id_build_unavailable_stack (cache
->prev_pc
);
1050 /* Implement the "sniffer" frame_unwind method. */
1053 aarch64_stub_unwind_sniffer (const struct frame_unwind
*self
,
1054 struct frame_info
*this_frame
,
1055 void **this_prologue_cache
)
1057 CORE_ADDR addr_in_block
;
1060 addr_in_block
= get_frame_address_in_block (this_frame
);
1061 if (in_plt_section (addr_in_block
)
1062 /* We also use the stub winder if the target memory is unreadable
1063 to avoid having the prologue unwinder trying to read it. */
1064 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1070 /* AArch64 stub unwinder. */
1071 struct frame_unwind aarch64_stub_unwind
=
1074 aarch64_stub_frame_unwind_stop_reason
,
1075 aarch64_stub_this_id
,
1076 aarch64_prologue_prev_register
,
1078 aarch64_stub_unwind_sniffer
1081 /* Return the frame base address of *THIS_FRAME. */
1084 aarch64_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1086 struct aarch64_prologue_cache
*cache
1087 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1089 return cache
->prev_sp
- cache
->framesize
;
1092 /* AArch64 default frame base information. */
1093 struct frame_base aarch64_normal_base
=
1095 &aarch64_prologue_unwind
,
1096 aarch64_normal_frame_base
,
1097 aarch64_normal_frame_base
,
1098 aarch64_normal_frame_base
1101 /* Return the value of the REGNUM register in the previous frame of
1104 static struct value
*
1105 aarch64_dwarf2_prev_register (struct frame_info
*this_frame
,
1106 void **this_cache
, int regnum
)
1108 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1113 case AARCH64_PC_REGNUM
:
1114 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
1115 lr
= aarch64_frame_unmask_lr (tdep
, this_frame
, lr
);
1116 return frame_unwind_got_constant (this_frame
, regnum
, lr
);
1119 internal_error (__FILE__
, __LINE__
,
1120 _("Unexpected register %d"), regnum
);
1124 static const unsigned char op_lit0
= DW_OP_lit0
;
1125 static const unsigned char op_lit1
= DW_OP_lit1
;
1127 /* Implement the "init_reg" dwarf2_frame_ops method. */
1130 aarch64_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1131 struct dwarf2_frame_state_reg
*reg
,
1132 struct frame_info
*this_frame
)
1134 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1138 case AARCH64_PC_REGNUM
:
1139 reg
->how
= DWARF2_FRAME_REG_FN
;
1140 reg
->loc
.fn
= aarch64_dwarf2_prev_register
;
1143 case AARCH64_SP_REGNUM
:
1144 reg
->how
= DWARF2_FRAME_REG_CFA
;
1148 /* Init pauth registers. */
1149 if (tdep
->has_pauth ())
1151 if (regnum
== tdep
->pauth_ra_state_regnum
)
1153 /* Initialize RA_STATE to zero. */
1154 reg
->how
= DWARF2_FRAME_REG_SAVED_VAL_EXP
;
1155 reg
->loc
.exp
.start
= &op_lit0
;
1156 reg
->loc
.exp
.len
= 1;
1159 else if (regnum
== AARCH64_PAUTH_DMASK_REGNUM (tdep
->pauth_reg_base
)
1160 || regnum
== AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
))
1162 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1168 /* Implement the execute_dwarf_cfa_vendor_op method. */
1171 aarch64_execute_dwarf_cfa_vendor_op (struct gdbarch
*gdbarch
, gdb_byte op
,
1172 struct dwarf2_frame_state
*fs
)
1174 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1175 struct dwarf2_frame_state_reg
*ra_state
;
1177 if (op
== DW_CFA_AARCH64_negate_ra_state
)
1179 /* On systems without pauth, treat as a nop. */
1180 if (!tdep
->has_pauth ())
1183 /* Allocate RA_STATE column if it's not allocated yet. */
1184 fs
->regs
.alloc_regs (AARCH64_DWARF_PAUTH_RA_STATE
+ 1);
1186 /* Toggle the status of RA_STATE between 0 and 1. */
1187 ra_state
= &(fs
->regs
.reg
[AARCH64_DWARF_PAUTH_RA_STATE
]);
1188 ra_state
->how
= DWARF2_FRAME_REG_SAVED_VAL_EXP
;
1190 if (ra_state
->loc
.exp
.start
== nullptr
1191 || ra_state
->loc
.exp
.start
== &op_lit0
)
1192 ra_state
->loc
.exp
.start
= &op_lit1
;
1194 ra_state
->loc
.exp
.start
= &op_lit0
;
1196 ra_state
->loc
.exp
.len
= 1;
1204 /* When arguments must be pushed onto the stack, they go on in reverse
1205 order. The code below implements a FILO (stack) to do this. */
1209 /* Value to pass on stack. It can be NULL if this item is for stack
1211 const gdb_byte
*data
;
1213 /* Size in bytes of value to pass on stack. */
1217 /* Implement the gdbarch type alignment method, overrides the generic
1218 alignment algorithm for anything that is aarch64 specific. */
1221 aarch64_type_align (gdbarch
*gdbarch
, struct type
*t
)
1223 t
= check_typedef (t
);
1224 if (TYPE_CODE (t
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (t
))
1226 /* Use the natural alignment for vector types (the same for
1227 scalar type), but the maximum alignment is 128-bit. */
1228 if (TYPE_LENGTH (t
) > 16)
1231 return TYPE_LENGTH (t
);
1234 /* Allow the common code to calculate the alignment. */
1238 /* Worker function for aapcs_is_vfp_call_or_return_candidate.
1240 Return the number of register required, or -1 on failure.
1242 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1243 to the element, else fail if the type of this element does not match the
1247 aapcs_is_vfp_call_or_return_candidate_1 (struct type
*type
,
1248 struct type
**fundamental_type
)
1250 if (type
== nullptr)
1253 switch (TYPE_CODE (type
))
1256 if (TYPE_LENGTH (type
) > 16)
1259 if (*fundamental_type
== nullptr)
1260 *fundamental_type
= type
;
1261 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1262 || TYPE_CODE (type
) != TYPE_CODE (*fundamental_type
))
1267 case TYPE_CODE_COMPLEX
:
1269 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (type
));
1270 if (TYPE_LENGTH (target_type
) > 16)
1273 if (*fundamental_type
== nullptr)
1274 *fundamental_type
= target_type
;
1275 else if (TYPE_LENGTH (target_type
) != TYPE_LENGTH (*fundamental_type
)
1276 || TYPE_CODE (target_type
) != TYPE_CODE (*fundamental_type
))
1282 case TYPE_CODE_ARRAY
:
1284 if (TYPE_VECTOR (type
))
1286 if (TYPE_LENGTH (type
) != 8 && TYPE_LENGTH (type
) != 16)
1289 if (*fundamental_type
== nullptr)
1290 *fundamental_type
= type
;
1291 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1292 || TYPE_CODE (type
) != TYPE_CODE (*fundamental_type
))
1299 struct type
*target_type
= TYPE_TARGET_TYPE (type
);
1300 int count
= aapcs_is_vfp_call_or_return_candidate_1
1301 (target_type
, fundamental_type
);
1306 count
*= (TYPE_LENGTH (type
) / TYPE_LENGTH (target_type
));
1311 case TYPE_CODE_STRUCT
:
1312 case TYPE_CODE_UNION
:
1316 for (int i
= 0; i
< TYPE_NFIELDS (type
); i
++)
1318 /* Ignore any static fields. */
1319 if (field_is_static (&TYPE_FIELD (type
, i
)))
1322 struct type
*member
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
1324 int sub_count
= aapcs_is_vfp_call_or_return_candidate_1
1325 (member
, fundamental_type
);
1326 if (sub_count
== -1)
1331 /* Ensure there is no padding between the fields (allowing for empty
1332 zero length structs) */
1333 int ftype_length
= (*fundamental_type
== nullptr)
1334 ? 0 : TYPE_LENGTH (*fundamental_type
);
1335 if (count
* ftype_length
!= TYPE_LENGTH (type
))
1348 /* Return true if an argument, whose type is described by TYPE, can be passed or
1349 returned in simd/fp registers, providing enough parameter passing registers
1350 are available. This is as described in the AAPCS64.
1352 Upon successful return, *COUNT returns the number of needed registers,
1353 *FUNDAMENTAL_TYPE contains the type of those registers.
1355 Candidate as per the AAPCS64 5.4.2.C is either a:
1358 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1359 all the members are floats and has at most 4 members.
1360 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1361 all the members are short vectors and has at most 4 members.
1364 Note that HFAs and HVAs can include nested structures and arrays. */
1367 aapcs_is_vfp_call_or_return_candidate (struct type
*type
, int *count
,
1368 struct type
**fundamental_type
)
1370 if (type
== nullptr)
1373 *fundamental_type
= nullptr;
1375 int ag_count
= aapcs_is_vfp_call_or_return_candidate_1 (type
,
1378 if (ag_count
> 0 && ag_count
<= HA_MAX_NUM_FLDS
)
1387 /* AArch64 function call information structure. */
1388 struct aarch64_call_info
1390 /* the current argument number. */
1391 unsigned argnum
= 0;
1393 /* The next general purpose register number, equivalent to NGRN as
1394 described in the AArch64 Procedure Call Standard. */
1397 /* The next SIMD and floating point register number, equivalent to
1398 NSRN as described in the AArch64 Procedure Call Standard. */
1401 /* The next stacked argument address, equivalent to NSAA as
1402 described in the AArch64 Procedure Call Standard. */
1405 /* Stack item vector. */
1406 std::vector
<stack_item_t
> si
;
1409 /* Pass a value in a sequence of consecutive X registers. The caller
1410 is responsible for ensuring sufficient registers are available. */
1413 pass_in_x (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1414 struct aarch64_call_info
*info
, struct type
*type
,
1417 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1418 int len
= TYPE_LENGTH (type
);
1419 enum type_code typecode
= TYPE_CODE (type
);
1420 int regnum
= AARCH64_X0_REGNUM
+ info
->ngrn
;
1421 const bfd_byte
*buf
= value_contents (arg
);
1427 int partial_len
= len
< X_REGISTER_SIZE
? len
: X_REGISTER_SIZE
;
1428 CORE_ADDR regval
= extract_unsigned_integer (buf
, partial_len
,
1432 /* Adjust sub-word struct/union args when big-endian. */
1433 if (byte_order
== BFD_ENDIAN_BIG
1434 && partial_len
< X_REGISTER_SIZE
1435 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1436 regval
<<= ((X_REGISTER_SIZE
- partial_len
) * TARGET_CHAR_BIT
);
1440 debug_printf ("arg %d in %s = 0x%s\n", info
->argnum
,
1441 gdbarch_register_name (gdbarch
, regnum
),
1442 phex (regval
, X_REGISTER_SIZE
));
1444 regcache_cooked_write_unsigned (regcache
, regnum
, regval
);
1451 /* Attempt to marshall a value in a V register. Return 1 if
1452 successful, or 0 if insufficient registers are available. This
1453 function, unlike the equivalent pass_in_x() function does not
1454 handle arguments spread across multiple registers. */
1457 pass_in_v (struct gdbarch
*gdbarch
,
1458 struct regcache
*regcache
,
1459 struct aarch64_call_info
*info
,
1460 int len
, const bfd_byte
*buf
)
1464 int regnum
= AARCH64_V0_REGNUM
+ info
->nsrn
;
1465 /* Enough space for a full vector register. */
1466 gdb_byte reg
[register_size (gdbarch
, regnum
)];
1467 gdb_assert (len
<= sizeof (reg
));
1472 memset (reg
, 0, sizeof (reg
));
1473 /* PCS C.1, the argument is allocated to the least significant
1474 bits of V register. */
1475 memcpy (reg
, buf
, len
);
1476 regcache
->cooked_write (regnum
, reg
);
1480 debug_printf ("arg %d in %s\n", info
->argnum
,
1481 gdbarch_register_name (gdbarch
, regnum
));
1489 /* Marshall an argument onto the stack. */
1492 pass_on_stack (struct aarch64_call_info
*info
, struct type
*type
,
1495 const bfd_byte
*buf
= value_contents (arg
);
1496 int len
= TYPE_LENGTH (type
);
1502 align
= type_align (type
);
1504 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1505 Natural alignment of the argument's type. */
1506 align
= align_up (align
, 8);
1508 /* The AArch64 PCS requires at most doubleword alignment. */
1514 debug_printf ("arg %d len=%d @ sp + %d\n", info
->argnum
, len
,
1520 info
->si
.push_back (item
);
1523 if (info
->nsaa
& (align
- 1))
1525 /* Push stack alignment padding. */
1526 int pad
= align
- (info
->nsaa
& (align
- 1));
1531 info
->si
.push_back (item
);
1536 /* Marshall an argument into a sequence of one or more consecutive X
1537 registers or, if insufficient X registers are available then onto
1541 pass_in_x_or_stack (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1542 struct aarch64_call_info
*info
, struct type
*type
,
1545 int len
= TYPE_LENGTH (type
);
1546 int nregs
= (len
+ X_REGISTER_SIZE
- 1) / X_REGISTER_SIZE
;
1548 /* PCS C.13 - Pass in registers if we have enough spare */
1549 if (info
->ngrn
+ nregs
<= 8)
1551 pass_in_x (gdbarch
, regcache
, info
, type
, arg
);
1552 info
->ngrn
+= nregs
;
1557 pass_on_stack (info
, type
, arg
);
1561 /* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1562 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1563 registers. A return value of false is an error state as the value will have
1564 been partially passed to the stack. */
1566 pass_in_v_vfp_candidate (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1567 struct aarch64_call_info
*info
, struct type
*arg_type
,
1570 switch (TYPE_CODE (arg_type
))
1573 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1574 value_contents (arg
));
1577 case TYPE_CODE_COMPLEX
:
1579 const bfd_byte
*buf
= value_contents (arg
);
1580 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (arg_type
));
1582 if (!pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1586 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1587 buf
+ TYPE_LENGTH (target_type
));
1590 case TYPE_CODE_ARRAY
:
1591 if (TYPE_VECTOR (arg_type
))
1592 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1593 value_contents (arg
));
1596 case TYPE_CODE_STRUCT
:
1597 case TYPE_CODE_UNION
:
1598 for (int i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
1600 /* Don't include static fields. */
1601 if (field_is_static (&TYPE_FIELD (arg_type
, i
)))
1604 struct value
*field
= value_primitive_field (arg
, 0, i
, arg_type
);
1605 struct type
*field_type
= check_typedef (value_type (field
));
1607 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, info
, field_type
,
1618 /* Implement the "push_dummy_call" gdbarch method. */
1621 aarch64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1622 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1624 struct value
**args
, CORE_ADDR sp
,
1625 function_call_return_method return_method
,
1626 CORE_ADDR struct_addr
)
1629 struct aarch64_call_info info
;
1631 /* We need to know what the type of the called function is in order
1632 to determine the number of named/anonymous arguments for the
1633 actual argument placement, and the return type in order to handle
1634 return value correctly.
1636 The generic code above us views the decision of return in memory
1637 or return in registers as a two stage processes. The language
1638 handler is consulted first and may decide to return in memory (eg
1639 class with copy constructor returned by value), this will cause
1640 the generic code to allocate space AND insert an initial leading
1643 If the language code does not decide to pass in memory then the
1644 target code is consulted.
1646 If the language code decides to pass in memory we want to move
1647 the pointer inserted as the initial argument from the argument
1648 list and into X8, the conventional AArch64 struct return pointer
1651 /* Set the return address. For the AArch64, the return breakpoint
1652 is always at BP_ADDR. */
1653 regcache_cooked_write_unsigned (regcache
, AARCH64_LR_REGNUM
, bp_addr
);
1655 /* If we were given an initial argument for the return slot, lose it. */
1656 if (return_method
== return_method_hidden_param
)
1662 /* The struct_return pointer occupies X8. */
1663 if (return_method
!= return_method_normal
)
1667 debug_printf ("struct return in %s = 0x%s\n",
1668 gdbarch_register_name (gdbarch
,
1669 AARCH64_STRUCT_RETURN_REGNUM
),
1670 paddress (gdbarch
, struct_addr
));
1672 regcache_cooked_write_unsigned (regcache
, AARCH64_STRUCT_RETURN_REGNUM
,
1676 for (argnum
= 0; argnum
< nargs
; argnum
++)
1678 struct value
*arg
= args
[argnum
];
1679 struct type
*arg_type
, *fundamental_type
;
1682 arg_type
= check_typedef (value_type (arg
));
1683 len
= TYPE_LENGTH (arg_type
);
1685 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1686 if there are enough spare registers. */
1687 if (aapcs_is_vfp_call_or_return_candidate (arg_type
, &elements
,
1690 if (info
.nsrn
+ elements
<= 8)
1692 /* We know that we have sufficient registers available therefore
1693 this will never need to fallback to the stack. */
1694 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, &info
, arg_type
,
1696 gdb_assert_not_reached ("Failed to push args");
1701 pass_on_stack (&info
, arg_type
, arg
);
1706 switch (TYPE_CODE (arg_type
))
1709 case TYPE_CODE_BOOL
:
1710 case TYPE_CODE_CHAR
:
1711 case TYPE_CODE_RANGE
:
1712 case TYPE_CODE_ENUM
:
1715 /* Promote to 32 bit integer. */
1716 if (TYPE_UNSIGNED (arg_type
))
1717 arg_type
= builtin_type (gdbarch
)->builtin_uint32
;
1719 arg_type
= builtin_type (gdbarch
)->builtin_int32
;
1720 arg
= value_cast (arg_type
, arg
);
1722 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1725 case TYPE_CODE_STRUCT
:
1726 case TYPE_CODE_ARRAY
:
1727 case TYPE_CODE_UNION
:
1730 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1731 invisible reference. */
1733 /* Allocate aligned storage. */
1734 sp
= align_down (sp
- len
, 16);
1736 /* Write the real data into the stack. */
1737 write_memory (sp
, value_contents (arg
), len
);
1739 /* Construct the indirection. */
1740 arg_type
= lookup_pointer_type (arg_type
);
1741 arg
= value_from_pointer (arg_type
, sp
);
1742 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1745 /* PCS C.15 / C.18 multiple values pass. */
1746 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1750 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1755 /* Make sure stack retains 16 byte alignment. */
1757 sp
-= 16 - (info
.nsaa
& 15);
1759 while (!info
.si
.empty ())
1761 const stack_item_t
&si
= info
.si
.back ();
1764 if (si
.data
!= NULL
)
1765 write_memory (sp
, si
.data
, si
.len
);
1766 info
.si
.pop_back ();
1769 /* Finally, update the SP register. */
1770 regcache_cooked_write_unsigned (regcache
, AARCH64_SP_REGNUM
, sp
);
1775 /* Implement the "frame_align" gdbarch method. */
1778 aarch64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1780 /* Align the stack to sixteen bytes. */
1781 return sp
& ~(CORE_ADDR
) 15;
1784 /* Return the type for an AdvSISD Q register. */
1786 static struct type
*
1787 aarch64_vnq_type (struct gdbarch
*gdbarch
)
1789 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1791 if (tdep
->vnq_type
== NULL
)
1796 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
1799 elem
= builtin_type (gdbarch
)->builtin_uint128
;
1800 append_composite_type_field (t
, "u", elem
);
1802 elem
= builtin_type (gdbarch
)->builtin_int128
;
1803 append_composite_type_field (t
, "s", elem
);
1808 return tdep
->vnq_type
;
1811 /* Return the type for an AdvSISD D register. */
1813 static struct type
*
1814 aarch64_vnd_type (struct gdbarch
*gdbarch
)
1816 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1818 if (tdep
->vnd_type
== NULL
)
1823 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
1826 elem
= builtin_type (gdbarch
)->builtin_double
;
1827 append_composite_type_field (t
, "f", elem
);
1829 elem
= builtin_type (gdbarch
)->builtin_uint64
;
1830 append_composite_type_field (t
, "u", elem
);
1832 elem
= builtin_type (gdbarch
)->builtin_int64
;
1833 append_composite_type_field (t
, "s", elem
);
1838 return tdep
->vnd_type
;
1841 /* Return the type for an AdvSISD S register. */
1843 static struct type
*
1844 aarch64_vns_type (struct gdbarch
*gdbarch
)
1846 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1848 if (tdep
->vns_type
== NULL
)
1853 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
1856 elem
= builtin_type (gdbarch
)->builtin_float
;
1857 append_composite_type_field (t
, "f", elem
);
1859 elem
= builtin_type (gdbarch
)->builtin_uint32
;
1860 append_composite_type_field (t
, "u", elem
);
1862 elem
= builtin_type (gdbarch
)->builtin_int32
;
1863 append_composite_type_field (t
, "s", elem
);
1868 return tdep
->vns_type
;
1871 /* Return the type for an AdvSISD H register. */
1873 static struct type
*
1874 aarch64_vnh_type (struct gdbarch
*gdbarch
)
1876 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1878 if (tdep
->vnh_type
== NULL
)
1883 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
1886 elem
= builtin_type (gdbarch
)->builtin_half
;
1887 append_composite_type_field (t
, "f", elem
);
1889 elem
= builtin_type (gdbarch
)->builtin_uint16
;
1890 append_composite_type_field (t
, "u", elem
);
1892 elem
= builtin_type (gdbarch
)->builtin_int16
;
1893 append_composite_type_field (t
, "s", elem
);
1898 return tdep
->vnh_type
;
1901 /* Return the type for an AdvSISD B register. */
1903 static struct type
*
1904 aarch64_vnb_type (struct gdbarch
*gdbarch
)
1906 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1908 if (tdep
->vnb_type
== NULL
)
1913 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
1916 elem
= builtin_type (gdbarch
)->builtin_uint8
;
1917 append_composite_type_field (t
, "u", elem
);
1919 elem
= builtin_type (gdbarch
)->builtin_int8
;
1920 append_composite_type_field (t
, "s", elem
);
1925 return tdep
->vnb_type
;
1928 /* Return the type for an AdvSISD V register. */
1930 static struct type
*
1931 aarch64_vnv_type (struct gdbarch
*gdbarch
)
1933 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1935 if (tdep
->vnv_type
== NULL
)
1937 /* The other AArch64 psuedo registers (Q,D,H,S,B) refer to a single value
1938 slice from the non-pseudo vector registers. However NEON V registers
1939 are always vector registers, and need constructing as such. */
1940 const struct builtin_type
*bt
= builtin_type (gdbarch
);
1942 struct type
*t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnv",
1945 struct type
*sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
1947 append_composite_type_field (sub
, "f",
1948 init_vector_type (bt
->builtin_double
, 2));
1949 append_composite_type_field (sub
, "u",
1950 init_vector_type (bt
->builtin_uint64
, 2));
1951 append_composite_type_field (sub
, "s",
1952 init_vector_type (bt
->builtin_int64
, 2));
1953 append_composite_type_field (t
, "d", sub
);
1955 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
1957 append_composite_type_field (sub
, "f",
1958 init_vector_type (bt
->builtin_float
, 4));
1959 append_composite_type_field (sub
, "u",
1960 init_vector_type (bt
->builtin_uint32
, 4));
1961 append_composite_type_field (sub
, "s",
1962 init_vector_type (bt
->builtin_int32
, 4));
1963 append_composite_type_field (t
, "s", sub
);
1965 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
1967 append_composite_type_field (sub
, "f",
1968 init_vector_type (bt
->builtin_half
, 8));
1969 append_composite_type_field (sub
, "u",
1970 init_vector_type (bt
->builtin_uint16
, 8));
1971 append_composite_type_field (sub
, "s",
1972 init_vector_type (bt
->builtin_int16
, 8));
1973 append_composite_type_field (t
, "h", sub
);
1975 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
1977 append_composite_type_field (sub
, "u",
1978 init_vector_type (bt
->builtin_uint8
, 16));
1979 append_composite_type_field (sub
, "s",
1980 init_vector_type (bt
->builtin_int8
, 16));
1981 append_composite_type_field (t
, "b", sub
);
1983 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
1985 append_composite_type_field (sub
, "u",
1986 init_vector_type (bt
->builtin_uint128
, 1));
1987 append_composite_type_field (sub
, "s",
1988 init_vector_type (bt
->builtin_int128
, 1));
1989 append_composite_type_field (t
, "q", sub
);
1994 return tdep
->vnv_type
;
1997 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
2000 aarch64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
2002 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2004 if (reg
>= AARCH64_DWARF_X0
&& reg
<= AARCH64_DWARF_X0
+ 30)
2005 return AARCH64_X0_REGNUM
+ reg
- AARCH64_DWARF_X0
;
2007 if (reg
== AARCH64_DWARF_SP
)
2008 return AARCH64_SP_REGNUM
;
2010 if (reg
>= AARCH64_DWARF_V0
&& reg
<= AARCH64_DWARF_V0
+ 31)
2011 return AARCH64_V0_REGNUM
+ reg
- AARCH64_DWARF_V0
;
2013 if (reg
== AARCH64_DWARF_SVE_VG
)
2014 return AARCH64_SVE_VG_REGNUM
;
2016 if (reg
== AARCH64_DWARF_SVE_FFR
)
2017 return AARCH64_SVE_FFR_REGNUM
;
2019 if (reg
>= AARCH64_DWARF_SVE_P0
&& reg
<= AARCH64_DWARF_SVE_P0
+ 15)
2020 return AARCH64_SVE_P0_REGNUM
+ reg
- AARCH64_DWARF_SVE_P0
;
2022 if (reg
>= AARCH64_DWARF_SVE_Z0
&& reg
<= AARCH64_DWARF_SVE_Z0
+ 15)
2023 return AARCH64_SVE_Z0_REGNUM
+ reg
- AARCH64_DWARF_SVE_Z0
;
2025 if (tdep
->has_pauth ())
2027 if (reg
>= AARCH64_DWARF_PAUTH_DMASK
&& reg
<= AARCH64_DWARF_PAUTH_CMASK
)
2028 return tdep
->pauth_reg_base
+ reg
- AARCH64_DWARF_PAUTH_DMASK
;
2030 if (reg
== AARCH64_DWARF_PAUTH_RA_STATE
)
2031 return tdep
->pauth_ra_state_regnum
;
2037 /* Implement the "print_insn" gdbarch method. */
2040 aarch64_gdb_print_insn (bfd_vma memaddr
, disassemble_info
*info
)
2042 info
->symbols
= NULL
;
2043 return default_print_insn (memaddr
, info
);
2046 /* AArch64 BRK software debug mode instruction.
2047 Note that AArch64 code is always little-endian.
2048 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
2049 constexpr gdb_byte aarch64_default_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
2051 typedef BP_MANIPULATION (aarch64_default_breakpoint
) aarch64_breakpoint
;
2053 /* Extract from an array REGS containing the (raw) register state a
2054 function return value of type TYPE, and copy that, in virtual
2055 format, into VALBUF. */
2058 aarch64_extract_return_value (struct type
*type
, struct regcache
*regs
,
2061 struct gdbarch
*gdbarch
= regs
->arch ();
2062 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2064 struct type
*fundamental_type
;
2066 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2069 int len
= TYPE_LENGTH (fundamental_type
);
2071 for (int i
= 0; i
< elements
; i
++)
2073 int regno
= AARCH64_V0_REGNUM
+ i
;
2074 /* Enough space for a full vector register. */
2075 gdb_byte buf
[register_size (gdbarch
, regno
)];
2076 gdb_assert (len
<= sizeof (buf
));
2080 debug_printf ("read HFA or HVA return value element %d from %s\n",
2082 gdbarch_register_name (gdbarch
, regno
));
2084 regs
->cooked_read (regno
, buf
);
2086 memcpy (valbuf
, buf
, len
);
2090 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2091 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2092 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2093 || TYPE_CODE (type
) == TYPE_CODE_PTR
2094 || TYPE_IS_REFERENCE (type
)
2095 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2097 /* If the type is a plain integer, then the access is
2098 straight-forward. Otherwise we have to play around a bit
2100 int len
= TYPE_LENGTH (type
);
2101 int regno
= AARCH64_X0_REGNUM
;
2106 /* By using store_unsigned_integer we avoid having to do
2107 anything special for small big-endian values. */
2108 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2109 store_unsigned_integer (valbuf
,
2110 (len
> X_REGISTER_SIZE
2111 ? X_REGISTER_SIZE
: len
), byte_order
, tmp
);
2112 len
-= X_REGISTER_SIZE
;
2113 valbuf
+= X_REGISTER_SIZE
;
2118 /* For a structure or union the behaviour is as if the value had
2119 been stored to word-aligned memory and then loaded into
2120 registers with 64-bit load instruction(s). */
2121 int len
= TYPE_LENGTH (type
);
2122 int regno
= AARCH64_X0_REGNUM
;
2123 bfd_byte buf
[X_REGISTER_SIZE
];
2127 regs
->cooked_read (regno
++, buf
);
2128 memcpy (valbuf
, buf
, len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2129 len
-= X_REGISTER_SIZE
;
2130 valbuf
+= X_REGISTER_SIZE
;
2136 /* Will a function return an aggregate type in memory or in a
2137 register? Return 0 if an aggregate type can be returned in a
2138 register, 1 if it must be returned in memory. */
2141 aarch64_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2143 type
= check_typedef (type
);
2145 struct type
*fundamental_type
;
2147 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2150 /* v0-v7 are used to return values and one register is allocated
2151 for one member. However, HFA or HVA has at most four members. */
2155 if (TYPE_LENGTH (type
) > 16)
2157 /* PCS B.6 Aggregates larger than 16 bytes are passed by
2158 invisible reference. */
2166 /* Write into appropriate registers a function return value of type
2167 TYPE, given in virtual format. */
2170 aarch64_store_return_value (struct type
*type
, struct regcache
*regs
,
2171 const gdb_byte
*valbuf
)
2173 struct gdbarch
*gdbarch
= regs
->arch ();
2174 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2176 struct type
*fundamental_type
;
2178 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2181 int len
= TYPE_LENGTH (fundamental_type
);
2183 for (int i
= 0; i
< elements
; i
++)
2185 int regno
= AARCH64_V0_REGNUM
+ i
;
2186 /* Enough space for a full vector register. */
2187 gdb_byte tmpbuf
[register_size (gdbarch
, regno
)];
2188 gdb_assert (len
<= sizeof (tmpbuf
));
2192 debug_printf ("write HFA or HVA return value element %d to %s\n",
2194 gdbarch_register_name (gdbarch
, regno
));
2197 memcpy (tmpbuf
, valbuf
,
2198 len
> V_REGISTER_SIZE
? V_REGISTER_SIZE
: len
);
2199 regs
->cooked_write (regno
, tmpbuf
);
2203 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2204 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2205 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2206 || TYPE_CODE (type
) == TYPE_CODE_PTR
2207 || TYPE_IS_REFERENCE (type
)
2208 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2210 if (TYPE_LENGTH (type
) <= X_REGISTER_SIZE
)
2212 /* Values of one word or less are zero/sign-extended and
2214 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2215 LONGEST val
= unpack_long (type
, valbuf
);
2217 store_signed_integer (tmpbuf
, X_REGISTER_SIZE
, byte_order
, val
);
2218 regs
->cooked_write (AARCH64_X0_REGNUM
, tmpbuf
);
2222 /* Integral values greater than one word are stored in
2223 consecutive registers starting with r0. This will always
2224 be a multiple of the regiser size. */
2225 int len
= TYPE_LENGTH (type
);
2226 int regno
= AARCH64_X0_REGNUM
;
2230 regs
->cooked_write (regno
++, valbuf
);
2231 len
-= X_REGISTER_SIZE
;
2232 valbuf
+= X_REGISTER_SIZE
;
2238 /* For a structure or union the behaviour is as if the value had
2239 been stored to word-aligned memory and then loaded into
2240 registers with 64-bit load instruction(s). */
2241 int len
= TYPE_LENGTH (type
);
2242 int regno
= AARCH64_X0_REGNUM
;
2243 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2247 memcpy (tmpbuf
, valbuf
,
2248 len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2249 regs
->cooked_write (regno
++, tmpbuf
);
2250 len
-= X_REGISTER_SIZE
;
2251 valbuf
+= X_REGISTER_SIZE
;
2256 /* Implement the "return_value" gdbarch method. */
2258 static enum return_value_convention
2259 aarch64_return_value (struct gdbarch
*gdbarch
, struct value
*func_value
,
2260 struct type
*valtype
, struct regcache
*regcache
,
2261 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2264 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2265 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2266 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2268 if (aarch64_return_in_memory (gdbarch
, valtype
))
2271 debug_printf ("return value in memory\n");
2272 return RETURN_VALUE_STRUCT_CONVENTION
;
2277 aarch64_store_return_value (valtype
, regcache
, writebuf
);
2280 aarch64_extract_return_value (valtype
, regcache
, readbuf
);
2283 debug_printf ("return value in registers\n");
2285 return RETURN_VALUE_REGISTER_CONVENTION
;
2288 /* Implement the "get_longjmp_target" gdbarch method. */
2291 aarch64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2294 gdb_byte buf
[X_REGISTER_SIZE
];
2295 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2296 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2297 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2299 jb_addr
= get_frame_register_unsigned (frame
, AARCH64_X0_REGNUM
);
2301 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2305 *pc
= extract_unsigned_integer (buf
, X_REGISTER_SIZE
, byte_order
);
2309 /* Implement the "gen_return_address" gdbarch method. */
2312 aarch64_gen_return_address (struct gdbarch
*gdbarch
,
2313 struct agent_expr
*ax
, struct axs_value
*value
,
2316 value
->type
= register_type (gdbarch
, AARCH64_LR_REGNUM
);
2317 value
->kind
= axs_lvalue_register
;
2318 value
->u
.reg
= AARCH64_LR_REGNUM
;
2322 /* Return the pseudo register name corresponding to register regnum. */
2325 aarch64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
2327 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2329 static const char *const q_name
[] =
2331 "q0", "q1", "q2", "q3",
2332 "q4", "q5", "q6", "q7",
2333 "q8", "q9", "q10", "q11",
2334 "q12", "q13", "q14", "q15",
2335 "q16", "q17", "q18", "q19",
2336 "q20", "q21", "q22", "q23",
2337 "q24", "q25", "q26", "q27",
2338 "q28", "q29", "q30", "q31",
2341 static const char *const d_name
[] =
2343 "d0", "d1", "d2", "d3",
2344 "d4", "d5", "d6", "d7",
2345 "d8", "d9", "d10", "d11",
2346 "d12", "d13", "d14", "d15",
2347 "d16", "d17", "d18", "d19",
2348 "d20", "d21", "d22", "d23",
2349 "d24", "d25", "d26", "d27",
2350 "d28", "d29", "d30", "d31",
2353 static const char *const s_name
[] =
2355 "s0", "s1", "s2", "s3",
2356 "s4", "s5", "s6", "s7",
2357 "s8", "s9", "s10", "s11",
2358 "s12", "s13", "s14", "s15",
2359 "s16", "s17", "s18", "s19",
2360 "s20", "s21", "s22", "s23",
2361 "s24", "s25", "s26", "s27",
2362 "s28", "s29", "s30", "s31",
2365 static const char *const h_name
[] =
2367 "h0", "h1", "h2", "h3",
2368 "h4", "h5", "h6", "h7",
2369 "h8", "h9", "h10", "h11",
2370 "h12", "h13", "h14", "h15",
2371 "h16", "h17", "h18", "h19",
2372 "h20", "h21", "h22", "h23",
2373 "h24", "h25", "h26", "h27",
2374 "h28", "h29", "h30", "h31",
2377 static const char *const b_name
[] =
2379 "b0", "b1", "b2", "b3",
2380 "b4", "b5", "b6", "b7",
2381 "b8", "b9", "b10", "b11",
2382 "b12", "b13", "b14", "b15",
2383 "b16", "b17", "b18", "b19",
2384 "b20", "b21", "b22", "b23",
2385 "b24", "b25", "b26", "b27",
2386 "b28", "b29", "b30", "b31",
2389 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2391 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2392 return q_name
[p_regnum
- AARCH64_Q0_REGNUM
];
2394 if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2395 return d_name
[p_regnum
- AARCH64_D0_REGNUM
];
2397 if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2398 return s_name
[p_regnum
- AARCH64_S0_REGNUM
];
2400 if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2401 return h_name
[p_regnum
- AARCH64_H0_REGNUM
];
2403 if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2404 return b_name
[p_regnum
- AARCH64_B0_REGNUM
];
2406 if (tdep
->has_sve ())
2408 static const char *const sve_v_name
[] =
2410 "v0", "v1", "v2", "v3",
2411 "v4", "v5", "v6", "v7",
2412 "v8", "v9", "v10", "v11",
2413 "v12", "v13", "v14", "v15",
2414 "v16", "v17", "v18", "v19",
2415 "v20", "v21", "v22", "v23",
2416 "v24", "v25", "v26", "v27",
2417 "v28", "v29", "v30", "v31",
2420 if (p_regnum
>= AARCH64_SVE_V0_REGNUM
2421 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2422 return sve_v_name
[p_regnum
- AARCH64_SVE_V0_REGNUM
];
2425 /* RA_STATE is used for unwinding only. Do not assign it a name - this
2426 prevents it from being read by methods such as
2427 mi_cmd_trace_frame_collected. */
2428 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2431 internal_error (__FILE__
, __LINE__
,
2432 _("aarch64_pseudo_register_name: bad register number %d"),
2436 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
2438 static struct type
*
2439 aarch64_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2441 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2443 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2445 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2446 return aarch64_vnq_type (gdbarch
);
2448 if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2449 return aarch64_vnd_type (gdbarch
);
2451 if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2452 return aarch64_vns_type (gdbarch
);
2454 if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2455 return aarch64_vnh_type (gdbarch
);
2457 if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2458 return aarch64_vnb_type (gdbarch
);
2460 if (tdep
->has_sve () && p_regnum
>= AARCH64_SVE_V0_REGNUM
2461 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2462 return aarch64_vnv_type (gdbarch
);
2464 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2465 return builtin_type (gdbarch
)->builtin_uint64
;
2467 internal_error (__FILE__
, __LINE__
,
2468 _("aarch64_pseudo_register_type: bad register number %d"),
2472 /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2475 aarch64_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2476 struct reggroup
*group
)
2478 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2480 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2482 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2483 return group
== all_reggroup
|| group
== vector_reggroup
;
2484 else if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2485 return (group
== all_reggroup
|| group
== vector_reggroup
2486 || group
== float_reggroup
);
2487 else if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2488 return (group
== all_reggroup
|| group
== vector_reggroup
2489 || group
== float_reggroup
);
2490 else if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2491 return group
== all_reggroup
|| group
== vector_reggroup
;
2492 else if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2493 return group
== all_reggroup
|| group
== vector_reggroup
;
2494 else if (tdep
->has_sve () && p_regnum
>= AARCH64_SVE_V0_REGNUM
2495 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2496 return group
== all_reggroup
|| group
== vector_reggroup
;
2497 /* RA_STATE is used for unwinding only. Do not assign it to any groups. */
2498 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2501 return group
== all_reggroup
;
2504 /* Helper for aarch64_pseudo_read_value. */
2506 static struct value
*
2507 aarch64_pseudo_read_value_1 (struct gdbarch
*gdbarch
,
2508 readable_regcache
*regcache
, int regnum_offset
,
2509 int regsize
, struct value
*result_value
)
2511 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2513 /* Enough space for a full vector register. */
2514 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2515 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2517 if (regcache
->raw_read (v_regnum
, reg_buf
) != REG_VALID
)
2518 mark_value_bytes_unavailable (result_value
, 0,
2519 TYPE_LENGTH (value_type (result_value
)));
2521 memcpy (value_contents_raw (result_value
), reg_buf
, regsize
);
2523 return result_value
;
2526 /* Implement the "pseudo_register_read_value" gdbarch method. */
2528 static struct value
*
2529 aarch64_pseudo_read_value (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2532 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2533 struct value
*result_value
= allocate_value (register_type (gdbarch
, regnum
));
2535 VALUE_LVAL (result_value
) = lval_register
;
2536 VALUE_REGNUM (result_value
) = regnum
;
2538 regnum
-= gdbarch_num_regs (gdbarch
);
2540 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2541 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2542 regnum
- AARCH64_Q0_REGNUM
,
2543 Q_REGISTER_SIZE
, result_value
);
2545 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2546 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2547 regnum
- AARCH64_D0_REGNUM
,
2548 D_REGISTER_SIZE
, result_value
);
2550 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2551 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2552 regnum
- AARCH64_S0_REGNUM
,
2553 S_REGISTER_SIZE
, result_value
);
2555 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2556 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2557 regnum
- AARCH64_H0_REGNUM
,
2558 H_REGISTER_SIZE
, result_value
);
2560 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2561 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2562 regnum
- AARCH64_B0_REGNUM
,
2563 B_REGISTER_SIZE
, result_value
);
2565 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2566 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2567 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2568 regnum
- AARCH64_SVE_V0_REGNUM
,
2569 V_REGISTER_SIZE
, result_value
);
2571 gdb_assert_not_reached ("regnum out of bound");
2574 /* Helper for aarch64_pseudo_write. */
2577 aarch64_pseudo_write_1 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2578 int regnum_offset
, int regsize
, const gdb_byte
*buf
)
2580 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2582 /* Enough space for a full vector register. */
2583 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2584 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2586 /* Ensure the register buffer is zero, we want gdb writes of the
2587 various 'scalar' pseudo registers to behavior like architectural
2588 writes, register width bytes are written the remainder are set to
2590 memset (reg_buf
, 0, register_size (gdbarch
, AARCH64_V0_REGNUM
));
2592 memcpy (reg_buf
, buf
, regsize
);
2593 regcache
->raw_write (v_regnum
, reg_buf
);
2596 /* Implement the "pseudo_register_write" gdbarch method. */
2599 aarch64_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2600 int regnum
, const gdb_byte
*buf
)
2602 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2603 regnum
-= gdbarch_num_regs (gdbarch
);
2605 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2606 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2607 regnum
- AARCH64_Q0_REGNUM
, Q_REGISTER_SIZE
,
2610 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2611 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2612 regnum
- AARCH64_D0_REGNUM
, D_REGISTER_SIZE
,
2615 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2616 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2617 regnum
- AARCH64_S0_REGNUM
, S_REGISTER_SIZE
,
2620 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2621 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2622 regnum
- AARCH64_H0_REGNUM
, H_REGISTER_SIZE
,
2625 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2626 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2627 regnum
- AARCH64_B0_REGNUM
, B_REGISTER_SIZE
,
2630 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2631 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2632 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2633 regnum
- AARCH64_SVE_V0_REGNUM
,
2634 V_REGISTER_SIZE
, buf
);
2636 gdb_assert_not_reached ("regnum out of bound");
2639 /* Callback function for user_reg_add. */
2641 static struct value
*
2642 value_of_aarch64_user_reg (struct frame_info
*frame
, const void *baton
)
2644 const int *reg_p
= (const int *) baton
;
2646 return value_of_register (*reg_p
, frame
);
2650 /* Implement the "software_single_step" gdbarch method, needed to
2651 single step through atomic sequences on AArch64. */
2653 static std::vector
<CORE_ADDR
>
2654 aarch64_software_single_step (struct regcache
*regcache
)
2656 struct gdbarch
*gdbarch
= regcache
->arch ();
2657 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2658 const int insn_size
= 4;
2659 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2660 CORE_ADDR pc
= regcache_read_pc (regcache
);
2661 CORE_ADDR breaks
[2] = { CORE_ADDR_MAX
, CORE_ADDR_MAX
};
2663 CORE_ADDR closing_insn
= 0;
2664 uint32_t insn
= read_memory_unsigned_integer (loc
, insn_size
,
2665 byte_order_for_code
);
2668 int bc_insn_count
= 0; /* Conditional branch instruction count. */
2669 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2672 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2675 /* Look for a Load Exclusive instruction which begins the sequence. */
2676 if (inst
.opcode
->iclass
!= ldstexcl
|| bit (insn
, 22) == 0)
2679 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2682 insn
= read_memory_unsigned_integer (loc
, insn_size
,
2683 byte_order_for_code
);
2685 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2687 /* Check if the instruction is a conditional branch. */
2688 if (inst
.opcode
->iclass
== condbranch
)
2690 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_ADDR_PCREL19
);
2692 if (bc_insn_count
>= 1)
2695 /* It is, so we'll try to set a breakpoint at the destination. */
2696 breaks
[1] = loc
+ inst
.operands
[0].imm
.value
;
2702 /* Look for the Store Exclusive which closes the atomic sequence. */
2703 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22) == 0)
2710 /* We didn't find a closing Store Exclusive instruction, fall back. */
2714 /* Insert breakpoint after the end of the atomic sequence. */
2715 breaks
[0] = loc
+ insn_size
;
2717 /* Check for duplicated breakpoints, and also check that the second
2718 breakpoint is not within the atomic sequence. */
2720 && (breaks
[1] == breaks
[0]
2721 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
2722 last_breakpoint
= 0;
2724 std::vector
<CORE_ADDR
> next_pcs
;
2726 /* Insert the breakpoint at the end of the sequence, and one at the
2727 destination of the conditional branch, if it exists. */
2728 for (index
= 0; index
<= last_breakpoint
; index
++)
2729 next_pcs
.push_back (breaks
[index
]);
2734 struct aarch64_displaced_step_closure
: public displaced_step_closure
2736 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2737 is being displaced stepping. */
2740 /* PC adjustment offset after displaced stepping. If 0, then we don't
2741 write the PC back, assuming the PC is already the right address. */
2742 int32_t pc_adjust
= 0;
2745 /* Data when visiting instructions for displaced stepping. */
2747 struct aarch64_displaced_step_data
2749 struct aarch64_insn_data base
;
2751 /* The address where the instruction will be executed at. */
2753 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2754 uint32_t insn_buf
[AARCH64_DISPLACED_MODIFIED_INSNS
];
2755 /* Number of instructions in INSN_BUF. */
2756 unsigned insn_count
;
2757 /* Registers when doing displaced stepping. */
2758 struct regcache
*regs
;
2760 aarch64_displaced_step_closure
*dsc
;
2763 /* Implementation of aarch64_insn_visitor method "b". */
2766 aarch64_displaced_step_b (const int is_bl
, const int32_t offset
,
2767 struct aarch64_insn_data
*data
)
2769 struct aarch64_displaced_step_data
*dsd
2770 = (struct aarch64_displaced_step_data
*) data
;
2771 int64_t new_offset
= data
->insn_addr
- dsd
->new_addr
+ offset
;
2773 if (can_encode_int32 (new_offset
, 28))
2775 /* Emit B rather than BL, because executing BL on a new address
2776 will get the wrong address into LR. In order to avoid this,
2777 we emit B, and update LR if the instruction is BL. */
2778 emit_b (dsd
->insn_buf
, 0, new_offset
);
2784 emit_nop (dsd
->insn_buf
);
2786 dsd
->dsc
->pc_adjust
= offset
;
2792 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_LR_REGNUM
,
2793 data
->insn_addr
+ 4);
2797 /* Implementation of aarch64_insn_visitor method "b_cond". */
2800 aarch64_displaced_step_b_cond (const unsigned cond
, const int32_t offset
,
2801 struct aarch64_insn_data
*data
)
2803 struct aarch64_displaced_step_data
*dsd
2804 = (struct aarch64_displaced_step_data
*) data
;
2806 /* GDB has to fix up PC after displaced step this instruction
2807 differently according to the condition is true or false. Instead
2808 of checking COND against conditional flags, we can use
2809 the following instructions, and GDB can tell how to fix up PC
2810 according to the PC value.
2812 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2818 emit_bcond (dsd
->insn_buf
, cond
, 8);
2820 dsd
->dsc
->pc_adjust
= offset
;
2821 dsd
->insn_count
= 1;
2824 /* Dynamically allocate a new register. If we know the register
2825 statically, we should make it a global as above instead of using this
2828 static struct aarch64_register
2829 aarch64_register (unsigned num
, int is64
)
2831 return (struct aarch64_register
) { num
, is64
};
2834 /* Implementation of aarch64_insn_visitor method "cb". */
2837 aarch64_displaced_step_cb (const int32_t offset
, const int is_cbnz
,
2838 const unsigned rn
, int is64
,
2839 struct aarch64_insn_data
*data
)
2841 struct aarch64_displaced_step_data
*dsd
2842 = (struct aarch64_displaced_step_data
*) data
;
2844 /* The offset is out of range for a compare and branch
2845 instruction. We can use the following instructions instead:
2847 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2852 emit_cb (dsd
->insn_buf
, is_cbnz
, aarch64_register (rn
, is64
), 8);
2853 dsd
->insn_count
= 1;
2855 dsd
->dsc
->pc_adjust
= offset
;
2858 /* Implementation of aarch64_insn_visitor method "tb". */
2861 aarch64_displaced_step_tb (const int32_t offset
, int is_tbnz
,
2862 const unsigned rt
, unsigned bit
,
2863 struct aarch64_insn_data
*data
)
2865 struct aarch64_displaced_step_data
*dsd
2866 = (struct aarch64_displaced_step_data
*) data
;
2868 /* The offset is out of range for a test bit and branch
2869 instruction We can use the following instructions instead:
2871 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2877 emit_tb (dsd
->insn_buf
, is_tbnz
, bit
, aarch64_register (rt
, 1), 8);
2878 dsd
->insn_count
= 1;
2880 dsd
->dsc
->pc_adjust
= offset
;
2883 /* Implementation of aarch64_insn_visitor method "adr". */
2886 aarch64_displaced_step_adr (const int32_t offset
, const unsigned rd
,
2887 const int is_adrp
, struct aarch64_insn_data
*data
)
2889 struct aarch64_displaced_step_data
*dsd
2890 = (struct aarch64_displaced_step_data
*) data
;
2891 /* We know exactly the address the ADR{P,} instruction will compute.
2892 We can just write it to the destination register. */
2893 CORE_ADDR address
= data
->insn_addr
+ offset
;
2897 /* Clear the lower 12 bits of the offset to get the 4K page. */
2898 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
2902 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
2905 dsd
->dsc
->pc_adjust
= 4;
2906 emit_nop (dsd
->insn_buf
);
2907 dsd
->insn_count
= 1;
2910 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
2913 aarch64_displaced_step_ldr_literal (const int32_t offset
, const int is_sw
,
2914 const unsigned rt
, const int is64
,
2915 struct aarch64_insn_data
*data
)
2917 struct aarch64_displaced_step_data
*dsd
2918 = (struct aarch64_displaced_step_data
*) data
;
2919 CORE_ADDR address
= data
->insn_addr
+ offset
;
2920 struct aarch64_memory_operand zero
= { MEMORY_OPERAND_OFFSET
, 0 };
2922 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rt
,
2926 dsd
->insn_count
= emit_ldrsw (dsd
->insn_buf
, aarch64_register (rt
, 1),
2927 aarch64_register (rt
, 1), zero
);
2929 dsd
->insn_count
= emit_ldr (dsd
->insn_buf
, aarch64_register (rt
, is64
),
2930 aarch64_register (rt
, 1), zero
);
2932 dsd
->dsc
->pc_adjust
= 4;
2935 /* Implementation of aarch64_insn_visitor method "others". */
2938 aarch64_displaced_step_others (const uint32_t insn
,
2939 struct aarch64_insn_data
*data
)
2941 struct aarch64_displaced_step_data
*dsd
2942 = (struct aarch64_displaced_step_data
*) data
;
2944 aarch64_emit_insn (dsd
->insn_buf
, insn
);
2945 dsd
->insn_count
= 1;
2947 if ((insn
& 0xfffffc1f) == 0xd65f0000)
2950 dsd
->dsc
->pc_adjust
= 0;
2953 dsd
->dsc
->pc_adjust
= 4;
2956 static const struct aarch64_insn_visitor visitor
=
2958 aarch64_displaced_step_b
,
2959 aarch64_displaced_step_b_cond
,
2960 aarch64_displaced_step_cb
,
2961 aarch64_displaced_step_tb
,
2962 aarch64_displaced_step_adr
,
2963 aarch64_displaced_step_ldr_literal
,
2964 aarch64_displaced_step_others
,
2967 /* Implement the "displaced_step_copy_insn" gdbarch method. */
2969 struct displaced_step_closure
*
2970 aarch64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
2971 CORE_ADDR from
, CORE_ADDR to
,
2972 struct regcache
*regs
)
2974 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2975 uint32_t insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
2976 struct aarch64_displaced_step_data dsd
;
2979 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2982 /* Look for a Load Exclusive instruction which begins the sequence. */
2983 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22))
2985 /* We can't displaced step atomic sequences. */
2989 std::unique_ptr
<aarch64_displaced_step_closure
> dsc
2990 (new aarch64_displaced_step_closure
);
2991 dsd
.base
.insn_addr
= from
;
2994 dsd
.dsc
= dsc
.get ();
2996 aarch64_relocate_instruction (insn
, &visitor
,
2997 (struct aarch64_insn_data
*) &dsd
);
2998 gdb_assert (dsd
.insn_count
<= AARCH64_DISPLACED_MODIFIED_INSNS
);
3000 if (dsd
.insn_count
!= 0)
3004 /* Instruction can be relocated to scratch pad. Copy
3005 relocated instruction(s) there. */
3006 for (i
= 0; i
< dsd
.insn_count
; i
++)
3008 if (debug_displaced
)
3010 debug_printf ("displaced: writing insn ");
3011 debug_printf ("%.8x", dsd
.insn_buf
[i
]);
3012 debug_printf (" at %s\n", paddress (gdbarch
, to
+ i
* 4));
3014 write_memory_unsigned_integer (to
+ i
* 4, 4, byte_order_for_code
,
3015 (ULONGEST
) dsd
.insn_buf
[i
]);
3023 return dsc
.release ();
3026 /* Implement the "displaced_step_fixup" gdbarch method. */
3029 aarch64_displaced_step_fixup (struct gdbarch
*gdbarch
,
3030 struct displaced_step_closure
*dsc_
,
3031 CORE_ADDR from
, CORE_ADDR to
,
3032 struct regcache
*regs
)
3034 aarch64_displaced_step_closure
*dsc
= (aarch64_displaced_step_closure
*) dsc_
;
3038 regcache_cooked_read_unsigned (regs
, AARCH64_PC_REGNUM
, &pc
);
3040 if (debug_displaced
)
3041 debug_printf ("Displaced: PC after stepping: %s (was %s).\n",
3042 paddress (gdbarch
, pc
), paddress (gdbarch
, to
));
3046 if (debug_displaced
)
3047 debug_printf ("Displaced: [Conditional] pc_adjust before: %d\n",
3052 /* Condition is true. */
3054 else if (pc
- to
== 4)
3056 /* Condition is false. */
3060 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
3062 if (debug_displaced
)
3063 debug_printf ("Displaced: [Conditional] pc_adjust after: %d\n",
3067 if (debug_displaced
)
3068 debug_printf ("Displaced: %s PC by %d\n",
3069 dsc
->pc_adjust
? "adjusting" : "not adjusting",
3073 if (dsc
->pc_adjust
!= 0)
3075 /* Make sure the previous instruction was executed (that is, the PC
3076 has changed). If the PC didn't change, then discard the adjustment
3077 offset. Otherwise we may skip an instruction before its execution
3081 if (debug_displaced
)
3082 debug_printf ("Displaced: PC did not move. Discarding PC "
3087 if (debug_displaced
)
3089 debug_printf ("Displaced: fixup: set PC to %s:%d\n",
3090 paddress (gdbarch
, from
), dsc
->pc_adjust
);
3092 regcache_cooked_write_unsigned (regs
, AARCH64_PC_REGNUM
,
3093 from
+ dsc
->pc_adjust
);
3097 /* Implement the "displaced_step_hw_singlestep" gdbarch method. */
3100 aarch64_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
3101 struct displaced_step_closure
*closure
)
3106 /* Get the correct target description for the given VQ value.
3107 If VQ is zero then it is assumed SVE is not supported.
3108 (It is not possible to set VQ to zero on an SVE system). */
3111 aarch64_read_description (uint64_t vq
, bool pauth_p
)
3113 if (vq
> AARCH64_MAX_SVE_VQ
)
3114 error (_("VQ is %" PRIu64
", maximum supported value is %d"), vq
,
3115 AARCH64_MAX_SVE_VQ
);
3117 struct target_desc
*tdesc
= tdesc_aarch64_list
[vq
][pauth_p
];
3121 tdesc
= aarch64_create_target_description (vq
, pauth_p
);
3122 tdesc_aarch64_list
[vq
][pauth_p
] = tdesc
;
3128 /* Return the VQ used when creating the target description TDESC. */
3131 aarch64_get_tdesc_vq (const struct target_desc
*tdesc
)
3133 const struct tdesc_feature
*feature_sve
;
3135 if (!tdesc_has_registers (tdesc
))
3138 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3140 if (feature_sve
== nullptr)
3143 uint64_t vl
= tdesc_register_bitsize (feature_sve
,
3144 aarch64_sve_register_names
[0]) / 8;
3145 return sve_vq_from_vl (vl
);
3148 /* Add all the expected register sets into GDBARCH. */
3151 aarch64_add_reggroups (struct gdbarch
*gdbarch
)
3153 reggroup_add (gdbarch
, general_reggroup
);
3154 reggroup_add (gdbarch
, float_reggroup
);
3155 reggroup_add (gdbarch
, system_reggroup
);
3156 reggroup_add (gdbarch
, vector_reggroup
);
3157 reggroup_add (gdbarch
, all_reggroup
);
3158 reggroup_add (gdbarch
, save_reggroup
);
3159 reggroup_add (gdbarch
, restore_reggroup
);
3162 /* Implement the "cannot_store_register" gdbarch method. */
3165 aarch64_cannot_store_register (struct gdbarch
*gdbarch
, int regnum
)
3167 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3169 if (!tdep
->has_pauth ())
3172 /* Pointer authentication registers are read-only. */
3173 return (regnum
== AARCH64_PAUTH_DMASK_REGNUM (tdep
->pauth_reg_base
)
3174 || regnum
== AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
));
3177 /* Initialize the current architecture based on INFO. If possible,
3178 re-use an architecture from ARCHES, which is a list of
3179 architectures already created during this debugging session.
3181 Called e.g. at program startup, when reading a core file, and when
3182 reading a binary file. */
3184 static struct gdbarch
*
3185 aarch64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3187 const struct tdesc_feature
*feature_core
, *feature_fpu
, *feature_sve
;
3188 const struct tdesc_feature
*feature_pauth
;
3189 bool valid_p
= true;
3190 int i
, num_regs
= 0, num_pseudo_regs
= 0;
3191 int first_pauth_regnum
= -1, pauth_ra_state_offset
= -1;
3193 /* Use the vector length passed via the target info. Here -1 is used for no
3194 SVE, and 0 is unset. If unset then use the vector length from the existing
3197 if (info
.id
== (int *) -1)
3199 else if (info
.id
!= 0)
3200 vq
= (uint64_t) info
.id
;
3202 vq
= aarch64_get_tdesc_vq (info
.target_desc
);
3204 if (vq
> AARCH64_MAX_SVE_VQ
)
3205 internal_error (__FILE__
, __LINE__
, _("VQ out of bounds: %s (max %d)"),
3206 pulongest (vq
), AARCH64_MAX_SVE_VQ
);
3208 /* If there is already a candidate, use it. */
3209 for (gdbarch_list
*best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
3210 best_arch
!= nullptr;
3211 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
3213 struct gdbarch_tdep
*tdep
= gdbarch_tdep (best_arch
->gdbarch
);
3214 if (tdep
&& tdep
->vq
== vq
)
3215 return best_arch
->gdbarch
;
3218 /* Ensure we always have a target descriptor, and that it is for the given VQ
3220 const struct target_desc
*tdesc
= info
.target_desc
;
3221 if (!tdesc_has_registers (tdesc
) || vq
!= aarch64_get_tdesc_vq (tdesc
))
3222 tdesc
= aarch64_read_description (vq
, false);
3225 feature_core
= tdesc_find_feature (tdesc
,"org.gnu.gdb.aarch64.core");
3226 feature_fpu
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.fpu");
3227 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3228 feature_pauth
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.pauth");
3230 if (feature_core
== nullptr)
3233 struct tdesc_arch_data
*tdesc_data
= tdesc_data_alloc ();
3235 /* Validate the description provides the mandatory core R registers
3236 and allocate their numbers. */
3237 for (i
= 0; i
< ARRAY_SIZE (aarch64_r_register_names
); i
++)
3238 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
,
3239 AARCH64_X0_REGNUM
+ i
,
3240 aarch64_r_register_names
[i
]);
3242 num_regs
= AARCH64_X0_REGNUM
+ i
;
3244 /* Add the V registers. */
3245 if (feature_fpu
!= nullptr)
3247 if (feature_sve
!= nullptr)
3248 error (_("Program contains both fpu and SVE features."));
3250 /* Validate the description provides the mandatory V registers
3251 and allocate their numbers. */
3252 for (i
= 0; i
< ARRAY_SIZE (aarch64_v_register_names
); i
++)
3253 valid_p
&= tdesc_numbered_register (feature_fpu
, tdesc_data
,
3254 AARCH64_V0_REGNUM
+ i
,
3255 aarch64_v_register_names
[i
]);
3257 num_regs
= AARCH64_V0_REGNUM
+ i
;
3260 /* Add the SVE registers. */
3261 if (feature_sve
!= nullptr)
3263 /* Validate the description provides the mandatory SVE registers
3264 and allocate their numbers. */
3265 for (i
= 0; i
< ARRAY_SIZE (aarch64_sve_register_names
); i
++)
3266 valid_p
&= tdesc_numbered_register (feature_sve
, tdesc_data
,
3267 AARCH64_SVE_Z0_REGNUM
+ i
,
3268 aarch64_sve_register_names
[i
]);
3270 num_regs
= AARCH64_SVE_Z0_REGNUM
+ i
;
3271 num_pseudo_regs
+= 32; /* add the Vn register pseudos. */
3274 if (feature_fpu
!= nullptr || feature_sve
!= nullptr)
3276 num_pseudo_regs
+= 32; /* add the Qn scalar register pseudos */
3277 num_pseudo_regs
+= 32; /* add the Dn scalar register pseudos */
3278 num_pseudo_regs
+= 32; /* add the Sn scalar register pseudos */
3279 num_pseudo_regs
+= 32; /* add the Hn scalar register pseudos */
3280 num_pseudo_regs
+= 32; /* add the Bn scalar register pseudos */
3283 /* Add the pauth registers. */
3284 if (feature_pauth
!= NULL
)
3286 first_pauth_regnum
= num_regs
;
3287 pauth_ra_state_offset
= num_pseudo_regs
;
3288 /* Validate the descriptor provides the mandatory PAUTH registers and
3289 allocate their numbers. */
3290 for (i
= 0; i
< ARRAY_SIZE (aarch64_pauth_register_names
); i
++)
3291 valid_p
&= tdesc_numbered_register (feature_pauth
, tdesc_data
,
3292 first_pauth_regnum
+ i
,
3293 aarch64_pauth_register_names
[i
]);
3296 num_pseudo_regs
+= 1; /* Count RA_STATE pseudo register. */
3301 tdesc_data_cleanup (tdesc_data
);
3305 /* AArch64 code is always little-endian. */
3306 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
3308 struct gdbarch_tdep
*tdep
= XCNEW (struct gdbarch_tdep
);
3309 struct gdbarch
*gdbarch
= gdbarch_alloc (&info
, tdep
);
3311 /* This should be low enough for everything. */
3312 tdep
->lowest_pc
= 0x20;
3313 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
3314 tdep
->jb_elt_size
= 8;
3316 tdep
->pauth_reg_base
= first_pauth_regnum
;
3317 tdep
->pauth_ra_state_regnum
= (feature_pauth
== NULL
) ? -1
3318 : pauth_ra_state_offset
+ num_regs
;
3320 set_gdbarch_push_dummy_call (gdbarch
, aarch64_push_dummy_call
);
3321 set_gdbarch_frame_align (gdbarch
, aarch64_frame_align
);
3323 /* Advance PC across function entry code. */
3324 set_gdbarch_skip_prologue (gdbarch
, aarch64_skip_prologue
);
3326 /* The stack grows downward. */
3327 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3329 /* Breakpoint manipulation. */
3330 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
3331 aarch64_breakpoint::kind_from_pc
);
3332 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
3333 aarch64_breakpoint::bp_from_kind
);
3334 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3335 set_gdbarch_software_single_step (gdbarch
, aarch64_software_single_step
);
3337 /* Information about registers, etc. */
3338 set_gdbarch_sp_regnum (gdbarch
, AARCH64_SP_REGNUM
);
3339 set_gdbarch_pc_regnum (gdbarch
, AARCH64_PC_REGNUM
);
3340 set_gdbarch_num_regs (gdbarch
, num_regs
);
3342 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudo_regs
);
3343 set_gdbarch_pseudo_register_read_value (gdbarch
, aarch64_pseudo_read_value
);
3344 set_gdbarch_pseudo_register_write (gdbarch
, aarch64_pseudo_write
);
3345 set_tdesc_pseudo_register_name (gdbarch
, aarch64_pseudo_register_name
);
3346 set_tdesc_pseudo_register_type (gdbarch
, aarch64_pseudo_register_type
);
3347 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3348 aarch64_pseudo_register_reggroup_p
);
3349 set_gdbarch_cannot_store_register (gdbarch
, aarch64_cannot_store_register
);
3352 set_gdbarch_short_bit (gdbarch
, 16);
3353 set_gdbarch_int_bit (gdbarch
, 32);
3354 set_gdbarch_float_bit (gdbarch
, 32);
3355 set_gdbarch_double_bit (gdbarch
, 64);
3356 set_gdbarch_long_double_bit (gdbarch
, 128);
3357 set_gdbarch_long_bit (gdbarch
, 64);
3358 set_gdbarch_long_long_bit (gdbarch
, 64);
3359 set_gdbarch_ptr_bit (gdbarch
, 64);
3360 set_gdbarch_char_signed (gdbarch
, 0);
3361 set_gdbarch_wchar_signed (gdbarch
, 0);
3362 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3363 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3364 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
3365 set_gdbarch_type_align (gdbarch
, aarch64_type_align
);
3367 /* Internal <-> external register number maps. */
3368 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, aarch64_dwarf_reg_to_regnum
);
3370 /* Returning results. */
3371 set_gdbarch_return_value (gdbarch
, aarch64_return_value
);
3374 set_gdbarch_print_insn (gdbarch
, aarch64_gdb_print_insn
);
3376 /* Virtual tables. */
3377 set_gdbarch_vbit_in_delta (gdbarch
, 1);
3379 /* Register architecture. */
3380 aarch64_add_reggroups (gdbarch
);
3382 /* Hook in the ABI-specific overrides, if they have been registered. */
3383 info
.target_desc
= tdesc
;
3384 info
.tdesc_data
= tdesc_data
;
3385 gdbarch_init_osabi (info
, gdbarch
);
3387 dwarf2_frame_set_init_reg (gdbarch
, aarch64_dwarf2_frame_init_reg
);
3388 /* Register DWARF CFA vendor handler. */
3389 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch
,
3390 aarch64_execute_dwarf_cfa_vendor_op
);
3392 /* Add some default predicates. */
3393 frame_unwind_append_unwinder (gdbarch
, &aarch64_stub_unwind
);
3394 dwarf2_append_unwinders (gdbarch
);
3395 frame_unwind_append_unwinder (gdbarch
, &aarch64_prologue_unwind
);
3397 frame_base_set_default (gdbarch
, &aarch64_normal_base
);
3399 /* Now we have tuned the configuration, set a few final things,
3400 based on what the OS ABI has told us. */
3402 if (tdep
->jb_pc
>= 0)
3403 set_gdbarch_get_longjmp_target (gdbarch
, aarch64_get_longjmp_target
);
3405 set_gdbarch_gen_return_address (gdbarch
, aarch64_gen_return_address
);
3407 set_gdbarch_get_pc_address_flags (gdbarch
, aarch64_get_pc_address_flags
);
3409 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
3411 /* Add standard register aliases. */
3412 for (i
= 0; i
< ARRAY_SIZE (aarch64_register_aliases
); i
++)
3413 user_reg_add (gdbarch
, aarch64_register_aliases
[i
].name
,
3414 value_of_aarch64_user_reg
,
3415 &aarch64_register_aliases
[i
].regnum
);
3417 register_aarch64_ravenscar_ops (gdbarch
);
3423 aarch64_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3425 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3430 fprintf_unfiltered (file
, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3431 paddress (gdbarch
, tdep
->lowest_pc
));
3437 static void aarch64_process_record_test (void);
3441 void _initialize_aarch64_tdep ();
3443 _initialize_aarch64_tdep ()
3445 gdbarch_register (bfd_arch_aarch64
, aarch64_gdbarch_init
,
3448 /* Debug this file's internals. */
3449 add_setshow_boolean_cmd ("aarch64", class_maintenance
, &aarch64_debug
, _("\
3450 Set AArch64 debugging."), _("\
3451 Show AArch64 debugging."), _("\
3452 When on, AArch64 specific debugging is enabled."),
3455 &setdebuglist
, &showdebuglist
);
3458 selftests::register_test ("aarch64-analyze-prologue",
3459 selftests::aarch64_analyze_prologue_test
);
3460 selftests::register_test ("aarch64-process-record",
3461 selftests::aarch64_process_record_test
);
3465 /* AArch64 process record-replay related structures, defines etc. */
3467 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3470 unsigned int reg_len = LENGTH; \
3473 REGS = XNEWVEC (uint32_t, reg_len); \
3474 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3479 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3482 unsigned int mem_len = LENGTH; \
3485 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3486 memcpy(&MEMS->len, &RECORD_BUF[0], \
3487 sizeof(struct aarch64_mem_r) * LENGTH); \
3492 /* AArch64 record/replay structures and enumerations. */
3494 struct aarch64_mem_r
3496 uint64_t len
; /* Record length. */
3497 uint64_t addr
; /* Memory address. */
3500 enum aarch64_record_result
3502 AARCH64_RECORD_SUCCESS
,
3503 AARCH64_RECORD_UNSUPPORTED
,
3504 AARCH64_RECORD_UNKNOWN
3507 typedef struct insn_decode_record_t
3509 struct gdbarch
*gdbarch
;
3510 struct regcache
*regcache
;
3511 CORE_ADDR this_addr
; /* Address of insn to be recorded. */
3512 uint32_t aarch64_insn
; /* Insn to be recorded. */
3513 uint32_t mem_rec_count
; /* Count of memory records. */
3514 uint32_t reg_rec_count
; /* Count of register records. */
3515 uint32_t *aarch64_regs
; /* Registers to be recorded. */
3516 struct aarch64_mem_r
*aarch64_mems
; /* Memory locations to be recorded. */
3517 } insn_decode_record
;
3519 /* Record handler for data processing - register instructions. */
3522 aarch64_record_data_proc_reg (insn_decode_record
*aarch64_insn_r
)
3524 uint8_t reg_rd
, insn_bits24_27
, insn_bits21_23
;
3525 uint32_t record_buf
[4];
3527 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3528 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3529 insn_bits21_23
= bits (aarch64_insn_r
->aarch64_insn
, 21, 23);
3531 if (!bit (aarch64_insn_r
->aarch64_insn
, 28))
3535 /* Logical (shifted register). */
3536 if (insn_bits24_27
== 0x0a)
3537 setflags
= (bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03);
3539 else if (insn_bits24_27
== 0x0b)
3540 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3542 return AARCH64_RECORD_UNKNOWN
;
3544 record_buf
[0] = reg_rd
;
3545 aarch64_insn_r
->reg_rec_count
= 1;
3547 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3551 if (insn_bits24_27
== 0x0b)
3553 /* Data-processing (3 source). */
3554 record_buf
[0] = reg_rd
;
3555 aarch64_insn_r
->reg_rec_count
= 1;
3557 else if (insn_bits24_27
== 0x0a)
3559 if (insn_bits21_23
== 0x00)
3561 /* Add/subtract (with carry). */
3562 record_buf
[0] = reg_rd
;
3563 aarch64_insn_r
->reg_rec_count
= 1;
3564 if (bit (aarch64_insn_r
->aarch64_insn
, 29))
3566 record_buf
[1] = AARCH64_CPSR_REGNUM
;
3567 aarch64_insn_r
->reg_rec_count
= 2;
3570 else if (insn_bits21_23
== 0x02)
3572 /* Conditional compare (register) and conditional compare
3573 (immediate) instructions. */
3574 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3575 aarch64_insn_r
->reg_rec_count
= 1;
3577 else if (insn_bits21_23
== 0x04 || insn_bits21_23
== 0x06)
3579 /* Conditional select. */
3580 /* Data-processing (2 source). */
3581 /* Data-processing (1 source). */
3582 record_buf
[0] = reg_rd
;
3583 aarch64_insn_r
->reg_rec_count
= 1;
3586 return AARCH64_RECORD_UNKNOWN
;
3590 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3592 return AARCH64_RECORD_SUCCESS
;
3595 /* Record handler for data processing - immediate instructions. */
3598 aarch64_record_data_proc_imm (insn_decode_record
*aarch64_insn_r
)
3600 uint8_t reg_rd
, insn_bit23
, insn_bits24_27
, setflags
;
3601 uint32_t record_buf
[4];
3603 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3604 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3605 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3607 if (insn_bits24_27
== 0x00 /* PC rel addressing. */
3608 || insn_bits24_27
== 0x03 /* Bitfield and Extract. */
3609 || (insn_bits24_27
== 0x02 && insn_bit23
)) /* Move wide (immediate). */
3611 record_buf
[0] = reg_rd
;
3612 aarch64_insn_r
->reg_rec_count
= 1;
3614 else if (insn_bits24_27
== 0x01)
3616 /* Add/Subtract (immediate). */
3617 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3618 record_buf
[0] = reg_rd
;
3619 aarch64_insn_r
->reg_rec_count
= 1;
3621 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3623 else if (insn_bits24_27
== 0x02 && !insn_bit23
)
3625 /* Logical (immediate). */
3626 setflags
= bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03;
3627 record_buf
[0] = reg_rd
;
3628 aarch64_insn_r
->reg_rec_count
= 1;
3630 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3633 return AARCH64_RECORD_UNKNOWN
;
3635 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3637 return AARCH64_RECORD_SUCCESS
;
3640 /* Record handler for branch, exception generation and system instructions. */
3643 aarch64_record_branch_except_sys (insn_decode_record
*aarch64_insn_r
)
3645 struct gdbarch_tdep
*tdep
= gdbarch_tdep (aarch64_insn_r
->gdbarch
);
3646 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits22_23
;
3647 uint32_t record_buf
[4];
3649 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3650 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
3651 insn_bits22_23
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3653 if (insn_bits28_31
== 0x0d)
3655 /* Exception generation instructions. */
3656 if (insn_bits24_27
== 0x04)
3658 if (!bits (aarch64_insn_r
->aarch64_insn
, 2, 4)
3659 && !bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
3660 && bits (aarch64_insn_r
->aarch64_insn
, 0, 1) == 0x01)
3662 ULONGEST svc_number
;
3664 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, 8,
3666 return tdep
->aarch64_syscall_record (aarch64_insn_r
->regcache
,
3670 return AARCH64_RECORD_UNSUPPORTED
;
3672 /* System instructions. */
3673 else if (insn_bits24_27
== 0x05 && insn_bits22_23
== 0x00)
3675 uint32_t reg_rt
, reg_crn
;
3677 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3678 reg_crn
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3680 /* Record rt in case of sysl and mrs instructions. */
3681 if (bit (aarch64_insn_r
->aarch64_insn
, 21))
3683 record_buf
[0] = reg_rt
;
3684 aarch64_insn_r
->reg_rec_count
= 1;
3686 /* Record cpsr for hint and msr(immediate) instructions. */
3687 else if (reg_crn
== 0x02 || reg_crn
== 0x04)
3689 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3690 aarch64_insn_r
->reg_rec_count
= 1;
3693 /* Unconditional branch (register). */
3694 else if((insn_bits24_27
& 0x0e) == 0x06)
3696 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3697 if (bits (aarch64_insn_r
->aarch64_insn
, 21, 22) == 0x01)
3698 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3701 return AARCH64_RECORD_UNKNOWN
;
3703 /* Unconditional branch (immediate). */
3704 else if ((insn_bits28_31
& 0x07) == 0x01 && (insn_bits24_27
& 0x0c) == 0x04)
3706 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3707 if (bit (aarch64_insn_r
->aarch64_insn
, 31))
3708 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3711 /* Compare & branch (immediate), Test & branch (immediate) and
3712 Conditional branch (immediate). */
3713 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3715 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3717 return AARCH64_RECORD_SUCCESS
;
3720 /* Record handler for advanced SIMD load and store instructions. */
3723 aarch64_record_asimd_load_store (insn_decode_record
*aarch64_insn_r
)
3726 uint64_t addr_offset
= 0;
3727 uint32_t record_buf
[24];
3728 uint64_t record_buf_mem
[24];
3729 uint32_t reg_rn
, reg_rt
;
3730 uint32_t reg_index
= 0, mem_index
= 0;
3731 uint8_t opcode_bits
, size_bits
;
3733 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3734 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3735 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3736 opcode_bits
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3737 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
, &address
);
3740 debug_printf ("Process record: Advanced SIMD load/store\n");
3742 /* Load/store single structure. */
3743 if (bit (aarch64_insn_r
->aarch64_insn
, 24))
3745 uint8_t sindex
, scale
, selem
, esize
, replicate
= 0;
3746 scale
= opcode_bits
>> 2;
3747 selem
= ((opcode_bits
& 0x02) |
3748 bit (aarch64_insn_r
->aarch64_insn
, 21)) + 1;
3752 if (size_bits
& 0x01)
3753 return AARCH64_RECORD_UNKNOWN
;
3756 if ((size_bits
>> 1) & 0x01)
3757 return AARCH64_RECORD_UNKNOWN
;
3758 if (size_bits
& 0x01)
3760 if (!((opcode_bits
>> 1) & 0x01))
3763 return AARCH64_RECORD_UNKNOWN
;
3767 if (bit (aarch64_insn_r
->aarch64_insn
, 22) && !(opcode_bits
& 0x01))
3774 return AARCH64_RECORD_UNKNOWN
;
3780 for (sindex
= 0; sindex
< selem
; sindex
++)
3782 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3783 reg_rt
= (reg_rt
+ 1) % 32;
3787 for (sindex
= 0; sindex
< selem
; sindex
++)
3789 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3790 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3793 record_buf_mem
[mem_index
++] = esize
/ 8;
3794 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3796 addr_offset
= addr_offset
+ (esize
/ 8);
3797 reg_rt
= (reg_rt
+ 1) % 32;
3801 /* Load/store multiple structure. */
3804 uint8_t selem
, esize
, rpt
, elements
;
3805 uint8_t eindex
, rindex
;
3807 esize
= 8 << size_bits
;
3808 if (bit (aarch64_insn_r
->aarch64_insn
, 30))
3809 elements
= 128 / esize
;
3811 elements
= 64 / esize
;
3813 switch (opcode_bits
)
3815 /*LD/ST4 (4 Registers). */
3820 /*LD/ST1 (4 Registers). */
3825 /*LD/ST3 (3 Registers). */
3830 /*LD/ST1 (3 Registers). */
3835 /*LD/ST1 (1 Register). */
3840 /*LD/ST2 (2 Registers). */
3845 /*LD/ST1 (2 Registers). */
3851 return AARCH64_RECORD_UNSUPPORTED
;
3854 for (rindex
= 0; rindex
< rpt
; rindex
++)
3855 for (eindex
= 0; eindex
< elements
; eindex
++)
3857 uint8_t reg_tt
, sindex
;
3858 reg_tt
= (reg_rt
+ rindex
) % 32;
3859 for (sindex
= 0; sindex
< selem
; sindex
++)
3861 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3862 record_buf
[reg_index
++] = reg_tt
+ AARCH64_V0_REGNUM
;
3865 record_buf_mem
[mem_index
++] = esize
/ 8;
3866 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3868 addr_offset
= addr_offset
+ (esize
/ 8);
3869 reg_tt
= (reg_tt
+ 1) % 32;
3874 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
3875 record_buf
[reg_index
++] = reg_rn
;
3877 aarch64_insn_r
->reg_rec_count
= reg_index
;
3878 aarch64_insn_r
->mem_rec_count
= mem_index
/ 2;
3879 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
3881 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3883 return AARCH64_RECORD_SUCCESS
;
3886 /* Record handler for load and store instructions. */
3889 aarch64_record_load_store (insn_decode_record
*aarch64_insn_r
)
3891 uint8_t insn_bits24_27
, insn_bits28_29
, insn_bits10_11
;
3892 uint8_t insn_bit23
, insn_bit21
;
3893 uint8_t opc
, size_bits
, ld_flag
, vector_flag
;
3894 uint32_t reg_rn
, reg_rt
, reg_rt2
;
3895 uint64_t datasize
, offset
;
3896 uint32_t record_buf
[8];
3897 uint64_t record_buf_mem
[8];
3900 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3901 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3902 insn_bits28_29
= bits (aarch64_insn_r
->aarch64_insn
, 28, 29);
3903 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
3904 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3905 ld_flag
= bit (aarch64_insn_r
->aarch64_insn
, 22);
3906 vector_flag
= bit (aarch64_insn_r
->aarch64_insn
, 26);
3907 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3908 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3909 reg_rt2
= bits (aarch64_insn_r
->aarch64_insn
, 10, 14);
3910 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 30, 31);
3912 /* Load/store exclusive. */
3913 if (insn_bits24_27
== 0x08 && insn_bits28_29
== 0x00)
3916 debug_printf ("Process record: load/store exclusive\n");
3920 record_buf
[0] = reg_rt
;
3921 aarch64_insn_r
->reg_rec_count
= 1;
3924 record_buf
[1] = reg_rt2
;
3925 aarch64_insn_r
->reg_rec_count
= 2;
3931 datasize
= (8 << size_bits
) * 2;
3933 datasize
= (8 << size_bits
);
3934 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3936 record_buf_mem
[0] = datasize
/ 8;
3937 record_buf_mem
[1] = address
;
3938 aarch64_insn_r
->mem_rec_count
= 1;
3941 /* Save register rs. */
3942 record_buf
[0] = bits (aarch64_insn_r
->aarch64_insn
, 16, 20);
3943 aarch64_insn_r
->reg_rec_count
= 1;
3947 /* Load register (literal) instructions decoding. */
3948 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x01)
3951 debug_printf ("Process record: load register (literal)\n");
3953 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3955 record_buf
[0] = reg_rt
;
3956 aarch64_insn_r
->reg_rec_count
= 1;
3958 /* All types of load/store pair instructions decoding. */
3959 else if ((insn_bits24_27
& 0x0a) == 0x08 && insn_bits28_29
== 0x02)
3962 debug_printf ("Process record: load/store pair\n");
3968 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3969 record_buf
[1] = reg_rt2
+ AARCH64_V0_REGNUM
;
3973 record_buf
[0] = reg_rt
;
3974 record_buf
[1] = reg_rt2
;
3976 aarch64_insn_r
->reg_rec_count
= 2;
3981 imm7_off
= bits (aarch64_insn_r
->aarch64_insn
, 15, 21);
3983 size_bits
= size_bits
>> 1;
3984 datasize
= 8 << (2 + size_bits
);
3985 offset
= (imm7_off
& 0x40) ? (~imm7_off
& 0x007f) + 1 : imm7_off
;
3986 offset
= offset
<< (2 + size_bits
);
3987 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3989 if (!((insn_bits24_27
& 0x0b) == 0x08 && insn_bit23
))
3991 if (imm7_off
& 0x40)
3992 address
= address
- offset
;
3994 address
= address
+ offset
;
3997 record_buf_mem
[0] = datasize
/ 8;
3998 record_buf_mem
[1] = address
;
3999 record_buf_mem
[2] = datasize
/ 8;
4000 record_buf_mem
[3] = address
+ (datasize
/ 8);
4001 aarch64_insn_r
->mem_rec_count
= 2;
4003 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
4004 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
4006 /* Load/store register (unsigned immediate) instructions. */
4007 else if ((insn_bits24_27
& 0x0b) == 0x09 && insn_bits28_29
== 0x03)
4009 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4019 if (size_bits
== 0x3 && vector_flag
== 0x0 && opc
== 0x2)
4021 /* PRFM (immediate) */
4022 return AARCH64_RECORD_SUCCESS
;
4024 else if (size_bits
== 0x2 && vector_flag
== 0x0 && opc
== 0x2)
4026 /* LDRSW (immediate) */
4040 debug_printf ("Process record: load/store (unsigned immediate):"
4041 " size %x V %d opc %x\n", size_bits
, vector_flag
,
4047 offset
= bits (aarch64_insn_r
->aarch64_insn
, 10, 21);
4048 datasize
= 8 << size_bits
;
4049 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4051 offset
= offset
<< size_bits
;
4052 address
= address
+ offset
;
4054 record_buf_mem
[0] = datasize
>> 3;
4055 record_buf_mem
[1] = address
;
4056 aarch64_insn_r
->mem_rec_count
= 1;
4061 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4063 record_buf
[0] = reg_rt
;
4064 aarch64_insn_r
->reg_rec_count
= 1;
4067 /* Load/store register (register offset) instructions. */
4068 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
4069 && insn_bits10_11
== 0x02 && insn_bit21
)
4072 debug_printf ("Process record: load/store (register offset)\n");
4073 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4080 if (size_bits
!= 0x03)
4083 return AARCH64_RECORD_UNKNOWN
;
4087 ULONGEST reg_rm_val
;
4089 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
,
4090 bits (aarch64_insn_r
->aarch64_insn
, 16, 20), ®_rm_val
);
4091 if (bit (aarch64_insn_r
->aarch64_insn
, 12))
4092 offset
= reg_rm_val
<< size_bits
;
4094 offset
= reg_rm_val
;
4095 datasize
= 8 << size_bits
;
4096 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4098 address
= address
+ offset
;
4099 record_buf_mem
[0] = datasize
>> 3;
4100 record_buf_mem
[1] = address
;
4101 aarch64_insn_r
->mem_rec_count
= 1;
4106 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4108 record_buf
[0] = reg_rt
;
4109 aarch64_insn_r
->reg_rec_count
= 1;
4112 /* Load/store register (immediate and unprivileged) instructions. */
4113 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
4118 debug_printf ("Process record: load/store "
4119 "(immediate and unprivileged)\n");
4121 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4128 if (size_bits
!= 0x03)
4131 return AARCH64_RECORD_UNKNOWN
;
4136 imm9_off
= bits (aarch64_insn_r
->aarch64_insn
, 12, 20);
4137 offset
= (imm9_off
& 0x0100) ? (((~imm9_off
) & 0x01ff) + 1) : imm9_off
;
4138 datasize
= 8 << size_bits
;
4139 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4141 if (insn_bits10_11
!= 0x01)
4143 if (imm9_off
& 0x0100)
4144 address
= address
- offset
;
4146 address
= address
+ offset
;
4148 record_buf_mem
[0] = datasize
>> 3;
4149 record_buf_mem
[1] = address
;
4150 aarch64_insn_r
->mem_rec_count
= 1;
4155 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4157 record_buf
[0] = reg_rt
;
4158 aarch64_insn_r
->reg_rec_count
= 1;
4160 if (insn_bits10_11
== 0x01 || insn_bits10_11
== 0x03)
4161 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
4163 /* Advanced SIMD load/store instructions. */
4165 return aarch64_record_asimd_load_store (aarch64_insn_r
);
4167 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
4169 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4171 return AARCH64_RECORD_SUCCESS
;
4174 /* Record handler for data processing SIMD and floating point instructions. */
4177 aarch64_record_data_proc_simd_fp (insn_decode_record
*aarch64_insn_r
)
4179 uint8_t insn_bit21
, opcode
, rmode
, reg_rd
;
4180 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits10_11
, insn_bits12_15
;
4181 uint8_t insn_bits11_14
;
4182 uint32_t record_buf
[2];
4184 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
4185 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
4186 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
4187 insn_bits12_15
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
4188 insn_bits11_14
= bits (aarch64_insn_r
->aarch64_insn
, 11, 14);
4189 opcode
= bits (aarch64_insn_r
->aarch64_insn
, 16, 18);
4190 rmode
= bits (aarch64_insn_r
->aarch64_insn
, 19, 20);
4191 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
4192 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
4195 debug_printf ("Process record: data processing SIMD/FP: ");
4197 if ((insn_bits28_31
& 0x05) == 0x01 && insn_bits24_27
== 0x0e)
4199 /* Floating point - fixed point conversion instructions. */
4203 debug_printf ("FP - fixed point conversion");
4205 if ((opcode
>> 1) == 0x0 && rmode
== 0x03)
4206 record_buf
[0] = reg_rd
;
4208 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4210 /* Floating point - conditional compare instructions. */
4211 else if (insn_bits10_11
== 0x01)
4214 debug_printf ("FP - conditional compare");
4216 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4218 /* Floating point - data processing (2-source) and
4219 conditional select instructions. */
4220 else if (insn_bits10_11
== 0x02 || insn_bits10_11
== 0x03)
4223 debug_printf ("FP - DP (2-source)");
4225 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4227 else if (insn_bits10_11
== 0x00)
4229 /* Floating point - immediate instructions. */
4230 if ((insn_bits12_15
& 0x01) == 0x01
4231 || (insn_bits12_15
& 0x07) == 0x04)
4234 debug_printf ("FP - immediate");
4235 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4237 /* Floating point - compare instructions. */
4238 else if ((insn_bits12_15
& 0x03) == 0x02)
4241 debug_printf ("FP - immediate");
4242 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4244 /* Floating point - integer conversions instructions. */
4245 else if (insn_bits12_15
== 0x00)
4247 /* Convert float to integer instruction. */
4248 if (!(opcode
>> 1) || ((opcode
>> 1) == 0x02 && !rmode
))
4251 debug_printf ("float to int conversion");
4253 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4255 /* Convert integer to float instruction. */
4256 else if ((opcode
>> 1) == 0x01 && !rmode
)
4259 debug_printf ("int to float conversion");
4261 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4263 /* Move float to integer instruction. */
4264 else if ((opcode
>> 1) == 0x03)
4267 debug_printf ("move float to int");
4269 if (!(opcode
& 0x01))
4270 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4272 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4275 return AARCH64_RECORD_UNKNOWN
;
4278 return AARCH64_RECORD_UNKNOWN
;
4281 return AARCH64_RECORD_UNKNOWN
;
4283 else if ((insn_bits28_31
& 0x09) == 0x00 && insn_bits24_27
== 0x0e)
4286 debug_printf ("SIMD copy");
4288 /* Advanced SIMD copy instructions. */
4289 if (!bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
4290 && !bit (aarch64_insn_r
->aarch64_insn
, 15)
4291 && bit (aarch64_insn_r
->aarch64_insn
, 10))
4293 if (insn_bits11_14
== 0x05 || insn_bits11_14
== 0x07)
4294 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4296 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4299 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4301 /* All remaining floating point or advanced SIMD instructions. */
4305 debug_printf ("all remain");
4307 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4311 debug_printf ("\n");
4313 aarch64_insn_r
->reg_rec_count
++;
4314 gdb_assert (aarch64_insn_r
->reg_rec_count
== 1);
4315 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4317 return AARCH64_RECORD_SUCCESS
;
4320 /* Decodes insns type and invokes its record handler. */
4323 aarch64_record_decode_insn_handler (insn_decode_record
*aarch64_insn_r
)
4325 uint32_t ins_bit25
, ins_bit26
, ins_bit27
, ins_bit28
;
4327 ins_bit25
= bit (aarch64_insn_r
->aarch64_insn
, 25);
4328 ins_bit26
= bit (aarch64_insn_r
->aarch64_insn
, 26);
4329 ins_bit27
= bit (aarch64_insn_r
->aarch64_insn
, 27);
4330 ins_bit28
= bit (aarch64_insn_r
->aarch64_insn
, 28);
4332 /* Data processing - immediate instructions. */
4333 if (!ins_bit26
&& !ins_bit27
&& ins_bit28
)
4334 return aarch64_record_data_proc_imm (aarch64_insn_r
);
4336 /* Branch, exception generation and system instructions. */
4337 if (ins_bit26
&& !ins_bit27
&& ins_bit28
)
4338 return aarch64_record_branch_except_sys (aarch64_insn_r
);
4340 /* Load and store instructions. */
4341 if (!ins_bit25
&& ins_bit27
)
4342 return aarch64_record_load_store (aarch64_insn_r
);
4344 /* Data processing - register instructions. */
4345 if (ins_bit25
&& !ins_bit26
&& ins_bit27
)
4346 return aarch64_record_data_proc_reg (aarch64_insn_r
);
4348 /* Data processing - SIMD and floating point instructions. */
4349 if (ins_bit25
&& ins_bit26
&& ins_bit27
)
4350 return aarch64_record_data_proc_simd_fp (aarch64_insn_r
);
4352 return AARCH64_RECORD_UNSUPPORTED
;
4355 /* Cleans up local record registers and memory allocations. */
4358 deallocate_reg_mem (insn_decode_record
*record
)
4360 xfree (record
->aarch64_regs
);
4361 xfree (record
->aarch64_mems
);
4365 namespace selftests
{
4368 aarch64_process_record_test (void)
4370 struct gdbarch_info info
;
4373 gdbarch_info_init (&info
);
4374 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
4376 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
4377 SELF_CHECK (gdbarch
!= NULL
);
4379 insn_decode_record aarch64_record
;
4381 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4382 aarch64_record
.regcache
= NULL
;
4383 aarch64_record
.this_addr
= 0;
4384 aarch64_record
.gdbarch
= gdbarch
;
4386 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4387 aarch64_record
.aarch64_insn
= 0xf9800020;
4388 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4389 SELF_CHECK (ret
== AARCH64_RECORD_SUCCESS
);
4390 SELF_CHECK (aarch64_record
.reg_rec_count
== 0);
4391 SELF_CHECK (aarch64_record
.mem_rec_count
== 0);
4393 deallocate_reg_mem (&aarch64_record
);
4396 } // namespace selftests
4397 #endif /* GDB_SELF_TEST */
4399 /* Parse the current instruction and record the values of the registers and
4400 memory that will be changed in current instruction to record_arch_list
4401 return -1 if something is wrong. */
4404 aarch64_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4405 CORE_ADDR insn_addr
)
4407 uint32_t rec_no
= 0;
4408 uint8_t insn_size
= 4;
4410 gdb_byte buf
[insn_size
];
4411 insn_decode_record aarch64_record
;
4413 memset (&buf
[0], 0, insn_size
);
4414 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4415 target_read_memory (insn_addr
, &buf
[0], insn_size
);
4416 aarch64_record
.aarch64_insn
4417 = (uint32_t) extract_unsigned_integer (&buf
[0],
4419 gdbarch_byte_order (gdbarch
));
4420 aarch64_record
.regcache
= regcache
;
4421 aarch64_record
.this_addr
= insn_addr
;
4422 aarch64_record
.gdbarch
= gdbarch
;
4424 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4425 if (ret
== AARCH64_RECORD_UNSUPPORTED
)
4427 printf_unfiltered (_("Process record does not support instruction "
4428 "0x%0x at address %s.\n"),
4429 aarch64_record
.aarch64_insn
,
4430 paddress (gdbarch
, insn_addr
));
4436 /* Record registers. */
4437 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4439 /* Always record register CPSR. */
4440 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4441 AARCH64_CPSR_REGNUM
);
4442 if (aarch64_record
.aarch64_regs
)
4443 for (rec_no
= 0; rec_no
< aarch64_record
.reg_rec_count
; rec_no
++)
4444 if (record_full_arch_list_add_reg (aarch64_record
.regcache
,
4445 aarch64_record
.aarch64_regs
[rec_no
]))
4448 /* Record memories. */
4449 if (aarch64_record
.aarch64_mems
)
4450 for (rec_no
= 0; rec_no
< aarch64_record
.mem_rec_count
; rec_no
++)
4451 if (record_full_arch_list_add_mem
4452 ((CORE_ADDR
)aarch64_record
.aarch64_mems
[rec_no
].addr
,
4453 aarch64_record
.aarch64_mems
[rec_no
].len
))
4456 if (record_full_arch_list_add_end ())
4460 deallocate_reg_mem (&aarch64_record
);