1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2014 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 #include "reggroups.h"
33 #include "arch-utils.h"
35 #include "frame-unwind.h"
36 #include "frame-base.h"
37 #include "trad-frame.h"
39 #include "dwarf2-frame.h"
41 #include "prologue-value.h"
42 #include "target-descriptions.h"
43 #include "user-regs.h"
47 #include "aarch64-tdep.h"
50 #include "elf/aarch64.h"
54 #include "features/aarch64.c"
56 /* Pseudo register base numbers. */
57 #define AARCH64_Q0_REGNUM 0
58 #define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + 32)
59 #define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32)
60 #define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
61 #define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
63 /* The standard register names, and all the valid aliases for them. */
66 const char *const name
;
68 } aarch64_register_aliases
[] =
70 /* 64-bit register names. */
71 {"fp", AARCH64_FP_REGNUM
},
72 {"lr", AARCH64_LR_REGNUM
},
73 {"sp", AARCH64_SP_REGNUM
},
75 /* 32-bit register names. */
76 {"w0", AARCH64_X0_REGNUM
+ 0},
77 {"w1", AARCH64_X0_REGNUM
+ 1},
78 {"w2", AARCH64_X0_REGNUM
+ 2},
79 {"w3", AARCH64_X0_REGNUM
+ 3},
80 {"w4", AARCH64_X0_REGNUM
+ 4},
81 {"w5", AARCH64_X0_REGNUM
+ 5},
82 {"w6", AARCH64_X0_REGNUM
+ 6},
83 {"w7", AARCH64_X0_REGNUM
+ 7},
84 {"w8", AARCH64_X0_REGNUM
+ 8},
85 {"w9", AARCH64_X0_REGNUM
+ 9},
86 {"w10", AARCH64_X0_REGNUM
+ 10},
87 {"w11", AARCH64_X0_REGNUM
+ 11},
88 {"w12", AARCH64_X0_REGNUM
+ 12},
89 {"w13", AARCH64_X0_REGNUM
+ 13},
90 {"w14", AARCH64_X0_REGNUM
+ 14},
91 {"w15", AARCH64_X0_REGNUM
+ 15},
92 {"w16", AARCH64_X0_REGNUM
+ 16},
93 {"w17", AARCH64_X0_REGNUM
+ 17},
94 {"w18", AARCH64_X0_REGNUM
+ 18},
95 {"w19", AARCH64_X0_REGNUM
+ 19},
96 {"w20", AARCH64_X0_REGNUM
+ 20},
97 {"w21", AARCH64_X0_REGNUM
+ 21},
98 {"w22", AARCH64_X0_REGNUM
+ 22},
99 {"w23", AARCH64_X0_REGNUM
+ 23},
100 {"w24", AARCH64_X0_REGNUM
+ 24},
101 {"w25", AARCH64_X0_REGNUM
+ 25},
102 {"w26", AARCH64_X0_REGNUM
+ 26},
103 {"w27", AARCH64_X0_REGNUM
+ 27},
104 {"w28", AARCH64_X0_REGNUM
+ 28},
105 {"w29", AARCH64_X0_REGNUM
+ 29},
106 {"w30", AARCH64_X0_REGNUM
+ 30},
109 {"ip0", AARCH64_X0_REGNUM
+ 16},
110 {"ip1", AARCH64_X0_REGNUM
+ 17}
113 /* The required core 'R' registers. */
114 static const char *const aarch64_r_register_names
[] =
116 /* These registers must appear in consecutive RAW register number
117 order and they must begin with AARCH64_X0_REGNUM! */
118 "x0", "x1", "x2", "x3",
119 "x4", "x5", "x6", "x7",
120 "x8", "x9", "x10", "x11",
121 "x12", "x13", "x14", "x15",
122 "x16", "x17", "x18", "x19",
123 "x20", "x21", "x22", "x23",
124 "x24", "x25", "x26", "x27",
125 "x28", "x29", "x30", "sp",
129 /* The FP/SIMD 'V' registers. */
130 static const char *const aarch64_v_register_names
[] =
132 /* These registers must appear in consecutive RAW register number
133 order and they must begin with AARCH64_V0_REGNUM! */
134 "v0", "v1", "v2", "v3",
135 "v4", "v5", "v6", "v7",
136 "v8", "v9", "v10", "v11",
137 "v12", "v13", "v14", "v15",
138 "v16", "v17", "v18", "v19",
139 "v20", "v21", "v22", "v23",
140 "v24", "v25", "v26", "v27",
141 "v28", "v29", "v30", "v31",
146 /* AArch64 prologue cache structure. */
147 struct aarch64_prologue_cache
149 /* The stack pointer at the time this frame was created; i.e. the
150 caller's stack pointer when this function was called. It is used
151 to identify this frame. */
154 /* The frame base for this frame is just prev_sp - frame size.
155 FRAMESIZE is the distance from the frame pointer to the
156 initial stack pointer. */
159 /* The register used to hold the frame pointer for this frame. */
162 /* Saved register offsets. */
163 struct trad_frame_saved_reg
*saved_regs
;
166 /* Toggle this file's internal debugging dump. */
167 static int aarch64_debug
;
170 show_aarch64_debug (struct ui_file
*file
, int from_tty
,
171 struct cmd_list_element
*c
, const char *value
)
173 fprintf_filtered (file
, _("AArch64 debugging is %s.\n"), value
);
176 /* Extract a signed value from a bit field within an instruction
179 INSN is the instruction opcode.
181 WIDTH specifies the width of the bit field to extract (in bits).
183 OFFSET specifies the least significant bit of the field where bits
184 are numbered zero counting from least to most significant. */
187 extract_signed_bitfield (uint32_t insn
, unsigned width
, unsigned offset
)
189 unsigned shift_l
= sizeof (int32_t) * 8 - (offset
+ width
);
190 unsigned shift_r
= sizeof (int32_t) * 8 - width
;
192 return ((int32_t) insn
<< shift_l
) >> shift_r
;
195 /* Determine if specified bits within an instruction opcode matches a
198 INSN is the instruction opcode.
200 MASK specifies the bits within the opcode that are to be tested
201 agsinst for a match with PATTERN. */
204 decode_masked_match (uint32_t insn
, uint32_t mask
, uint32_t pattern
)
206 return (insn
& mask
) == pattern
;
209 /* Decode an opcode if it represents an immediate ADD or SUB instruction.
211 ADDR specifies the address of the opcode.
212 INSN specifies the opcode to test.
213 RD receives the 'rd' field from the decoded instruction.
214 RN receives the 'rn' field from the decoded instruction.
216 Return 1 if the opcodes matches and is decoded, otherwise 0. */
218 decode_add_sub_imm (CORE_ADDR addr
, uint32_t insn
, unsigned *rd
, unsigned *rn
,
221 if ((insn
& 0x9f000000) == 0x91000000)
226 *rd
= (insn
>> 0) & 0x1f;
227 *rn
= (insn
>> 5) & 0x1f;
228 *imm
= (insn
>> 10) & 0xfff;
229 shift
= (insn
>> 22) & 0x3;
230 op_is_sub
= (insn
>> 30) & 0x1;
248 fprintf_unfiltered (gdb_stdlog
,
249 "decode: 0x%s 0x%x add x%u, x%u, #%d\n",
250 core_addr_to_string_nz (addr
), insn
, *rd
, *rn
,
257 /* Decode an opcode if it represents an ADRP instruction.
259 ADDR specifies the address of the opcode.
260 INSN specifies the opcode to test.
261 RD receives the 'rd' field from the decoded instruction.
263 Return 1 if the opcodes matches and is decoded, otherwise 0. */
266 decode_adrp (CORE_ADDR addr
, uint32_t insn
, unsigned *rd
)
268 if (decode_masked_match (insn
, 0x9f000000, 0x90000000))
270 *rd
= (insn
>> 0) & 0x1f;
273 fprintf_unfiltered (gdb_stdlog
,
274 "decode: 0x%s 0x%x adrp x%u, #?\n",
275 core_addr_to_string_nz (addr
), insn
, *rd
);
281 /* Decode an opcode if it represents an branch immediate or branch
282 and link immediate instruction.
284 ADDR specifies the address of the opcode.
285 INSN specifies the opcode to test.
286 LINK receives the 'link' bit from the decoded instruction.
287 OFFSET receives the immediate offset from the decoded instruction.
289 Return 1 if the opcodes matches and is decoded, otherwise 0. */
292 decode_b (CORE_ADDR addr
, uint32_t insn
, unsigned *link
, int32_t *offset
)
294 /* b 0001 01ii iiii iiii iiii iiii iiii iiii */
295 /* bl 1001 01ii iiii iiii iiii iiii iiii iiii */
296 if (decode_masked_match (insn
, 0x7c000000, 0x14000000))
299 *offset
= extract_signed_bitfield (insn
, 26, 0) << 2;
302 fprintf_unfiltered (gdb_stdlog
,
303 "decode: 0x%s 0x%x %s 0x%s\n",
304 core_addr_to_string_nz (addr
), insn
,
306 core_addr_to_string_nz (addr
+ *offset
));
313 /* Decode an opcode if it represents a conditional branch instruction.
315 ADDR specifies the address of the opcode.
316 INSN specifies the opcode to test.
317 COND receives the branch condition field from the decoded
319 OFFSET receives the immediate offset from the decoded instruction.
321 Return 1 if the opcodes matches and is decoded, otherwise 0. */
324 decode_bcond (CORE_ADDR addr
, uint32_t insn
, unsigned *cond
, int32_t *offset
)
326 if (decode_masked_match (insn
, 0xfe000000, 0x54000000))
328 *cond
= (insn
>> 0) & 0xf;
329 *offset
= extract_signed_bitfield (insn
, 19, 5) << 2;
332 fprintf_unfiltered (gdb_stdlog
,
333 "decode: 0x%s 0x%x b<%u> 0x%s\n",
334 core_addr_to_string_nz (addr
), insn
, *cond
,
335 core_addr_to_string_nz (addr
+ *offset
));
341 /* Decode an opcode if it represents a branch via register instruction.
343 ADDR specifies the address of the opcode.
344 INSN specifies the opcode to test.
345 LINK receives the 'link' bit from the decoded instruction.
346 RN receives the 'rn' field from the decoded instruction.
348 Return 1 if the opcodes matches and is decoded, otherwise 0. */
351 decode_br (CORE_ADDR addr
, uint32_t insn
, unsigned *link
, unsigned *rn
)
353 /* 8 4 0 6 2 8 4 0 */
354 /* blr 110101100011111100000000000rrrrr */
355 /* br 110101100001111100000000000rrrrr */
356 if (decode_masked_match (insn
, 0xffdffc1f, 0xd61f0000))
358 *link
= (insn
>> 21) & 1;
359 *rn
= (insn
>> 5) & 0x1f;
362 fprintf_unfiltered (gdb_stdlog
,
363 "decode: 0x%s 0x%x %s 0x%x\n",
364 core_addr_to_string_nz (addr
), insn
,
365 *link
? "blr" : "br", *rn
);
372 /* Decode an opcode if it represents a CBZ or CBNZ instruction.
374 ADDR specifies the address of the opcode.
375 INSN specifies the opcode to test.
376 IS64 receives the 'sf' field from the decoded instruction.
377 OP receives the 'op' field from the decoded instruction.
378 RN receives the 'rn' field from the decoded instruction.
379 OFFSET receives the 'imm19' field from the decoded instruction.
381 Return 1 if the opcodes matches and is decoded, otherwise 0. */
384 decode_cb (CORE_ADDR addr
,
385 uint32_t insn
, int *is64
, unsigned *op
, unsigned *rn
,
388 if (decode_masked_match (insn
, 0x7e000000, 0x34000000))
390 /* cbz T011 010o iiii iiii iiii iiii iiir rrrr */
391 /* cbnz T011 010o iiii iiii iiii iiii iiir rrrr */
393 *rn
= (insn
>> 0) & 0x1f;
394 *is64
= (insn
>> 31) & 0x1;
395 *op
= (insn
>> 24) & 0x1;
396 *offset
= extract_signed_bitfield (insn
, 19, 5) << 2;
399 fprintf_unfiltered (gdb_stdlog
,
400 "decode: 0x%s 0x%x %s 0x%s\n",
401 core_addr_to_string_nz (addr
), insn
,
402 *op
? "cbnz" : "cbz",
403 core_addr_to_string_nz (addr
+ *offset
));
409 /* Decode an opcode if it represents a ERET instruction.
411 ADDR specifies the address of the opcode.
412 INSN specifies the opcode to test.
414 Return 1 if the opcodes matches and is decoded, otherwise 0. */
417 decode_eret (CORE_ADDR addr
, uint32_t insn
)
419 /* eret 1101 0110 1001 1111 0000 0011 1110 0000 */
420 if (insn
== 0xd69f03e0)
423 fprintf_unfiltered (gdb_stdlog
, "decode: 0x%s 0x%x eret\n",
424 core_addr_to_string_nz (addr
), insn
);
430 /* Decode an opcode if it represents a MOVZ instruction.
432 ADDR specifies the address of the opcode.
433 INSN specifies the opcode to test.
434 RD receives the 'rd' field from the decoded instruction.
436 Return 1 if the opcodes matches and is decoded, otherwise 0. */
439 decode_movz (CORE_ADDR addr
, uint32_t insn
, unsigned *rd
)
441 if (decode_masked_match (insn
, 0xff800000, 0x52800000))
443 *rd
= (insn
>> 0) & 0x1f;
446 fprintf_unfiltered (gdb_stdlog
,
447 "decode: 0x%s 0x%x movz x%u, #?\n",
448 core_addr_to_string_nz (addr
), insn
, *rd
);
454 /* Decode an opcode if it represents a ORR (shifted register)
457 ADDR specifies the address of the opcode.
458 INSN specifies the opcode to test.
459 RD receives the 'rd' field from the decoded instruction.
460 RN receives the 'rn' field from the decoded instruction.
461 RM receives the 'rm' field from the decoded instruction.
462 IMM receives the 'imm6' field from the decoded instruction.
464 Return 1 if the opcodes matches and is decoded, otherwise 0. */
467 decode_orr_shifted_register_x (CORE_ADDR addr
,
468 uint32_t insn
, unsigned *rd
, unsigned *rn
,
469 unsigned *rm
, int32_t *imm
)
471 if (decode_masked_match (insn
, 0xff200000, 0xaa000000))
473 *rd
= (insn
>> 0) & 0x1f;
474 *rn
= (insn
>> 5) & 0x1f;
475 *rm
= (insn
>> 16) & 0x1f;
476 *imm
= (insn
>> 10) & 0x3f;
479 fprintf_unfiltered (gdb_stdlog
,
480 "decode: 0x%s 0x%x orr x%u, x%u, x%u, #%u\n",
481 core_addr_to_string_nz (addr
), insn
, *rd
,
488 /* Decode an opcode if it represents a RET instruction.
490 ADDR specifies the address of the opcode.
491 INSN specifies the opcode to test.
492 RN receives the 'rn' field from the decoded instruction.
494 Return 1 if the opcodes matches and is decoded, otherwise 0. */
497 decode_ret (CORE_ADDR addr
, uint32_t insn
, unsigned *rn
)
499 if (decode_masked_match (insn
, 0xfffffc1f, 0xd65f0000))
501 *rn
= (insn
>> 5) & 0x1f;
503 fprintf_unfiltered (gdb_stdlog
,
504 "decode: 0x%s 0x%x ret x%u\n",
505 core_addr_to_string_nz (addr
), insn
, *rn
);
511 /* Decode an opcode if it represents the following instruction:
512 STP rt, rt2, [rn, #imm]
514 ADDR specifies the address of the opcode.
515 INSN specifies the opcode to test.
516 RT1 receives the 'rt' field from the decoded instruction.
517 RT2 receives the 'rt2' field from the decoded instruction.
518 RN receives the 'rn' field from the decoded instruction.
519 IMM receives the 'imm' field from the decoded instruction.
521 Return 1 if the opcodes matches and is decoded, otherwise 0. */
524 decode_stp_offset (CORE_ADDR addr
,
526 unsigned *rt1
, unsigned *rt2
, unsigned *rn
, int32_t *imm
)
528 if (decode_masked_match (insn
, 0xffc00000, 0xa9000000))
530 *rt1
= (insn
>> 0) & 0x1f;
531 *rn
= (insn
>> 5) & 0x1f;
532 *rt2
= (insn
>> 10) & 0x1f;
533 *imm
= extract_signed_bitfield (insn
, 7, 15);
537 fprintf_unfiltered (gdb_stdlog
,
538 "decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]\n",
539 core_addr_to_string_nz (addr
), insn
,
540 *rt1
, *rt2
, *rn
, *imm
);
546 /* Decode an opcode if it represents the following instruction:
547 STP rt, rt2, [rn, #imm]!
549 ADDR specifies the address of the opcode.
550 INSN specifies the opcode to test.
551 RT1 receives the 'rt' field from the decoded instruction.
552 RT2 receives the 'rt2' field from the decoded instruction.
553 RN receives the 'rn' field from the decoded instruction.
554 IMM receives the 'imm' field from the decoded instruction.
556 Return 1 if the opcodes matches and is decoded, otherwise 0. */
559 decode_stp_offset_wb (CORE_ADDR addr
,
561 unsigned *rt1
, unsigned *rt2
, unsigned *rn
,
564 if (decode_masked_match (insn
, 0xffc00000, 0xa9800000))
566 *rt1
= (insn
>> 0) & 0x1f;
567 *rn
= (insn
>> 5) & 0x1f;
568 *rt2
= (insn
>> 10) & 0x1f;
569 *imm
= extract_signed_bitfield (insn
, 7, 15);
573 fprintf_unfiltered (gdb_stdlog
,
574 "decode: 0x%s 0x%x stp x%u, x%u, [x%u + #%d]!\n",
575 core_addr_to_string_nz (addr
), insn
,
576 *rt1
, *rt2
, *rn
, *imm
);
582 /* Decode an opcode if it represents the following instruction:
585 ADDR specifies the address of the opcode.
586 INSN specifies the opcode to test.
587 IS64 receives size field from the decoded instruction.
588 RT receives the 'rt' field from the decoded instruction.
589 RN receives the 'rn' field from the decoded instruction.
590 IMM receives the 'imm' field from the decoded instruction.
592 Return 1 if the opcodes matches and is decoded, otherwise 0. */
595 decode_stur (CORE_ADDR addr
, uint32_t insn
, int *is64
, unsigned *rt
,
596 unsigned *rn
, int32_t *imm
)
598 if (decode_masked_match (insn
, 0xbfe00c00, 0xb8000000))
600 *is64
= (insn
>> 30) & 1;
601 *rt
= (insn
>> 0) & 0x1f;
602 *rn
= (insn
>> 5) & 0x1f;
603 *imm
= extract_signed_bitfield (insn
, 9, 12);
606 fprintf_unfiltered (gdb_stdlog
,
607 "decode: 0x%s 0x%x stur %c%u, [x%u + #%d]\n",
608 core_addr_to_string_nz (addr
), insn
,
609 *is64
? 'x' : 'w', *rt
, *rn
, *imm
);
615 /* Decode an opcode if it represents a TB or TBNZ instruction.
617 ADDR specifies the address of the opcode.
618 INSN specifies the opcode to test.
619 OP receives the 'op' field from the decoded instruction.
620 BIT receives the bit position field from the decoded instruction.
621 RT receives 'rt' field from the decoded instruction.
622 IMM receives 'imm' field from the decoded instruction.
624 Return 1 if the opcodes matches and is decoded, otherwise 0. */
627 decode_tb (CORE_ADDR addr
,
628 uint32_t insn
, unsigned *op
, unsigned *bit
, unsigned *rt
,
631 if (decode_masked_match (insn
, 0x7e000000, 0x36000000))
633 /* tbz b011 0110 bbbb biii iiii iiii iiir rrrr */
634 /* tbnz B011 0111 bbbb biii iiii iiii iiir rrrr */
636 *rt
= (insn
>> 0) & 0x1f;
637 *op
= insn
& (1 << 24);
638 *bit
= ((insn
>> (31 - 4)) & 0x20) | ((insn
>> 19) & 0x1f);
639 *imm
= extract_signed_bitfield (insn
, 14, 5) << 2;
642 fprintf_unfiltered (gdb_stdlog
,
643 "decode: 0x%s 0x%x %s x%u, #%u, 0x%s\n",
644 core_addr_to_string_nz (addr
), insn
,
645 *op
? "tbnz" : "tbz", *rt
, *bit
,
646 core_addr_to_string_nz (addr
+ *imm
));
652 /* Analyze a prologue, looking for a recognizable stack frame
653 and frame pointer. Scan until we encounter a store that could
654 clobber the stack frame unexpectedly, or an unknown instruction. */
657 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
658 CORE_ADDR start
, CORE_ADDR limit
,
659 struct aarch64_prologue_cache
*cache
)
661 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
663 pv_t regs
[AARCH64_X_REGISTER_COUNT
];
664 struct pv_area
*stack
;
665 struct cleanup
*back_to
;
667 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
668 regs
[i
] = pv_register (i
, 0);
669 stack
= make_pv_area (AARCH64_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
670 back_to
= make_cleanup_free_pv_area (stack
);
672 for (; start
< limit
; start
+= 4)
690 insn
= read_memory_unsigned_integer (start
, 4, byte_order_for_code
);
692 if (decode_add_sub_imm (start
, insn
, &rd
, &rn
, &imm
))
693 regs
[rd
] = pv_add_constant (regs
[rn
], imm
);
694 else if (decode_adrp (start
, insn
, &rd
))
695 regs
[rd
] = pv_unknown ();
696 else if (decode_b (start
, insn
, &is_link
, &offset
))
698 /* Stop analysis on branch. */
701 else if (decode_bcond (start
, insn
, &cond
, &offset
))
703 /* Stop analysis on branch. */
706 else if (decode_br (start
, insn
, &is_link
, &rn
))
708 /* Stop analysis on branch. */
711 else if (decode_cb (start
, insn
, &is64
, &op
, &rn
, &offset
))
713 /* Stop analysis on branch. */
716 else if (decode_eret (start
, insn
))
718 /* Stop analysis on branch. */
721 else if (decode_movz (start
, insn
, &rd
))
722 regs
[rd
] = pv_unknown ();
724 if (decode_orr_shifted_register_x (start
, insn
, &rd
, &rn
, &rm
, &imm
))
726 if (imm
== 0 && rn
== 31)
733 "aarch64: prologue analysis gave up addr=0x%s "
734 "opcode=0x%x (orr x register)\n",
735 core_addr_to_string_nz (start
),
740 else if (decode_ret (start
, insn
, &rn
))
742 /* Stop analysis on branch. */
745 else if (decode_stur (start
, insn
, &is64
, &rt
, &rn
, &offset
))
747 pv_area_store (stack
, pv_add_constant (regs
[rn
], offset
),
748 is64
? 8 : 4, regs
[rt
]);
750 else if (decode_stp_offset (start
, insn
, &rt1
, &rt2
, &rn
, &imm
))
752 /* If recording this store would invalidate the store area
753 (perhaps because rn is not known) then we should abandon
754 further prologue analysis. */
755 if (pv_area_store_would_trash (stack
,
756 pv_add_constant (regs
[rn
], imm
)))
759 if (pv_area_store_would_trash (stack
,
760 pv_add_constant (regs
[rn
], imm
+ 8)))
763 pv_area_store (stack
, pv_add_constant (regs
[rn
], imm
), 8,
765 pv_area_store (stack
, pv_add_constant (regs
[rn
], imm
+ 8), 8,
768 else if (decode_stp_offset_wb (start
, insn
, &rt1
, &rt2
, &rn
, &imm
))
770 /* If recording this store would invalidate the store area
771 (perhaps because rn is not known) then we should abandon
772 further prologue analysis. */
773 if (pv_area_store_would_trash (stack
,
774 pv_add_constant (regs
[rn
], imm
)))
777 if (pv_area_store_would_trash (stack
,
778 pv_add_constant (regs
[rn
], imm
+ 8)))
781 pv_area_store (stack
, pv_add_constant (regs
[rn
], imm
), 8,
783 pv_area_store (stack
, pv_add_constant (regs
[rn
], imm
+ 8), 8,
785 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
787 else if (decode_tb (start
, insn
, &op
, &bit
, &rn
, &offset
))
789 /* Stop analysis on branch. */
795 fprintf_unfiltered (gdb_stdlog
,
796 "aarch64: prologue analysis gave up addr=0x%s"
798 core_addr_to_string_nz (start
), insn
);
805 do_cleanups (back_to
);
809 if (pv_is_register (regs
[AARCH64_FP_REGNUM
], AARCH64_SP_REGNUM
))
811 /* Frame pointer is fp. Frame size is constant. */
812 cache
->framereg
= AARCH64_FP_REGNUM
;
813 cache
->framesize
= -regs
[AARCH64_FP_REGNUM
].k
;
815 else if (pv_is_register (regs
[AARCH64_SP_REGNUM
], AARCH64_SP_REGNUM
))
817 /* Try the stack pointer. */
818 cache
->framesize
= -regs
[AARCH64_SP_REGNUM
].k
;
819 cache
->framereg
= AARCH64_SP_REGNUM
;
823 /* We're just out of luck. We don't know where the frame is. */
824 cache
->framereg
= -1;
825 cache
->framesize
= 0;
828 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
832 if (pv_area_find_reg (stack
, gdbarch
, i
, &offset
))
833 cache
->saved_regs
[i
].addr
= offset
;
836 do_cleanups (back_to
);
840 /* Implement the "skip_prologue" gdbarch method. */
843 aarch64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
847 CORE_ADDR func_addr
, limit_pc
;
848 struct symtab_and_line sal
;
850 /* See if we can determine the end of the prologue via the symbol
851 table. If so, then return either PC, or the PC after the
852 prologue, whichever is greater. */
853 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
855 CORE_ADDR post_prologue_pc
856 = skip_prologue_using_sal (gdbarch
, func_addr
);
858 if (post_prologue_pc
!= 0)
859 return max (pc
, post_prologue_pc
);
862 /* Can't determine prologue from the symbol table, need to examine
865 /* Find an upper limit on the function prologue using the debug
866 information. If the debug information could not be used to
867 provide that bound, then use an arbitrary large number as the
869 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
871 limit_pc
= pc
+ 128; /* Magic. */
873 /* Try disassembling prologue. */
874 return aarch64_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
877 /* Scan the function prologue for THIS_FRAME and populate the prologue
881 aarch64_scan_prologue (struct frame_info
*this_frame
,
882 struct aarch64_prologue_cache
*cache
)
884 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
885 CORE_ADDR prologue_start
;
886 CORE_ADDR prologue_end
;
887 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
888 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
890 /* Assume we do not find a frame. */
891 cache
->framereg
= -1;
892 cache
->framesize
= 0;
894 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
897 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
901 /* No line info so use the current PC. */
902 prologue_end
= prev_pc
;
904 else if (sal
.end
< prologue_end
)
906 /* The next line begins after the function end. */
907 prologue_end
= sal
.end
;
910 prologue_end
= min (prologue_end
, prev_pc
);
911 aarch64_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
918 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
920 frame_loc
= get_frame_register_unsigned (this_frame
, AARCH64_FP_REGNUM
);
924 cache
->framereg
= AARCH64_FP_REGNUM
;
925 cache
->framesize
= 16;
926 cache
->saved_regs
[29].addr
= 0;
927 cache
->saved_regs
[30].addr
= 8;
931 /* Allocate an aarch64_prologue_cache and fill it with information
932 about the prologue of *THIS_FRAME. */
934 static struct aarch64_prologue_cache
*
935 aarch64_make_prologue_cache (struct frame_info
*this_frame
)
937 struct aarch64_prologue_cache
*cache
;
938 CORE_ADDR unwound_fp
;
941 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
942 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
944 aarch64_scan_prologue (this_frame
, cache
);
946 if (cache
->framereg
== -1)
949 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
953 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
955 /* Calculate actual addresses of saved registers using offsets
956 determined by aarch64_analyze_prologue. */
957 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
958 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
959 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
964 /* Our frame ID for a normal frame is the current function's starting
965 PC and the caller's SP when we were called. */
968 aarch64_prologue_this_id (struct frame_info
*this_frame
,
969 void **this_cache
, struct frame_id
*this_id
)
971 struct aarch64_prologue_cache
*cache
;
975 if (*this_cache
== NULL
)
976 *this_cache
= aarch64_make_prologue_cache (this_frame
);
979 /* This is meant to halt the backtrace at "_start". */
980 pc
= get_frame_pc (this_frame
);
981 if (pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
984 /* If we've hit a wall, stop. */
985 if (cache
->prev_sp
== 0)
988 func
= get_frame_func (this_frame
);
989 id
= frame_id_build (cache
->prev_sp
, func
);
993 /* Implement the "prev_register" frame_unwind method. */
995 static struct value
*
996 aarch64_prologue_prev_register (struct frame_info
*this_frame
,
997 void **this_cache
, int prev_regnum
)
999 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1000 struct aarch64_prologue_cache
*cache
;
1002 if (*this_cache
== NULL
)
1003 *this_cache
= aarch64_make_prologue_cache (this_frame
);
1004 cache
= *this_cache
;
1006 /* If we are asked to unwind the PC, then we need to return the LR
1007 instead. The prologue may save PC, but it will point into this
1008 frame's prologue, not the next frame's resume location. */
1009 if (prev_regnum
== AARCH64_PC_REGNUM
)
1013 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
1014 return frame_unwind_got_constant (this_frame
, prev_regnum
, lr
);
1017 /* SP is generally not saved to the stack, but this frame is
1018 identified by the next frame's stack pointer at the time of the
1019 call. The value was already reconstructed into PREV_SP. */
1025 | | | <- Previous SP
1028 +--| saved fp |<- FP
1032 if (prev_regnum
== AARCH64_SP_REGNUM
)
1033 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1036 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1040 /* AArch64 prologue unwinder. */
1041 struct frame_unwind aarch64_prologue_unwind
=
1044 default_frame_unwind_stop_reason
,
1045 aarch64_prologue_this_id
,
1046 aarch64_prologue_prev_register
,
1048 default_frame_sniffer
1051 /* Allocate an aarch64_prologue_cache and fill it with information
1052 about the prologue of *THIS_FRAME. */
1054 static struct aarch64_prologue_cache
*
1055 aarch64_make_stub_cache (struct frame_info
*this_frame
)
1058 struct aarch64_prologue_cache
*cache
;
1059 CORE_ADDR unwound_fp
;
1061 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
1062 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1065 = get_frame_register_unsigned (this_frame
, AARCH64_SP_REGNUM
);
1070 /* Our frame ID for a stub frame is the current SP and LR. */
1073 aarch64_stub_this_id (struct frame_info
*this_frame
,
1074 void **this_cache
, struct frame_id
*this_id
)
1076 struct aarch64_prologue_cache
*cache
;
1078 if (*this_cache
== NULL
)
1079 *this_cache
= aarch64_make_stub_cache (this_frame
);
1080 cache
= *this_cache
;
1082 *this_id
= frame_id_build (cache
->prev_sp
, get_frame_pc (this_frame
));
1085 /* Implement the "sniffer" frame_unwind method. */
1088 aarch64_stub_unwind_sniffer (const struct frame_unwind
*self
,
1089 struct frame_info
*this_frame
,
1090 void **this_prologue_cache
)
1092 CORE_ADDR addr_in_block
;
1095 addr_in_block
= get_frame_address_in_block (this_frame
);
1096 if (in_plt_section (addr_in_block
)
1097 /* We also use the stub winder if the target memory is unreadable
1098 to avoid having the prologue unwinder trying to read it. */
1099 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1105 /* AArch64 stub unwinder. */
1106 struct frame_unwind aarch64_stub_unwind
=
1109 default_frame_unwind_stop_reason
,
1110 aarch64_stub_this_id
,
1111 aarch64_prologue_prev_register
,
1113 aarch64_stub_unwind_sniffer
1116 /* Return the frame base address of *THIS_FRAME. */
1119 aarch64_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1121 struct aarch64_prologue_cache
*cache
;
1123 if (*this_cache
== NULL
)
1124 *this_cache
= aarch64_make_prologue_cache (this_frame
);
1125 cache
= *this_cache
;
1127 return cache
->prev_sp
- cache
->framesize
;
1130 /* AArch64 default frame base information. */
1131 struct frame_base aarch64_normal_base
=
1133 &aarch64_prologue_unwind
,
1134 aarch64_normal_frame_base
,
1135 aarch64_normal_frame_base
,
1136 aarch64_normal_frame_base
1139 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1140 dummy frame. The frame ID's base needs to match the TOS value
1141 saved by save_dummy_frame_tos () and returned from
1142 aarch64_push_dummy_call, and the PC needs to match the dummy
1143 frame's breakpoint. */
1145 static struct frame_id
1146 aarch64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1148 return frame_id_build (get_frame_register_unsigned (this_frame
,
1150 get_frame_pc (this_frame
));
1153 /* Implement the "unwind_pc" gdbarch method. */
1156 aarch64_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1159 = frame_unwind_register_unsigned (this_frame
, AARCH64_PC_REGNUM
);
1164 /* Implement the "unwind_sp" gdbarch method. */
1167 aarch64_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1169 return frame_unwind_register_unsigned (this_frame
, AARCH64_SP_REGNUM
);
1172 /* Return the value of the REGNUM register in the previous frame of
1175 static struct value
*
1176 aarch64_dwarf2_prev_register (struct frame_info
*this_frame
,
1177 void **this_cache
, int regnum
)
1179 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1184 case AARCH64_PC_REGNUM
:
1185 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
1186 return frame_unwind_got_constant (this_frame
, regnum
, lr
);
1189 internal_error (__FILE__
, __LINE__
,
1190 _("Unexpected register %d"), regnum
);
1194 /* Implement the "init_reg" dwarf2_frame_ops method. */
1197 aarch64_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1198 struct dwarf2_frame_state_reg
*reg
,
1199 struct frame_info
*this_frame
)
1203 case AARCH64_PC_REGNUM
:
1204 reg
->how
= DWARF2_FRAME_REG_FN
;
1205 reg
->loc
.fn
= aarch64_dwarf2_prev_register
;
1207 case AARCH64_SP_REGNUM
:
1208 reg
->how
= DWARF2_FRAME_REG_CFA
;
1213 /* When arguments must be pushed onto the stack, they go on in reverse
1214 order. The code below implements a FILO (stack) to do this. */
1218 /* Value to pass on stack. */
1221 /* Size in bytes of value to pass on stack. */
1225 DEF_VEC_O (stack_item_t
);
1227 /* Return the alignment (in bytes) of the given type. */
1230 aarch64_type_align (struct type
*t
)
1236 t
= check_typedef (t
);
1237 switch (TYPE_CODE (t
))
1240 /* Should never happen. */
1241 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1245 case TYPE_CODE_ENUM
:
1249 case TYPE_CODE_RANGE
:
1250 case TYPE_CODE_BITSTRING
:
1252 case TYPE_CODE_CHAR
:
1253 case TYPE_CODE_BOOL
:
1254 return TYPE_LENGTH (t
);
1256 case TYPE_CODE_ARRAY
:
1257 case TYPE_CODE_COMPLEX
:
1258 return aarch64_type_align (TYPE_TARGET_TYPE (t
));
1260 case TYPE_CODE_STRUCT
:
1261 case TYPE_CODE_UNION
:
1263 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1265 falign
= aarch64_type_align (TYPE_FIELD_TYPE (t
, n
));
1273 /* Return 1 if *TY is a homogeneous floating-point aggregate as
1274 defined in the AAPCS64 ABI document; otherwise return 0. */
1277 is_hfa (struct type
*ty
)
1279 switch (TYPE_CODE (ty
))
1281 case TYPE_CODE_ARRAY
:
1283 struct type
*target_ty
= TYPE_TARGET_TYPE (ty
);
1284 if (TYPE_CODE (target_ty
) == TYPE_CODE_FLT
&& TYPE_LENGTH (ty
) <= 4)
1289 case TYPE_CODE_UNION
:
1290 case TYPE_CODE_STRUCT
:
1292 if (TYPE_NFIELDS (ty
) > 0 && TYPE_NFIELDS (ty
) <= 4)
1294 struct type
*member0_type
;
1296 member0_type
= check_typedef (TYPE_FIELD_TYPE (ty
, 0));
1297 if (TYPE_CODE (member0_type
) == TYPE_CODE_FLT
)
1301 for (i
= 0; i
< TYPE_NFIELDS (ty
); i
++)
1303 struct type
*member1_type
;
1305 member1_type
= check_typedef (TYPE_FIELD_TYPE (ty
, i
));
1306 if (TYPE_CODE (member0_type
) != TYPE_CODE (member1_type
)
1307 || (TYPE_LENGTH (member0_type
)
1308 != TYPE_LENGTH (member1_type
)))
1324 /* AArch64 function call information structure. */
1325 struct aarch64_call_info
1327 /* the current argument number. */
1330 /* The next general purpose register number, equivalent to NGRN as
1331 described in the AArch64 Procedure Call Standard. */
1334 /* The next SIMD and floating point register number, equivalent to
1335 NSRN as described in the AArch64 Procedure Call Standard. */
1338 /* The next stacked argument address, equivalent to NSAA as
1339 described in the AArch64 Procedure Call Standard. */
1342 /* Stack item vector. */
1343 VEC(stack_item_t
) *si
;
1346 /* Pass a value in a sequence of consecutive X registers. The caller
1347 is responsbile for ensuring sufficient registers are available. */
1350 pass_in_x (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1351 struct aarch64_call_info
*info
, struct type
*type
,
1352 const bfd_byte
*buf
)
1354 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1355 int len
= TYPE_LENGTH (type
);
1356 enum type_code typecode
= TYPE_CODE (type
);
1357 int regnum
= AARCH64_X0_REGNUM
+ info
->ngrn
;
1363 int partial_len
= len
< X_REGISTER_SIZE
? len
: X_REGISTER_SIZE
;
1364 CORE_ADDR regval
= extract_unsigned_integer (buf
, partial_len
,
1368 /* Adjust sub-word struct/union args when big-endian. */
1369 if (byte_order
== BFD_ENDIAN_BIG
1370 && partial_len
< X_REGISTER_SIZE
1371 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1372 regval
<<= ((X_REGISTER_SIZE
- partial_len
) * TARGET_CHAR_BIT
);
1375 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1377 gdbarch_register_name (gdbarch
, regnum
),
1378 phex (regval
, X_REGISTER_SIZE
));
1379 regcache_cooked_write_unsigned (regcache
, regnum
, regval
);
1386 /* Attempt to marshall a value in a V register. Return 1 if
1387 successful, or 0 if insufficient registers are available. This
1388 function, unlike the equivalent pass_in_x() function does not
1389 handle arguments spread across multiple registers. */
1392 pass_in_v (struct gdbarch
*gdbarch
,
1393 struct regcache
*regcache
,
1394 struct aarch64_call_info
*info
,
1395 const bfd_byte
*buf
)
1399 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1400 int regnum
= AARCH64_V0_REGNUM
+ info
->nsrn
;
1405 regcache_cooked_write (regcache
, regnum
, buf
);
1407 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s\n",
1409 gdbarch_register_name (gdbarch
, regnum
));
1416 /* Marshall an argument onto the stack. */
1419 pass_on_stack (struct aarch64_call_info
*info
, struct type
*type
,
1420 const bfd_byte
*buf
)
1422 int len
= TYPE_LENGTH (type
);
1428 align
= aarch64_type_align (type
);
1430 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1431 Natural alignment of the argument's type. */
1432 align
= align_up (align
, 8);
1434 /* The AArch64 PCS requires at most doubleword alignment. */
1439 fprintf_unfiltered (gdb_stdlog
, "arg %d len=%d @ sp + %d\n",
1440 info
->argnum
, len
, info
->nsaa
);
1444 VEC_safe_push (stack_item_t
, info
->si
, &item
);
1447 if (info
->nsaa
& (align
- 1))
1449 /* Push stack alignment padding. */
1450 int pad
= align
- (info
->nsaa
& (align
- 1));
1455 VEC_safe_push (stack_item_t
, info
->si
, &item
);
1460 /* Marshall an argument into a sequence of one or more consecutive X
1461 registers or, if insufficient X registers are available then onto
1465 pass_in_x_or_stack (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1466 struct aarch64_call_info
*info
, struct type
*type
,
1467 const bfd_byte
*buf
)
1469 int len
= TYPE_LENGTH (type
);
1470 int nregs
= (len
+ X_REGISTER_SIZE
- 1) / X_REGISTER_SIZE
;
1472 /* PCS C.13 - Pass in registers if we have enough spare */
1473 if (info
->ngrn
+ nregs
<= 8)
1475 pass_in_x (gdbarch
, regcache
, info
, type
, buf
);
1476 info
->ngrn
+= nregs
;
1481 pass_on_stack (info
, type
, buf
);
1485 /* Pass a value in a V register, or on the stack if insufficient are
1489 pass_in_v_or_stack (struct gdbarch
*gdbarch
,
1490 struct regcache
*regcache
,
1491 struct aarch64_call_info
*info
,
1493 const bfd_byte
*buf
)
1495 if (!pass_in_v (gdbarch
, regcache
, info
, buf
))
1496 pass_on_stack (info
, type
, buf
);
1499 /* Implement the "push_dummy_call" gdbarch method. */
1502 aarch64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1503 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1505 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1506 CORE_ADDR struct_addr
)
1512 struct aarch64_call_info info
;
1513 struct type
*func_type
;
1514 struct type
*return_type
;
1515 int lang_struct_return
;
1517 memset (&info
, 0, sizeof (info
));
1519 /* We need to know what the type of the called function is in order
1520 to determine the number of named/anonymous arguments for the
1521 actual argument placement, and the return type in order to handle
1522 return value correctly.
1524 The generic code above us views the decision of return in memory
1525 or return in registers as a two stage processes. The language
1526 handler is consulted first and may decide to return in memory (eg
1527 class with copy constructor returned by value), this will cause
1528 the generic code to allocate space AND insert an initial leading
1531 If the language code does not decide to pass in memory then the
1532 target code is consulted.
1534 If the language code decides to pass in memory we want to move
1535 the pointer inserted as the initial argument from the argument
1536 list and into X8, the conventional AArch64 struct return pointer
1539 This is slightly awkward, ideally the flag "lang_struct_return"
1540 would be passed to the targets implementation of push_dummy_call.
1541 Rather that change the target interface we call the language code
1542 directly ourselves. */
1544 func_type
= check_typedef (value_type (function
));
1546 /* Dereference function pointer types. */
1547 if (TYPE_CODE (func_type
) == TYPE_CODE_PTR
)
1548 func_type
= TYPE_TARGET_TYPE (func_type
);
1550 gdb_assert (TYPE_CODE (func_type
) == TYPE_CODE_FUNC
1551 || TYPE_CODE (func_type
) == TYPE_CODE_METHOD
);
1553 /* If language_pass_by_reference () returned true we will have been
1554 given an additional initial argument, a hidden pointer to the
1555 return slot in memory. */
1556 return_type
= TYPE_TARGET_TYPE (func_type
);
1557 lang_struct_return
= language_pass_by_reference (return_type
);
1559 /* Set the return address. For the AArch64, the return breakpoint
1560 is always at BP_ADDR. */
1561 regcache_cooked_write_unsigned (regcache
, AARCH64_LR_REGNUM
, bp_addr
);
1563 /* If we were given an initial argument for the return slot because
1564 lang_struct_return was true, lose it. */
1565 if (lang_struct_return
)
1571 /* The struct_return pointer occupies X8. */
1572 if (struct_return
|| lang_struct_return
)
1575 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1576 gdbarch_register_name
1578 AARCH64_STRUCT_RETURN_REGNUM
),
1579 paddress (gdbarch
, struct_addr
));
1580 regcache_cooked_write_unsigned (regcache
, AARCH64_STRUCT_RETURN_REGNUM
,
1584 for (argnum
= 0; argnum
< nargs
; argnum
++)
1586 struct value
*arg
= args
[argnum
];
1587 struct type
*arg_type
;
1590 arg_type
= check_typedef (value_type (arg
));
1591 len
= TYPE_LENGTH (arg_type
);
1593 switch (TYPE_CODE (arg_type
))
1596 case TYPE_CODE_BOOL
:
1597 case TYPE_CODE_CHAR
:
1598 case TYPE_CODE_RANGE
:
1599 case TYPE_CODE_ENUM
:
1602 /* Promote to 32 bit integer. */
1603 if (TYPE_UNSIGNED (arg_type
))
1604 arg_type
= builtin_type (gdbarch
)->builtin_uint32
;
1606 arg_type
= builtin_type (gdbarch
)->builtin_int32
;
1607 arg
= value_cast (arg_type
, arg
);
1609 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
,
1610 value_contents (arg
));
1613 case TYPE_CODE_COMPLEX
:
1616 const bfd_byte
*buf
= value_contents (arg
);
1617 struct type
*target_type
=
1618 check_typedef (TYPE_TARGET_TYPE (arg_type
));
1620 pass_in_v (gdbarch
, regcache
, &info
, buf
);
1621 pass_in_v (gdbarch
, regcache
, &info
,
1622 buf
+ TYPE_LENGTH (target_type
));
1627 pass_on_stack (&info
, arg_type
, value_contents (arg
));
1631 pass_in_v_or_stack (gdbarch
, regcache
, &info
, arg_type
,
1632 value_contents (arg
));
1635 case TYPE_CODE_STRUCT
:
1636 case TYPE_CODE_ARRAY
:
1637 case TYPE_CODE_UNION
:
1638 if (is_hfa (arg_type
))
1640 int elements
= TYPE_NFIELDS (arg_type
);
1642 /* Homogeneous Aggregates */
1643 if (info
.nsrn
+ elements
< 8)
1647 for (i
= 0; i
< elements
; i
++)
1649 /* We know that we have sufficient registers
1650 available therefore this will never fallback
1652 struct value
*field
=
1653 value_primitive_field (arg
, 0, i
, arg_type
);
1654 struct type
*field_type
=
1655 check_typedef (value_type (field
));
1657 pass_in_v_or_stack (gdbarch
, regcache
, &info
, field_type
,
1658 value_contents_writeable (field
));
1664 pass_on_stack (&info
, arg_type
, value_contents (arg
));
1669 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1670 invisible reference. */
1672 /* Allocate aligned storage. */
1673 sp
= align_down (sp
- len
, 16);
1675 /* Write the real data into the stack. */
1676 write_memory (sp
, value_contents (arg
), len
);
1678 /* Construct the indirection. */
1679 arg_type
= lookup_pointer_type (arg_type
);
1680 arg
= value_from_pointer (arg_type
, sp
);
1681 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
,
1682 value_contents (arg
));
1685 /* PCS C.15 / C.18 multiple values pass. */
1686 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
,
1687 value_contents (arg
));
1691 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
,
1692 value_contents (arg
));
1697 /* Make sure stack retains 16 byte alignment. */
1699 sp
-= 16 - (info
.nsaa
& 15);
1701 while (!VEC_empty (stack_item_t
, info
.si
))
1703 stack_item_t
*si
= VEC_last (stack_item_t
, info
.si
);
1706 write_memory (sp
, si
->data
, si
->len
);
1707 VEC_pop (stack_item_t
, info
.si
);
1710 VEC_free (stack_item_t
, info
.si
);
1712 /* Finally, update the SP register. */
1713 regcache_cooked_write_unsigned (regcache
, AARCH64_SP_REGNUM
, sp
);
1718 /* Implement the "frame_align" gdbarch method. */
1721 aarch64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1723 /* Align the stack to sixteen bytes. */
1724 return sp
& ~(CORE_ADDR
) 15;
1727 /* Return the type for an AdvSISD Q register. */
1729 static struct type
*
1730 aarch64_vnq_type (struct gdbarch
*gdbarch
)
1732 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1734 if (tdep
->vnq_type
== NULL
)
1739 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
1742 elem
= builtin_type (gdbarch
)->builtin_uint128
;
1743 append_composite_type_field (t
, "u", elem
);
1745 elem
= builtin_type (gdbarch
)->builtin_int128
;
1746 append_composite_type_field (t
, "s", elem
);
1751 return tdep
->vnq_type
;
1754 /* Return the type for an AdvSISD D register. */
1756 static struct type
*
1757 aarch64_vnd_type (struct gdbarch
*gdbarch
)
1759 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1761 if (tdep
->vnd_type
== NULL
)
1766 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
1769 elem
= builtin_type (gdbarch
)->builtin_double
;
1770 append_composite_type_field (t
, "f", elem
);
1772 elem
= builtin_type (gdbarch
)->builtin_uint64
;
1773 append_composite_type_field (t
, "u", elem
);
1775 elem
= builtin_type (gdbarch
)->builtin_int64
;
1776 append_composite_type_field (t
, "s", elem
);
1781 return tdep
->vnd_type
;
1784 /* Return the type for an AdvSISD S register. */
1786 static struct type
*
1787 aarch64_vns_type (struct gdbarch
*gdbarch
)
1789 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1791 if (tdep
->vns_type
== NULL
)
1796 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
1799 elem
= builtin_type (gdbarch
)->builtin_float
;
1800 append_composite_type_field (t
, "f", elem
);
1802 elem
= builtin_type (gdbarch
)->builtin_uint32
;
1803 append_composite_type_field (t
, "u", elem
);
1805 elem
= builtin_type (gdbarch
)->builtin_int32
;
1806 append_composite_type_field (t
, "s", elem
);
1811 return tdep
->vns_type
;
1814 /* Return the type for an AdvSISD H register. */
1816 static struct type
*
1817 aarch64_vnh_type (struct gdbarch
*gdbarch
)
1819 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1821 if (tdep
->vnh_type
== NULL
)
1826 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
1829 elem
= builtin_type (gdbarch
)->builtin_uint16
;
1830 append_composite_type_field (t
, "u", elem
);
1832 elem
= builtin_type (gdbarch
)->builtin_int16
;
1833 append_composite_type_field (t
, "s", elem
);
1838 return tdep
->vnh_type
;
1841 /* Return the type for an AdvSISD B register. */
1843 static struct type
*
1844 aarch64_vnb_type (struct gdbarch
*gdbarch
)
1846 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1848 if (tdep
->vnb_type
== NULL
)
1853 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
1856 elem
= builtin_type (gdbarch
)->builtin_uint8
;
1857 append_composite_type_field (t
, "u", elem
);
1859 elem
= builtin_type (gdbarch
)->builtin_int8
;
1860 append_composite_type_field (t
, "s", elem
);
1865 return tdep
->vnb_type
;
1868 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
1871 aarch64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
1873 if (reg
>= AARCH64_DWARF_X0
&& reg
<= AARCH64_DWARF_X0
+ 30)
1874 return AARCH64_X0_REGNUM
+ reg
- AARCH64_DWARF_X0
;
1876 if (reg
== AARCH64_DWARF_SP
)
1877 return AARCH64_SP_REGNUM
;
1879 if (reg
>= AARCH64_DWARF_V0
&& reg
<= AARCH64_DWARF_V0
+ 31)
1880 return AARCH64_V0_REGNUM
+ reg
- AARCH64_DWARF_V0
;
1886 /* Implement the "print_insn" gdbarch method. */
1889 aarch64_gdb_print_insn (bfd_vma memaddr
, disassemble_info
*info
)
1891 info
->symbols
= NULL
;
1892 return print_insn_aarch64 (memaddr
, info
);
1895 /* AArch64 BRK software debug mode instruction.
1896 Note that AArch64 code is always little-endian.
1897 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
1898 static const gdb_byte aarch64_default_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
1900 /* Implement the "breakpoint_from_pc" gdbarch method. */
1902 static const gdb_byte
*
1903 aarch64_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
1906 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1908 *lenptr
= sizeof (aarch64_default_breakpoint
);
1909 return aarch64_default_breakpoint
;
1912 /* Extract from an array REGS containing the (raw) register state a
1913 function return value of type TYPE, and copy that, in virtual
1914 format, into VALBUF. */
1917 aarch64_extract_return_value (struct type
*type
, struct regcache
*regs
,
1920 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
1921 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1923 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1925 bfd_byte buf
[V_REGISTER_SIZE
];
1926 int len
= TYPE_LENGTH (type
);
1928 regcache_cooked_read (regs
, AARCH64_V0_REGNUM
, buf
);
1929 memcpy (valbuf
, buf
, len
);
1931 else if (TYPE_CODE (type
) == TYPE_CODE_INT
1932 || TYPE_CODE (type
) == TYPE_CODE_CHAR
1933 || TYPE_CODE (type
) == TYPE_CODE_BOOL
1934 || TYPE_CODE (type
) == TYPE_CODE_PTR
1935 || TYPE_CODE (type
) == TYPE_CODE_REF
1936 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
1938 /* If the the type is a plain integer, then the access is
1939 straight-forward. Otherwise we have to play around a bit
1941 int len
= TYPE_LENGTH (type
);
1942 int regno
= AARCH64_X0_REGNUM
;
1947 /* By using store_unsigned_integer we avoid having to do
1948 anything special for small big-endian values. */
1949 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
1950 store_unsigned_integer (valbuf
,
1951 (len
> X_REGISTER_SIZE
1952 ? X_REGISTER_SIZE
: len
), byte_order
, tmp
);
1953 len
-= X_REGISTER_SIZE
;
1954 valbuf
+= X_REGISTER_SIZE
;
1957 else if (TYPE_CODE (type
) == TYPE_CODE_COMPLEX
)
1959 int regno
= AARCH64_V0_REGNUM
;
1960 bfd_byte buf
[V_REGISTER_SIZE
];
1961 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (type
));
1962 int len
= TYPE_LENGTH (target_type
);
1964 regcache_cooked_read (regs
, regno
, buf
);
1965 memcpy (valbuf
, buf
, len
);
1967 regcache_cooked_read (regs
, regno
+ 1, buf
);
1968 memcpy (valbuf
, buf
, len
);
1971 else if (is_hfa (type
))
1973 int elements
= TYPE_NFIELDS (type
);
1974 struct type
*member_type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
1975 int len
= TYPE_LENGTH (member_type
);
1978 for (i
= 0; i
< elements
; i
++)
1980 int regno
= AARCH64_V0_REGNUM
+ i
;
1981 bfd_byte buf
[X_REGISTER_SIZE
];
1984 fprintf_unfiltered (gdb_stdlog
,
1985 "read HFA return value element %d from %s\n",
1987 gdbarch_register_name (gdbarch
, regno
));
1988 regcache_cooked_read (regs
, regno
, buf
);
1990 memcpy (valbuf
, buf
, len
);
1996 /* For a structure or union the behaviour is as if the value had
1997 been stored to word-aligned memory and then loaded into
1998 registers with 64-bit load instruction(s). */
1999 int len
= TYPE_LENGTH (type
);
2000 int regno
= AARCH64_X0_REGNUM
;
2001 bfd_byte buf
[X_REGISTER_SIZE
];
2005 regcache_cooked_read (regs
, regno
++, buf
);
2006 memcpy (valbuf
, buf
, len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2007 len
-= X_REGISTER_SIZE
;
2008 valbuf
+= X_REGISTER_SIZE
;
2014 /* Will a function return an aggregate type in memory or in a
2015 register? Return 0 if an aggregate type can be returned in a
2016 register, 1 if it must be returned in memory. */
2019 aarch64_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2022 enum type_code code
;
2024 CHECK_TYPEDEF (type
);
2026 /* In the AArch64 ABI, "integer" like aggregate types are returned
2027 in registers. For an aggregate type to be integer like, its size
2028 must be less than or equal to 4 * X_REGISTER_SIZE. */
2032 /* PCS B.5 If the argument is a Named HFA, then the argument is
2037 if (TYPE_LENGTH (type
) > 16)
2039 /* PCS B.6 Aggregates larger than 16 bytes are passed by
2040 invisible reference. */
2048 /* Write into appropriate registers a function return value of type
2049 TYPE, given in virtual format. */
2052 aarch64_store_return_value (struct type
*type
, struct regcache
*regs
,
2053 const gdb_byte
*valbuf
)
2055 struct gdbarch
*gdbarch
= get_regcache_arch (regs
);
2056 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2058 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2060 bfd_byte buf
[V_REGISTER_SIZE
];
2061 int len
= TYPE_LENGTH (type
);
2063 memcpy (buf
, valbuf
, len
> V_REGISTER_SIZE
? V_REGISTER_SIZE
: len
);
2064 regcache_cooked_write (regs
, AARCH64_V0_REGNUM
, buf
);
2066 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2067 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2068 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2069 || TYPE_CODE (type
) == TYPE_CODE_PTR
2070 || TYPE_CODE (type
) == TYPE_CODE_REF
2071 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2073 if (TYPE_LENGTH (type
) <= X_REGISTER_SIZE
)
2075 /* Values of one word or less are zero/sign-extended and
2077 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2078 LONGEST val
= unpack_long (type
, valbuf
);
2080 store_signed_integer (tmpbuf
, X_REGISTER_SIZE
, byte_order
, val
);
2081 regcache_cooked_write (regs
, AARCH64_X0_REGNUM
, tmpbuf
);
2085 /* Integral values greater than one word are stored in
2086 consecutive registers starting with r0. This will always
2087 be a multiple of the regiser size. */
2088 int len
= TYPE_LENGTH (type
);
2089 int regno
= AARCH64_X0_REGNUM
;
2093 regcache_cooked_write (regs
, regno
++, valbuf
);
2094 len
-= X_REGISTER_SIZE
;
2095 valbuf
+= X_REGISTER_SIZE
;
2099 else if (is_hfa (type
))
2101 int elements
= TYPE_NFIELDS (type
);
2102 struct type
*member_type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2103 int len
= TYPE_LENGTH (member_type
);
2106 for (i
= 0; i
< elements
; i
++)
2108 int regno
= AARCH64_V0_REGNUM
+ i
;
2109 bfd_byte tmpbuf
[MAX_REGISTER_SIZE
];
2112 fprintf_unfiltered (gdb_stdlog
,
2113 "write HFA return value element %d to %s\n",
2115 gdbarch_register_name (gdbarch
, regno
));
2117 memcpy (tmpbuf
, valbuf
, len
);
2118 regcache_cooked_write (regs
, regno
, tmpbuf
);
2124 /* For a structure or union the behaviour is as if the value had
2125 been stored to word-aligned memory and then loaded into
2126 registers with 64-bit load instruction(s). */
2127 int len
= TYPE_LENGTH (type
);
2128 int regno
= AARCH64_X0_REGNUM
;
2129 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2133 memcpy (tmpbuf
, valbuf
,
2134 len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2135 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2136 len
-= X_REGISTER_SIZE
;
2137 valbuf
+= X_REGISTER_SIZE
;
2142 /* Implement the "return_value" gdbarch method. */
2144 static enum return_value_convention
2145 aarch64_return_value (struct gdbarch
*gdbarch
, struct value
*func_value
,
2146 struct type
*valtype
, struct regcache
*regcache
,
2147 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2149 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2151 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2152 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2153 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2155 if (aarch64_return_in_memory (gdbarch
, valtype
))
2158 fprintf_unfiltered (gdb_stdlog
, "return value in memory\n");
2159 return RETURN_VALUE_STRUCT_CONVENTION
;
2164 aarch64_store_return_value (valtype
, regcache
, writebuf
);
2167 aarch64_extract_return_value (valtype
, regcache
, readbuf
);
2170 fprintf_unfiltered (gdb_stdlog
, "return value in registers\n");
2172 return RETURN_VALUE_REGISTER_CONVENTION
;
2175 /* Implement the "get_longjmp_target" gdbarch method. */
2178 aarch64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2181 gdb_byte buf
[X_REGISTER_SIZE
];
2182 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2183 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2184 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2186 jb_addr
= get_frame_register_unsigned (frame
, AARCH64_X0_REGNUM
);
2188 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2192 *pc
= extract_unsigned_integer (buf
, X_REGISTER_SIZE
, byte_order
);
2197 /* Return the pseudo register name corresponding to register regnum. */
2200 aarch64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
2202 static const char *const q_name
[] =
2204 "q0", "q1", "q2", "q3",
2205 "q4", "q5", "q6", "q7",
2206 "q8", "q9", "q10", "q11",
2207 "q12", "q13", "q14", "q15",
2208 "q16", "q17", "q18", "q19",
2209 "q20", "q21", "q22", "q23",
2210 "q24", "q25", "q26", "q27",
2211 "q28", "q29", "q30", "q31",
2214 static const char *const d_name
[] =
2216 "d0", "d1", "d2", "d3",
2217 "d4", "d5", "d6", "d7",
2218 "d8", "d9", "d10", "d11",
2219 "d12", "d13", "d14", "d15",
2220 "d16", "d17", "d18", "d19",
2221 "d20", "d21", "d22", "d23",
2222 "d24", "d25", "d26", "d27",
2223 "d28", "d29", "d30", "d31",
2226 static const char *const s_name
[] =
2228 "s0", "s1", "s2", "s3",
2229 "s4", "s5", "s6", "s7",
2230 "s8", "s9", "s10", "s11",
2231 "s12", "s13", "s14", "s15",
2232 "s16", "s17", "s18", "s19",
2233 "s20", "s21", "s22", "s23",
2234 "s24", "s25", "s26", "s27",
2235 "s28", "s29", "s30", "s31",
2238 static const char *const h_name
[] =
2240 "h0", "h1", "h2", "h3",
2241 "h4", "h5", "h6", "h7",
2242 "h8", "h9", "h10", "h11",
2243 "h12", "h13", "h14", "h15",
2244 "h16", "h17", "h18", "h19",
2245 "h20", "h21", "h22", "h23",
2246 "h24", "h25", "h26", "h27",
2247 "h28", "h29", "h30", "h31",
2250 static const char *const b_name
[] =
2252 "b0", "b1", "b2", "b3",
2253 "b4", "b5", "b6", "b7",
2254 "b8", "b9", "b10", "b11",
2255 "b12", "b13", "b14", "b15",
2256 "b16", "b17", "b18", "b19",
2257 "b20", "b21", "b22", "b23",
2258 "b24", "b25", "b26", "b27",
2259 "b28", "b29", "b30", "b31",
2262 regnum
-= gdbarch_num_regs (gdbarch
);
2264 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2265 return q_name
[regnum
- AARCH64_Q0_REGNUM
];
2267 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2268 return d_name
[regnum
- AARCH64_D0_REGNUM
];
2270 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2271 return s_name
[regnum
- AARCH64_S0_REGNUM
];
2273 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2274 return h_name
[regnum
- AARCH64_H0_REGNUM
];
2276 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2277 return b_name
[regnum
- AARCH64_B0_REGNUM
];
2279 internal_error (__FILE__
, __LINE__
,
2280 _("aarch64_pseudo_register_name: bad register number %d"),
2284 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
2286 static struct type
*
2287 aarch64_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2289 regnum
-= gdbarch_num_regs (gdbarch
);
2291 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2292 return aarch64_vnq_type (gdbarch
);
2294 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2295 return aarch64_vnd_type (gdbarch
);
2297 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2298 return aarch64_vns_type (gdbarch
);
2300 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2301 return aarch64_vnh_type (gdbarch
);
2303 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2304 return aarch64_vnb_type (gdbarch
);
2306 internal_error (__FILE__
, __LINE__
,
2307 _("aarch64_pseudo_register_type: bad register number %d"),
2311 /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2314 aarch64_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2315 struct reggroup
*group
)
2317 regnum
-= gdbarch_num_regs (gdbarch
);
2319 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2320 return group
== all_reggroup
|| group
== vector_reggroup
;
2321 else if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2322 return (group
== all_reggroup
|| group
== vector_reggroup
2323 || group
== float_reggroup
);
2324 else if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2325 return (group
== all_reggroup
|| group
== vector_reggroup
2326 || group
== float_reggroup
);
2327 else if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2328 return group
== all_reggroup
|| group
== vector_reggroup
;
2329 else if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2330 return group
== all_reggroup
|| group
== vector_reggroup
;
2332 return group
== all_reggroup
;
2335 /* Implement the "pseudo_register_read_value" gdbarch method. */
2337 static struct value
*
2338 aarch64_pseudo_read_value (struct gdbarch
*gdbarch
,
2339 struct regcache
*regcache
,
2342 gdb_byte reg_buf
[MAX_REGISTER_SIZE
];
2343 struct value
*result_value
;
2346 result_value
= allocate_value (register_type (gdbarch
, regnum
));
2347 VALUE_LVAL (result_value
) = lval_register
;
2348 VALUE_REGNUM (result_value
) = regnum
;
2349 buf
= value_contents_raw (result_value
);
2351 regnum
-= gdbarch_num_regs (gdbarch
);
2353 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2355 enum register_status status
;
2358 v_regnum
= AARCH64_V0_REGNUM
+ regnum
- AARCH64_Q0_REGNUM
;
2359 status
= regcache_raw_read (regcache
, v_regnum
, reg_buf
);
2360 if (status
!= REG_VALID
)
2361 mark_value_bytes_unavailable (result_value
, 0,
2362 TYPE_LENGTH (value_type (result_value
)));
2364 memcpy (buf
, reg_buf
, Q_REGISTER_SIZE
);
2365 return result_value
;
2368 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2370 enum register_status status
;
2373 v_regnum
= AARCH64_V0_REGNUM
+ regnum
- AARCH64_D0_REGNUM
;
2374 status
= regcache_raw_read (regcache
, v_regnum
, reg_buf
);
2375 if (status
!= REG_VALID
)
2376 mark_value_bytes_unavailable (result_value
, 0,
2377 TYPE_LENGTH (value_type (result_value
)));
2379 memcpy (buf
, reg_buf
, D_REGISTER_SIZE
);
2380 return result_value
;
2383 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2385 enum register_status status
;
2388 v_regnum
= AARCH64_V0_REGNUM
+ regnum
- AARCH64_S0_REGNUM
;
2389 status
= regcache_raw_read (regcache
, v_regnum
, reg_buf
);
2390 memcpy (buf
, reg_buf
, S_REGISTER_SIZE
);
2391 return result_value
;
2394 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2396 enum register_status status
;
2399 v_regnum
= AARCH64_V0_REGNUM
+ regnum
- AARCH64_H0_REGNUM
;
2400 status
= regcache_raw_read (regcache
, v_regnum
, reg_buf
);
2401 if (status
!= REG_VALID
)
2402 mark_value_bytes_unavailable (result_value
, 0,
2403 TYPE_LENGTH (value_type (result_value
)));
2405 memcpy (buf
, reg_buf
, H_REGISTER_SIZE
);
2406 return result_value
;
2409 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2411 enum register_status status
;
2414 v_regnum
= AARCH64_V0_REGNUM
+ regnum
- AARCH64_B0_REGNUM
;
2415 status
= regcache_raw_read (regcache
, v_regnum
, reg_buf
);
2416 if (status
!= REG_VALID
)
2417 mark_value_bytes_unavailable (result_value
, 0,
2418 TYPE_LENGTH (value_type (result_value
)));
2420 memcpy (buf
, reg_buf
, B_REGISTER_SIZE
);
2421 return result_value
;
2424 gdb_assert_not_reached ("regnum out of bound");
2427 /* Implement the "pseudo_register_write" gdbarch method. */
2430 aarch64_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2431 int regnum
, const gdb_byte
*buf
)
2433 gdb_byte reg_buf
[MAX_REGISTER_SIZE
];
2435 /* Ensure the register buffer is zero, we want gdb writes of the
2436 various 'scalar' pseudo registers to behavior like architectural
2437 writes, register width bytes are written the remainder are set to
2439 memset (reg_buf
, 0, sizeof (reg_buf
));
2441 regnum
-= gdbarch_num_regs (gdbarch
);
2443 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2445 /* pseudo Q registers */
2448 v_regnum
= AARCH64_V0_REGNUM
+ regnum
- AARCH64_Q0_REGNUM
;
2449 memcpy (reg_buf
, buf
, Q_REGISTER_SIZE
);
2450 regcache_raw_write (regcache
, v_regnum
, reg_buf
);
2454 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2456 /* pseudo D registers */
2459 v_regnum
= AARCH64_V0_REGNUM
+ regnum
- AARCH64_D0_REGNUM
;
2460 memcpy (reg_buf
, buf
, D_REGISTER_SIZE
);
2461 regcache_raw_write (regcache
, v_regnum
, reg_buf
);
2465 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2469 v_regnum
= AARCH64_V0_REGNUM
+ regnum
- AARCH64_S0_REGNUM
;
2470 memcpy (reg_buf
, buf
, S_REGISTER_SIZE
);
2471 regcache_raw_write (regcache
, v_regnum
, reg_buf
);
2475 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2477 /* pseudo H registers */
2480 v_regnum
= AARCH64_V0_REGNUM
+ regnum
- AARCH64_H0_REGNUM
;
2481 memcpy (reg_buf
, buf
, H_REGISTER_SIZE
);
2482 regcache_raw_write (regcache
, v_regnum
, reg_buf
);
2486 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2488 /* pseudo B registers */
2491 v_regnum
= AARCH64_V0_REGNUM
+ regnum
- AARCH64_B0_REGNUM
;
2492 memcpy (reg_buf
, buf
, B_REGISTER_SIZE
);
2493 regcache_raw_write (regcache
, v_regnum
, reg_buf
);
2497 gdb_assert_not_reached ("regnum out of bound");
2500 /* Callback function for user_reg_add. */
2502 static struct value
*
2503 value_of_aarch64_user_reg (struct frame_info
*frame
, const void *baton
)
2505 const int *reg_p
= baton
;
2507 return value_of_register (*reg_p
, frame
);
2511 /* Implement the "software_single_step" gdbarch method, needed to
2512 single step through atomic sequences on AArch64. */
2515 aarch64_software_single_step (struct frame_info
*frame
)
2517 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2518 struct address_space
*aspace
= get_frame_address_space (frame
);
2519 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2520 const int insn_size
= 4;
2521 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2522 CORE_ADDR pc
= get_frame_pc (frame
);
2523 CORE_ADDR breaks
[2] = { -1, -1 };
2525 CORE_ADDR closing_insn
= 0;
2526 uint32_t insn
= read_memory_unsigned_integer (loc
, insn_size
,
2527 byte_order_for_code
);
2530 int bc_insn_count
= 0; /* Conditional branch instruction count. */
2531 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2533 /* Look for a Load Exclusive instruction which begins the sequence. */
2534 if (!decode_masked_match (insn
, 0x3fc00000, 0x08400000))
2537 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2543 insn
= read_memory_unsigned_integer (loc
, insn_size
,
2544 byte_order_for_code
);
2546 /* Check if the instruction is a conditional branch. */
2547 if (decode_bcond (loc
, insn
, &cond
, &offset
))
2549 if (bc_insn_count
>= 1)
2552 /* It is, so we'll try to set a breakpoint at the destination. */
2553 breaks
[1] = loc
+ offset
;
2559 /* Look for the Store Exclusive which closes the atomic sequence. */
2560 if (decode_masked_match (insn
, 0x3fc00000, 0x08000000))
2567 /* We didn't find a closing Store Exclusive instruction, fall back. */
2571 /* Insert breakpoint after the end of the atomic sequence. */
2572 breaks
[0] = loc
+ insn_size
;
2574 /* Check for duplicated breakpoints, and also check that the second
2575 breakpoint is not within the atomic sequence. */
2577 && (breaks
[1] == breaks
[0]
2578 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
2579 last_breakpoint
= 0;
2581 /* Insert the breakpoint at the end of the sequence, and one at the
2582 destination of the conditional branch, if it exists. */
2583 for (index
= 0; index
<= last_breakpoint
; index
++)
2584 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
2589 /* Initialize the current architecture based on INFO. If possible,
2590 re-use an architecture from ARCHES, which is a list of
2591 architectures already created during this debugging session.
2593 Called e.g. at program startup, when reading a core file, and when
2594 reading a binary file. */
2596 static struct gdbarch
*
2597 aarch64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2599 struct gdbarch_tdep
*tdep
;
2600 struct gdbarch
*gdbarch
;
2601 struct gdbarch_list
*best_arch
;
2602 struct tdesc_arch_data
*tdesc_data
= NULL
;
2603 const struct target_desc
*tdesc
= info
.target_desc
;
2605 int have_fpa_registers
= 1;
2607 const struct tdesc_feature
*feature
;
2609 int num_pseudo_regs
= 0;
2611 /* Ensure we always have a target descriptor. */
2612 if (!tdesc_has_registers (tdesc
))
2613 tdesc
= tdesc_aarch64
;
2617 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.core");
2619 if (feature
== NULL
)
2622 tdesc_data
= tdesc_data_alloc ();
2624 /* Validate the descriptor provides the mandatory core R registers
2625 and allocate their numbers. */
2626 for (i
= 0; i
< ARRAY_SIZE (aarch64_r_register_names
); i
++)
2628 tdesc_numbered_register (feature
, tdesc_data
, AARCH64_X0_REGNUM
+ i
,
2629 aarch64_r_register_names
[i
]);
2631 num_regs
= AARCH64_X0_REGNUM
+ i
;
2633 /* Look for the V registers. */
2634 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.fpu");
2637 /* Validate the descriptor provides the mandatory V registers
2638 and allocate their numbers. */
2639 for (i
= 0; i
< ARRAY_SIZE (aarch64_v_register_names
); i
++)
2641 tdesc_numbered_register (feature
, tdesc_data
, AARCH64_V0_REGNUM
+ i
,
2642 aarch64_v_register_names
[i
]);
2644 num_regs
= AARCH64_V0_REGNUM
+ i
;
2646 num_pseudo_regs
+= 32; /* add the Qn scalar register pseudos */
2647 num_pseudo_regs
+= 32; /* add the Dn scalar register pseudos */
2648 num_pseudo_regs
+= 32; /* add the Sn scalar register pseudos */
2649 num_pseudo_regs
+= 32; /* add the Hn scalar register pseudos */
2650 num_pseudo_regs
+= 32; /* add the Bn scalar register pseudos */
2655 tdesc_data_cleanup (tdesc_data
);
2659 /* AArch64 code is always little-endian. */
2660 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
2662 /* If there is already a candidate, use it. */
2663 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
2665 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
2667 /* Found a match. */
2671 if (best_arch
!= NULL
)
2673 if (tdesc_data
!= NULL
)
2674 tdesc_data_cleanup (tdesc_data
);
2675 return best_arch
->gdbarch
;
2678 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
2679 gdbarch
= gdbarch_alloc (&info
, tdep
);
2681 /* This should be low enough for everything. */
2682 tdep
->lowest_pc
= 0x20;
2683 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2684 tdep
->jb_elt_size
= 8;
2686 set_gdbarch_push_dummy_call (gdbarch
, aarch64_push_dummy_call
);
2687 set_gdbarch_frame_align (gdbarch
, aarch64_frame_align
);
2689 /* Frame handling. */
2690 set_gdbarch_dummy_id (gdbarch
, aarch64_dummy_id
);
2691 set_gdbarch_unwind_pc (gdbarch
, aarch64_unwind_pc
);
2692 set_gdbarch_unwind_sp (gdbarch
, aarch64_unwind_sp
);
2694 /* Advance PC across function entry code. */
2695 set_gdbarch_skip_prologue (gdbarch
, aarch64_skip_prologue
);
2697 /* The stack grows downward. */
2698 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2700 /* Breakpoint manipulation. */
2701 set_gdbarch_breakpoint_from_pc (gdbarch
, aarch64_breakpoint_from_pc
);
2702 set_gdbarch_cannot_step_breakpoint (gdbarch
, 1);
2703 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
2704 set_gdbarch_software_single_step (gdbarch
, aarch64_software_single_step
);
2706 /* Information about registers, etc. */
2707 set_gdbarch_sp_regnum (gdbarch
, AARCH64_SP_REGNUM
);
2708 set_gdbarch_pc_regnum (gdbarch
, AARCH64_PC_REGNUM
);
2709 set_gdbarch_num_regs (gdbarch
, num_regs
);
2711 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudo_regs
);
2712 set_gdbarch_pseudo_register_read_value (gdbarch
, aarch64_pseudo_read_value
);
2713 set_gdbarch_pseudo_register_write (gdbarch
, aarch64_pseudo_write
);
2714 set_tdesc_pseudo_register_name (gdbarch
, aarch64_pseudo_register_name
);
2715 set_tdesc_pseudo_register_type (gdbarch
, aarch64_pseudo_register_type
);
2716 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
2717 aarch64_pseudo_register_reggroup_p
);
2720 set_gdbarch_short_bit (gdbarch
, 16);
2721 set_gdbarch_int_bit (gdbarch
, 32);
2722 set_gdbarch_float_bit (gdbarch
, 32);
2723 set_gdbarch_double_bit (gdbarch
, 64);
2724 set_gdbarch_long_double_bit (gdbarch
, 128);
2725 set_gdbarch_long_bit (gdbarch
, 64);
2726 set_gdbarch_long_long_bit (gdbarch
, 64);
2727 set_gdbarch_ptr_bit (gdbarch
, 64);
2728 set_gdbarch_char_signed (gdbarch
, 0);
2729 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
2730 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
2731 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
2733 /* Internal <-> external register number maps. */
2734 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, aarch64_dwarf_reg_to_regnum
);
2736 /* Returning results. */
2737 set_gdbarch_return_value (gdbarch
, aarch64_return_value
);
2740 set_gdbarch_print_insn (gdbarch
, aarch64_gdb_print_insn
);
2742 /* Virtual tables. */
2743 set_gdbarch_vbit_in_delta (gdbarch
, 1);
2745 /* Hook in the ABI-specific overrides, if they have been registered. */
2746 info
.target_desc
= tdesc
;
2747 info
.tdep_info
= (void *) tdesc_data
;
2748 gdbarch_init_osabi (info
, gdbarch
);
2750 dwarf2_frame_set_init_reg (gdbarch
, aarch64_dwarf2_frame_init_reg
);
2752 /* Add some default predicates. */
2753 frame_unwind_append_unwinder (gdbarch
, &aarch64_stub_unwind
);
2754 dwarf2_append_unwinders (gdbarch
);
2755 frame_unwind_append_unwinder (gdbarch
, &aarch64_prologue_unwind
);
2757 frame_base_set_default (gdbarch
, &aarch64_normal_base
);
2759 /* Now we have tuned the configuration, set a few final things,
2760 based on what the OS ABI has told us. */
2762 if (tdep
->jb_pc
>= 0)
2763 set_gdbarch_get_longjmp_target (gdbarch
, aarch64_get_longjmp_target
);
2765 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
2767 /* Add standard register aliases. */
2768 for (i
= 0; i
< ARRAY_SIZE (aarch64_register_aliases
); i
++)
2769 user_reg_add (gdbarch
, aarch64_register_aliases
[i
].name
,
2770 value_of_aarch64_user_reg
,
2771 &aarch64_register_aliases
[i
].regnum
);
2777 aarch64_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
2779 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2784 fprintf_unfiltered (file
, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
2785 paddress (gdbarch
, tdep
->lowest_pc
));
2788 /* Suppress warning from -Wmissing-prototypes. */
2789 extern initialize_file_ftype _initialize_aarch64_tdep
;
2792 _initialize_aarch64_tdep (void)
2794 gdbarch_register (bfd_arch_aarch64
, aarch64_gdbarch_init
,
2797 initialize_tdesc_aarch64 ();
2799 /* Debug this file's internals. */
2800 add_setshow_boolean_cmd ("aarch64", class_maintenance
, &aarch64_debug
, _("\
2801 Set AArch64 debugging."), _("\
2802 Show AArch64 debugging."), _("\
2803 When on, AArch64 specific debugging is enabled."),
2806 &setdebuglist
, &showdebuglist
);