1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "reggroups.h"
31 #include "arch-utils.h"
33 #include "frame-unwind.h"
34 #include "frame-base.h"
35 #include "trad-frame.h"
37 #include "dwarf2-frame.h"
39 #include "prologue-value.h"
40 #include "target-descriptions.h"
41 #include "user-regs.h"
48 #include "aarch64-tdep.h"
51 #include "elf/aarch64.h"
56 #include "record-full.h"
57 #include "arch/aarch64-insn.h"
59 #include "opcode/aarch64.h"
62 #define submask(x) ((1L << ((x) + 1)) - 1)
63 #define bit(obj,st) (((obj) >> (st)) & 1)
64 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
66 /* Pseudo register base numbers. */
67 #define AARCH64_Q0_REGNUM 0
68 #define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + AARCH64_D_REGISTER_COUNT)
69 #define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32)
70 #define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
71 #define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
72 #define AARCH64_SVE_V0_REGNUM (AARCH64_B0_REGNUM + 32)
74 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
76 #define HA_MAX_NUM_FLDS 4
78 /* All possible aarch64 target descriptors. */
79 struct target_desc
*tdesc_aarch64_list
[AARCH64_MAX_SVE_VQ
+ 1];
81 /* The standard register names, and all the valid aliases for them. */
84 const char *const name
;
86 } aarch64_register_aliases
[] =
88 /* 64-bit register names. */
89 {"fp", AARCH64_FP_REGNUM
},
90 {"lr", AARCH64_LR_REGNUM
},
91 {"sp", AARCH64_SP_REGNUM
},
93 /* 32-bit register names. */
94 {"w0", AARCH64_X0_REGNUM
+ 0},
95 {"w1", AARCH64_X0_REGNUM
+ 1},
96 {"w2", AARCH64_X0_REGNUM
+ 2},
97 {"w3", AARCH64_X0_REGNUM
+ 3},
98 {"w4", AARCH64_X0_REGNUM
+ 4},
99 {"w5", AARCH64_X0_REGNUM
+ 5},
100 {"w6", AARCH64_X0_REGNUM
+ 6},
101 {"w7", AARCH64_X0_REGNUM
+ 7},
102 {"w8", AARCH64_X0_REGNUM
+ 8},
103 {"w9", AARCH64_X0_REGNUM
+ 9},
104 {"w10", AARCH64_X0_REGNUM
+ 10},
105 {"w11", AARCH64_X0_REGNUM
+ 11},
106 {"w12", AARCH64_X0_REGNUM
+ 12},
107 {"w13", AARCH64_X0_REGNUM
+ 13},
108 {"w14", AARCH64_X0_REGNUM
+ 14},
109 {"w15", AARCH64_X0_REGNUM
+ 15},
110 {"w16", AARCH64_X0_REGNUM
+ 16},
111 {"w17", AARCH64_X0_REGNUM
+ 17},
112 {"w18", AARCH64_X0_REGNUM
+ 18},
113 {"w19", AARCH64_X0_REGNUM
+ 19},
114 {"w20", AARCH64_X0_REGNUM
+ 20},
115 {"w21", AARCH64_X0_REGNUM
+ 21},
116 {"w22", AARCH64_X0_REGNUM
+ 22},
117 {"w23", AARCH64_X0_REGNUM
+ 23},
118 {"w24", AARCH64_X0_REGNUM
+ 24},
119 {"w25", AARCH64_X0_REGNUM
+ 25},
120 {"w26", AARCH64_X0_REGNUM
+ 26},
121 {"w27", AARCH64_X0_REGNUM
+ 27},
122 {"w28", AARCH64_X0_REGNUM
+ 28},
123 {"w29", AARCH64_X0_REGNUM
+ 29},
124 {"w30", AARCH64_X0_REGNUM
+ 30},
127 {"ip0", AARCH64_X0_REGNUM
+ 16},
128 {"ip1", AARCH64_X0_REGNUM
+ 17}
131 /* The required core 'R' registers. */
132 static const char *const aarch64_r_register_names
[] =
134 /* These registers must appear in consecutive RAW register number
135 order and they must begin with AARCH64_X0_REGNUM! */
136 "x0", "x1", "x2", "x3",
137 "x4", "x5", "x6", "x7",
138 "x8", "x9", "x10", "x11",
139 "x12", "x13", "x14", "x15",
140 "x16", "x17", "x18", "x19",
141 "x20", "x21", "x22", "x23",
142 "x24", "x25", "x26", "x27",
143 "x28", "x29", "x30", "sp",
147 /* The FP/SIMD 'V' registers. */
148 static const char *const aarch64_v_register_names
[] =
150 /* These registers must appear in consecutive RAW register number
151 order and they must begin with AARCH64_V0_REGNUM! */
152 "v0", "v1", "v2", "v3",
153 "v4", "v5", "v6", "v7",
154 "v8", "v9", "v10", "v11",
155 "v12", "v13", "v14", "v15",
156 "v16", "v17", "v18", "v19",
157 "v20", "v21", "v22", "v23",
158 "v24", "v25", "v26", "v27",
159 "v28", "v29", "v30", "v31",
164 /* The SVE 'Z' and 'P' registers. */
165 static const char *const aarch64_sve_register_names
[] =
167 /* These registers must appear in consecutive RAW register number
168 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
169 "z0", "z1", "z2", "z3",
170 "z4", "z5", "z6", "z7",
171 "z8", "z9", "z10", "z11",
172 "z12", "z13", "z14", "z15",
173 "z16", "z17", "z18", "z19",
174 "z20", "z21", "z22", "z23",
175 "z24", "z25", "z26", "z27",
176 "z28", "z29", "z30", "z31",
178 "p0", "p1", "p2", "p3",
179 "p4", "p5", "p6", "p7",
180 "p8", "p9", "p10", "p11",
181 "p12", "p13", "p14", "p15",
185 /* AArch64 prologue cache structure. */
186 struct aarch64_prologue_cache
188 /* The program counter at the start of the function. It is used to
189 identify this frame as a prologue frame. */
192 /* The program counter at the time this frame was created; i.e. where
193 this function was called from. It is used to identify this frame as a
197 /* The stack pointer at the time this frame was created; i.e. the
198 caller's stack pointer when this function was called. It is used
199 to identify this frame. */
202 /* Is the target available to read from? */
205 /* The frame base for this frame is just prev_sp - frame size.
206 FRAMESIZE is the distance from the frame pointer to the
207 initial stack pointer. */
210 /* The register used to hold the frame pointer for this frame. */
213 /* Saved register offsets. */
214 struct trad_frame_saved_reg
*saved_regs
;
218 show_aarch64_debug (struct ui_file
*file
, int from_tty
,
219 struct cmd_list_element
*c
, const char *value
)
221 fprintf_filtered (file
, _("AArch64 debugging is %s.\n"), value
);
226 /* Abstract instruction reader. */
228 class abstract_instruction_reader
231 /* Read in one instruction. */
232 virtual ULONGEST
read (CORE_ADDR memaddr
, int len
,
233 enum bfd_endian byte_order
) = 0;
236 /* Instruction reader from real target. */
238 class instruction_reader
: public abstract_instruction_reader
241 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
244 return read_code_unsigned_integer (memaddr
, len
, byte_order
);
250 /* Analyze a prologue, looking for a recognizable stack frame
251 and frame pointer. Scan until we encounter a store that could
252 clobber the stack frame unexpectedly, or an unknown instruction. */
255 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
256 CORE_ADDR start
, CORE_ADDR limit
,
257 struct aarch64_prologue_cache
*cache
,
258 abstract_instruction_reader
& reader
)
260 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
262 /* Track X registers and D registers in prologue. */
263 pv_t regs
[AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
];
265 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
; i
++)
266 regs
[i
] = pv_register (i
, 0);
267 pv_area
stack (AARCH64_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
269 for (; start
< limit
; start
+= 4)
274 insn
= reader
.read (start
, 4, byte_order_for_code
);
276 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
279 if (inst
.opcode
->iclass
== addsub_imm
280 && (inst
.opcode
->op
== OP_ADD
281 || strcmp ("sub", inst
.opcode
->name
) == 0))
283 unsigned rd
= inst
.operands
[0].reg
.regno
;
284 unsigned rn
= inst
.operands
[1].reg
.regno
;
286 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 3);
287 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd_SP
);
288 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn_SP
);
289 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_AIMM
);
291 if (inst
.opcode
->op
== OP_ADD
)
293 regs
[rd
] = pv_add_constant (regs
[rn
],
294 inst
.operands
[2].imm
.value
);
298 regs
[rd
] = pv_add_constant (regs
[rn
],
299 -inst
.operands
[2].imm
.value
);
302 else if (inst
.opcode
->iclass
== pcreladdr
303 && inst
.operands
[1].type
== AARCH64_OPND_ADDR_ADRP
)
305 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
306 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
308 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
310 else if (inst
.opcode
->iclass
== branch_imm
)
312 /* Stop analysis on branch. */
315 else if (inst
.opcode
->iclass
== condbranch
)
317 /* Stop analysis on branch. */
320 else if (inst
.opcode
->iclass
== branch_reg
)
322 /* Stop analysis on branch. */
325 else if (inst
.opcode
->iclass
== compbranch
)
327 /* Stop analysis on branch. */
330 else if (inst
.opcode
->op
== OP_MOVZ
)
332 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
333 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
335 else if (inst
.opcode
->iclass
== log_shift
336 && strcmp (inst
.opcode
->name
, "orr") == 0)
338 unsigned rd
= inst
.operands
[0].reg
.regno
;
339 unsigned rn
= inst
.operands
[1].reg
.regno
;
340 unsigned rm
= inst
.operands
[2].reg
.regno
;
342 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
343 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn
);
344 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_Rm_SFT
);
346 if (inst
.operands
[2].shifter
.amount
== 0
347 && rn
== AARCH64_SP_REGNUM
)
353 debug_printf ("aarch64: prologue analysis gave up "
354 "addr=%s opcode=0x%x (orr x register)\n",
355 core_addr_to_string_nz (start
), insn
);
360 else if (inst
.opcode
->op
== OP_STUR
)
362 unsigned rt
= inst
.operands
[0].reg
.regno
;
363 unsigned rn
= inst
.operands
[1].addr
.base_regno
;
365 = (aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
) == 8);
367 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
368 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
);
369 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_ADDR_SIMM9
);
370 gdb_assert (!inst
.operands
[1].addr
.offset
.is_reg
);
372 stack
.store (pv_add_constant (regs
[rn
],
373 inst
.operands
[1].addr
.offset
.imm
),
374 is64
? 8 : 4, regs
[rt
]);
376 else if ((inst
.opcode
->iclass
== ldstpair_off
377 || (inst
.opcode
->iclass
== ldstpair_indexed
378 && inst
.operands
[2].addr
.preind
))
379 && strcmp ("stp", inst
.opcode
->name
) == 0)
381 /* STP with addressing mode Pre-indexed and Base register. */
384 unsigned rn
= inst
.operands
[2].addr
.base_regno
;
385 int32_t imm
= inst
.operands
[2].addr
.offset
.imm
;
387 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
388 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
389 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rt2
390 || inst
.operands
[1].type
== AARCH64_OPND_Ft2
);
391 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_ADDR_SIMM7
);
392 gdb_assert (!inst
.operands
[2].addr
.offset
.is_reg
);
394 /* If recording this store would invalidate the store area
395 (perhaps because rn is not known) then we should abandon
396 further prologue analysis. */
397 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
)))
400 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
+ 8)))
403 rt1
= inst
.operands
[0].reg
.regno
;
404 rt2
= inst
.operands
[1].reg
.regno
;
405 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
407 /* Only bottom 64-bit of each V register (D register) need
409 gdb_assert (inst
.operands
[0].qualifier
== AARCH64_OPND_QLF_S_D
);
410 rt1
+= AARCH64_X_REGISTER_COUNT
;
411 rt2
+= AARCH64_X_REGISTER_COUNT
;
414 stack
.store (pv_add_constant (regs
[rn
], imm
), 8,
416 stack
.store (pv_add_constant (regs
[rn
], imm
+ 8), 8,
419 if (inst
.operands
[2].addr
.writeback
)
420 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
423 else if ((inst
.opcode
->iclass
== ldst_imm9
/* Signed immediate. */
424 || (inst
.opcode
->iclass
== ldst_pos
/* Unsigned immediate. */
425 && (inst
.opcode
->op
== OP_STR_POS
426 || inst
.opcode
->op
== OP_STRF_POS
)))
427 && inst
.operands
[1].addr
.base_regno
== AARCH64_SP_REGNUM
428 && strcmp ("str", inst
.opcode
->name
) == 0)
430 /* STR (immediate) */
431 unsigned int rt
= inst
.operands
[0].reg
.regno
;
432 int32_t imm
= inst
.operands
[1].addr
.offset
.imm
;
433 unsigned int rn
= inst
.operands
[1].addr
.base_regno
;
435 = (aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
) == 8);
436 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
437 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
439 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
441 /* Only bottom 64-bit of each V register (D register) need
443 gdb_assert (inst
.operands
[0].qualifier
== AARCH64_OPND_QLF_S_D
);
444 rt
+= AARCH64_X_REGISTER_COUNT
;
447 stack
.store (pv_add_constant (regs
[rn
], imm
),
448 is64
? 8 : 4, regs
[rt
]);
449 if (inst
.operands
[1].addr
.writeback
)
450 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
452 else if (inst
.opcode
->iclass
== testbranch
)
454 /* Stop analysis on branch. */
461 debug_printf ("aarch64: prologue analysis gave up addr=%s"
463 core_addr_to_string_nz (start
), insn
);
472 if (pv_is_register (regs
[AARCH64_FP_REGNUM
], AARCH64_SP_REGNUM
))
474 /* Frame pointer is fp. Frame size is constant. */
475 cache
->framereg
= AARCH64_FP_REGNUM
;
476 cache
->framesize
= -regs
[AARCH64_FP_REGNUM
].k
;
478 else if (pv_is_register (regs
[AARCH64_SP_REGNUM
], AARCH64_SP_REGNUM
))
480 /* Try the stack pointer. */
481 cache
->framesize
= -regs
[AARCH64_SP_REGNUM
].k
;
482 cache
->framereg
= AARCH64_SP_REGNUM
;
486 /* We're just out of luck. We don't know where the frame is. */
487 cache
->framereg
= -1;
488 cache
->framesize
= 0;
491 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
495 if (stack
.find_reg (gdbarch
, i
, &offset
))
496 cache
->saved_regs
[i
].addr
= offset
;
499 for (i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
501 int regnum
= gdbarch_num_regs (gdbarch
);
504 if (stack
.find_reg (gdbarch
, i
+ AARCH64_X_REGISTER_COUNT
,
506 cache
->saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
= offset
;
513 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
514 CORE_ADDR start
, CORE_ADDR limit
,
515 struct aarch64_prologue_cache
*cache
)
517 instruction_reader reader
;
519 return aarch64_analyze_prologue (gdbarch
, start
, limit
, cache
,
525 namespace selftests
{
527 /* Instruction reader from manually cooked instruction sequences. */
529 class instruction_reader_test
: public abstract_instruction_reader
532 template<size_t SIZE
>
533 explicit instruction_reader_test (const uint32_t (&insns
)[SIZE
])
534 : m_insns (insns
), m_insns_size (SIZE
)
537 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
540 SELF_CHECK (len
== 4);
541 SELF_CHECK (memaddr
% 4 == 0);
542 SELF_CHECK (memaddr
/ 4 < m_insns_size
);
544 return m_insns
[memaddr
/ 4];
548 const uint32_t *m_insns
;
553 aarch64_analyze_prologue_test (void)
555 struct gdbarch_info info
;
557 gdbarch_info_init (&info
);
558 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
560 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
561 SELF_CHECK (gdbarch
!= NULL
);
563 /* Test the simple prologue in which frame pointer is used. */
565 struct aarch64_prologue_cache cache
;
566 cache
.saved_regs
= trad_frame_alloc_saved_regs (gdbarch
);
568 static const uint32_t insns
[] = {
569 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
570 0x910003fd, /* mov x29, sp */
571 0x97ffffe6, /* bl 0x400580 */
573 instruction_reader_test
reader (insns
);
575 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
576 SELF_CHECK (end
== 4 * 2);
578 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
579 SELF_CHECK (cache
.framesize
== 272);
581 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
583 if (i
== AARCH64_FP_REGNUM
)
584 SELF_CHECK (cache
.saved_regs
[i
].addr
== -272);
585 else if (i
== AARCH64_LR_REGNUM
)
586 SELF_CHECK (cache
.saved_regs
[i
].addr
== -264);
588 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
591 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
593 int regnum
= gdbarch_num_regs (gdbarch
);
595 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
600 /* Test a prologue in which STR is used and frame pointer is not
603 struct aarch64_prologue_cache cache
;
604 cache
.saved_regs
= trad_frame_alloc_saved_regs (gdbarch
);
606 static const uint32_t insns
[] = {
607 0xf81d0ff3, /* str x19, [sp, #-48]! */
608 0xb9002fe0, /* str w0, [sp, #44] */
609 0xf90013e1, /* str x1, [sp, #32]*/
610 0xfd000fe0, /* str d0, [sp, #24] */
611 0xaa0203f3, /* mov x19, x2 */
612 0xf94013e0, /* ldr x0, [sp, #32] */
614 instruction_reader_test
reader (insns
);
616 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
618 SELF_CHECK (end
== 4 * 5);
620 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
621 SELF_CHECK (cache
.framesize
== 48);
623 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
626 SELF_CHECK (cache
.saved_regs
[i
].addr
== -16);
628 SELF_CHECK (cache
.saved_regs
[i
].addr
== -48);
630 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
633 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
635 int regnum
= gdbarch_num_regs (gdbarch
);
638 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
641 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
646 } // namespace selftests
647 #endif /* GDB_SELF_TEST */
649 /* Implement the "skip_prologue" gdbarch method. */
652 aarch64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
654 CORE_ADDR func_addr
, limit_pc
;
656 /* See if we can determine the end of the prologue via the symbol
657 table. If so, then return either PC, or the PC after the
658 prologue, whichever is greater. */
659 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
661 CORE_ADDR post_prologue_pc
662 = skip_prologue_using_sal (gdbarch
, func_addr
);
664 if (post_prologue_pc
!= 0)
665 return std::max (pc
, post_prologue_pc
);
668 /* Can't determine prologue from the symbol table, need to examine
671 /* Find an upper limit on the function prologue using the debug
672 information. If the debug information could not be used to
673 provide that bound, then use an arbitrary large number as the
675 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
677 limit_pc
= pc
+ 128; /* Magic. */
679 /* Try disassembling prologue. */
680 return aarch64_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
683 /* Scan the function prologue for THIS_FRAME and populate the prologue
687 aarch64_scan_prologue (struct frame_info
*this_frame
,
688 struct aarch64_prologue_cache
*cache
)
690 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
691 CORE_ADDR prologue_start
;
692 CORE_ADDR prologue_end
;
693 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
694 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
696 cache
->prev_pc
= prev_pc
;
698 /* Assume we do not find a frame. */
699 cache
->framereg
= -1;
700 cache
->framesize
= 0;
702 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
705 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
709 /* No line info so use the current PC. */
710 prologue_end
= prev_pc
;
712 else if (sal
.end
< prologue_end
)
714 /* The next line begins after the function end. */
715 prologue_end
= sal
.end
;
718 prologue_end
= std::min (prologue_end
, prev_pc
);
719 aarch64_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
725 frame_loc
= get_frame_register_unsigned (this_frame
, AARCH64_FP_REGNUM
);
729 cache
->framereg
= AARCH64_FP_REGNUM
;
730 cache
->framesize
= 16;
731 cache
->saved_regs
[29].addr
= 0;
732 cache
->saved_regs
[30].addr
= 8;
736 /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
737 function may throw an exception if the inferior's registers or memory is
741 aarch64_make_prologue_cache_1 (struct frame_info
*this_frame
,
742 struct aarch64_prologue_cache
*cache
)
744 CORE_ADDR unwound_fp
;
747 aarch64_scan_prologue (this_frame
, cache
);
749 if (cache
->framereg
== -1)
752 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
756 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
758 /* Calculate actual addresses of saved registers using offsets
759 determined by aarch64_analyze_prologue. */
760 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
761 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
762 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
764 cache
->func
= get_frame_func (this_frame
);
766 cache
->available_p
= 1;
769 /* Allocate and fill in *THIS_CACHE with information about the prologue of
770 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
771 Return a pointer to the current aarch64_prologue_cache in
774 static struct aarch64_prologue_cache
*
775 aarch64_make_prologue_cache (struct frame_info
*this_frame
, void **this_cache
)
777 struct aarch64_prologue_cache
*cache
;
779 if (*this_cache
!= NULL
)
780 return (struct aarch64_prologue_cache
*) *this_cache
;
782 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
783 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
788 aarch64_make_prologue_cache_1 (this_frame
, cache
);
790 CATCH (ex
, RETURN_MASK_ERROR
)
792 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
793 throw_exception (ex
);
800 /* Implement the "stop_reason" frame_unwind method. */
802 static enum unwind_stop_reason
803 aarch64_prologue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
806 struct aarch64_prologue_cache
*cache
807 = aarch64_make_prologue_cache (this_frame
, this_cache
);
809 if (!cache
->available_p
)
810 return UNWIND_UNAVAILABLE
;
812 /* Halt the backtrace at "_start". */
813 if (cache
->prev_pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
814 return UNWIND_OUTERMOST
;
816 /* We've hit a wall, stop. */
817 if (cache
->prev_sp
== 0)
818 return UNWIND_OUTERMOST
;
820 return UNWIND_NO_REASON
;
823 /* Our frame ID for a normal frame is the current function's starting
824 PC and the caller's SP when we were called. */
827 aarch64_prologue_this_id (struct frame_info
*this_frame
,
828 void **this_cache
, struct frame_id
*this_id
)
830 struct aarch64_prologue_cache
*cache
831 = aarch64_make_prologue_cache (this_frame
, this_cache
);
833 if (!cache
->available_p
)
834 *this_id
= frame_id_build_unavailable_stack (cache
->func
);
836 *this_id
= frame_id_build (cache
->prev_sp
, cache
->func
);
839 /* Implement the "prev_register" frame_unwind method. */
841 static struct value
*
842 aarch64_prologue_prev_register (struct frame_info
*this_frame
,
843 void **this_cache
, int prev_regnum
)
845 struct aarch64_prologue_cache
*cache
846 = aarch64_make_prologue_cache (this_frame
, this_cache
);
848 /* If we are asked to unwind the PC, then we need to return the LR
849 instead. The prologue may save PC, but it will point into this
850 frame's prologue, not the next frame's resume location. */
851 if (prev_regnum
== AARCH64_PC_REGNUM
)
855 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
856 return frame_unwind_got_constant (this_frame
, prev_regnum
, lr
);
859 /* SP is generally not saved to the stack, but this frame is
860 identified by the next frame's stack pointer at the time of the
861 call. The value was already reconstructed into PREV_SP. */
874 if (prev_regnum
== AARCH64_SP_REGNUM
)
875 return frame_unwind_got_constant (this_frame
, prev_regnum
,
878 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
882 /* AArch64 prologue unwinder. */
883 struct frame_unwind aarch64_prologue_unwind
=
886 aarch64_prologue_frame_unwind_stop_reason
,
887 aarch64_prologue_this_id
,
888 aarch64_prologue_prev_register
,
890 default_frame_sniffer
893 /* Allocate and fill in *THIS_CACHE with information about the prologue of
894 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
895 Return a pointer to the current aarch64_prologue_cache in
898 static struct aarch64_prologue_cache
*
899 aarch64_make_stub_cache (struct frame_info
*this_frame
, void **this_cache
)
901 struct aarch64_prologue_cache
*cache
;
903 if (*this_cache
!= NULL
)
904 return (struct aarch64_prologue_cache
*) *this_cache
;
906 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
907 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
912 cache
->prev_sp
= get_frame_register_unsigned (this_frame
,
914 cache
->prev_pc
= get_frame_pc (this_frame
);
915 cache
->available_p
= 1;
917 CATCH (ex
, RETURN_MASK_ERROR
)
919 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
920 throw_exception (ex
);
927 /* Implement the "stop_reason" frame_unwind method. */
929 static enum unwind_stop_reason
930 aarch64_stub_frame_unwind_stop_reason (struct frame_info
*this_frame
,
933 struct aarch64_prologue_cache
*cache
934 = aarch64_make_stub_cache (this_frame
, this_cache
);
936 if (!cache
->available_p
)
937 return UNWIND_UNAVAILABLE
;
939 return UNWIND_NO_REASON
;
942 /* Our frame ID for a stub frame is the current SP and LR. */
945 aarch64_stub_this_id (struct frame_info
*this_frame
,
946 void **this_cache
, struct frame_id
*this_id
)
948 struct aarch64_prologue_cache
*cache
949 = aarch64_make_stub_cache (this_frame
, this_cache
);
951 if (cache
->available_p
)
952 *this_id
= frame_id_build (cache
->prev_sp
, cache
->prev_pc
);
954 *this_id
= frame_id_build_unavailable_stack (cache
->prev_pc
);
957 /* Implement the "sniffer" frame_unwind method. */
960 aarch64_stub_unwind_sniffer (const struct frame_unwind
*self
,
961 struct frame_info
*this_frame
,
962 void **this_prologue_cache
)
964 CORE_ADDR addr_in_block
;
967 addr_in_block
= get_frame_address_in_block (this_frame
);
968 if (in_plt_section (addr_in_block
)
969 /* We also use the stub winder if the target memory is unreadable
970 to avoid having the prologue unwinder trying to read it. */
971 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
977 /* AArch64 stub unwinder. */
978 struct frame_unwind aarch64_stub_unwind
=
981 aarch64_stub_frame_unwind_stop_reason
,
982 aarch64_stub_this_id
,
983 aarch64_prologue_prev_register
,
985 aarch64_stub_unwind_sniffer
988 /* Return the frame base address of *THIS_FRAME. */
991 aarch64_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
993 struct aarch64_prologue_cache
*cache
994 = aarch64_make_prologue_cache (this_frame
, this_cache
);
996 return cache
->prev_sp
- cache
->framesize
;
999 /* AArch64 default frame base information. */
1000 struct frame_base aarch64_normal_base
=
1002 &aarch64_prologue_unwind
,
1003 aarch64_normal_frame_base
,
1004 aarch64_normal_frame_base
,
1005 aarch64_normal_frame_base
1008 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1009 dummy frame. The frame ID's base needs to match the TOS value
1010 saved by save_dummy_frame_tos () and returned from
1011 aarch64_push_dummy_call, and the PC needs to match the dummy
1012 frame's breakpoint. */
1014 static struct frame_id
1015 aarch64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1017 return frame_id_build (get_frame_register_unsigned (this_frame
,
1019 get_frame_pc (this_frame
));
1022 /* Implement the "unwind_pc" gdbarch method. */
1025 aarch64_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1028 = frame_unwind_register_unsigned (this_frame
, AARCH64_PC_REGNUM
);
1033 /* Implement the "unwind_sp" gdbarch method. */
1036 aarch64_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1038 return frame_unwind_register_unsigned (this_frame
, AARCH64_SP_REGNUM
);
1041 /* Return the value of the REGNUM register in the previous frame of
1044 static struct value
*
1045 aarch64_dwarf2_prev_register (struct frame_info
*this_frame
,
1046 void **this_cache
, int regnum
)
1052 case AARCH64_PC_REGNUM
:
1053 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
1054 return frame_unwind_got_constant (this_frame
, regnum
, lr
);
1057 internal_error (__FILE__
, __LINE__
,
1058 _("Unexpected register %d"), regnum
);
1062 /* Implement the "init_reg" dwarf2_frame_ops method. */
1065 aarch64_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1066 struct dwarf2_frame_state_reg
*reg
,
1067 struct frame_info
*this_frame
)
1071 case AARCH64_PC_REGNUM
:
1072 reg
->how
= DWARF2_FRAME_REG_FN
;
1073 reg
->loc
.fn
= aarch64_dwarf2_prev_register
;
1075 case AARCH64_SP_REGNUM
:
1076 reg
->how
= DWARF2_FRAME_REG_CFA
;
1081 /* When arguments must be pushed onto the stack, they go on in reverse
1082 order. The code below implements a FILO (stack) to do this. */
1086 /* Value to pass on stack. It can be NULL if this item is for stack
1088 const gdb_byte
*data
;
1090 /* Size in bytes of value to pass on stack. */
1094 DEF_VEC_O (stack_item_t
);
1096 /* Return the alignment (in bytes) of the given type. */
1099 aarch64_type_align (struct type
*t
)
1105 t
= check_typedef (t
);
1106 switch (TYPE_CODE (t
))
1109 /* Should never happen. */
1110 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1114 case TYPE_CODE_ENUM
:
1118 case TYPE_CODE_RANGE
:
1119 case TYPE_CODE_BITSTRING
:
1121 case TYPE_CODE_RVALUE_REF
:
1122 case TYPE_CODE_CHAR
:
1123 case TYPE_CODE_BOOL
:
1124 return TYPE_LENGTH (t
);
1126 case TYPE_CODE_ARRAY
:
1127 if (TYPE_VECTOR (t
))
1129 /* Use the natural alignment for vector types (the same for
1130 scalar type), but the maximum alignment is 128-bit. */
1131 if (TYPE_LENGTH (t
) > 16)
1134 return TYPE_LENGTH (t
);
1137 return aarch64_type_align (TYPE_TARGET_TYPE (t
));
1138 case TYPE_CODE_COMPLEX
:
1139 return aarch64_type_align (TYPE_TARGET_TYPE (t
));
1141 case TYPE_CODE_STRUCT
:
1142 case TYPE_CODE_UNION
:
1144 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1146 falign
= aarch64_type_align (TYPE_FIELD_TYPE (t
, n
));
1154 /* Return 1 if *TY is a homogeneous floating-point aggregate or
1155 homogeneous short-vector aggregate as defined in the AAPCS64 ABI
1156 document; otherwise return 0. */
1159 is_hfa_or_hva (struct type
*ty
)
1161 switch (TYPE_CODE (ty
))
1163 case TYPE_CODE_ARRAY
:
1165 struct type
*target_ty
= TYPE_TARGET_TYPE (ty
);
1167 if (TYPE_VECTOR (ty
))
1170 if (TYPE_LENGTH (ty
) <= 4 /* HFA or HVA has at most 4 members. */
1171 && (TYPE_CODE (target_ty
) == TYPE_CODE_FLT
/* HFA */
1172 || (TYPE_CODE (target_ty
) == TYPE_CODE_ARRAY
/* HVA */
1173 && TYPE_VECTOR (target_ty
))))
1178 case TYPE_CODE_UNION
:
1179 case TYPE_CODE_STRUCT
:
1181 /* HFA or HVA has at most four members. */
1182 if (TYPE_NFIELDS (ty
) > 0 && TYPE_NFIELDS (ty
) <= 4)
1184 struct type
*member0_type
;
1186 member0_type
= check_typedef (TYPE_FIELD_TYPE (ty
, 0));
1187 if (TYPE_CODE (member0_type
) == TYPE_CODE_FLT
1188 || (TYPE_CODE (member0_type
) == TYPE_CODE_ARRAY
1189 && TYPE_VECTOR (member0_type
)))
1193 for (i
= 0; i
< TYPE_NFIELDS (ty
); i
++)
1195 struct type
*member1_type
;
1197 member1_type
= check_typedef (TYPE_FIELD_TYPE (ty
, i
));
1198 if (TYPE_CODE (member0_type
) != TYPE_CODE (member1_type
)
1199 || (TYPE_LENGTH (member0_type
)
1200 != TYPE_LENGTH (member1_type
)))
1216 /* Worker function for aapcs_is_vfp_call_or_return_candidate.
1218 Return the number of register required, or -1 on failure.
1220 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1221 to the element, else fail if the type of this element does not match the
1225 aapcs_is_vfp_call_or_return_candidate_1 (struct type
*type
,
1226 struct type
**fundamental_type
)
1228 if (type
== nullptr)
1231 switch (TYPE_CODE (type
))
1234 if (TYPE_LENGTH (type
) > 16)
1237 if (*fundamental_type
== nullptr)
1238 *fundamental_type
= type
;
1239 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1240 || TYPE_CODE (type
) != TYPE_CODE (*fundamental_type
))
1245 case TYPE_CODE_COMPLEX
:
1247 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (type
));
1248 if (TYPE_LENGTH (target_type
) > 16)
1251 if (*fundamental_type
== nullptr)
1252 *fundamental_type
= target_type
;
1253 else if (TYPE_LENGTH (target_type
) != TYPE_LENGTH (*fundamental_type
)
1254 || TYPE_CODE (target_type
) != TYPE_CODE (*fundamental_type
))
1260 case TYPE_CODE_ARRAY
:
1262 if (TYPE_VECTOR (type
))
1264 if (TYPE_LENGTH (type
) != 8 && TYPE_LENGTH (type
) != 16)
1267 if (*fundamental_type
== nullptr)
1268 *fundamental_type
= type
;
1269 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1270 || TYPE_CODE (type
) != TYPE_CODE (*fundamental_type
))
1277 struct type
*target_type
= TYPE_TARGET_TYPE (type
);
1278 int count
= aapcs_is_vfp_call_or_return_candidate_1
1279 (target_type
, fundamental_type
);
1284 count
*= TYPE_LENGTH (type
);
1289 case TYPE_CODE_STRUCT
:
1290 case TYPE_CODE_UNION
:
1294 for (int i
= 0; i
< TYPE_NFIELDS (type
); i
++)
1296 struct type
*member
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
1298 int sub_count
= aapcs_is_vfp_call_or_return_candidate_1
1299 (member
, fundamental_type
);
1300 if (sub_count
== -1)
1314 /* Return true if an argument, whose type is described by TYPE, can be passed or
1315 returned in simd/fp registers, providing enough parameter passing registers
1316 are available. This is as described in the AAPCS64.
1318 Upon successful return, *COUNT returns the number of needed registers,
1319 *FUNDAMENTAL_TYPE contains the type of those registers.
1321 Candidate as per the AAPCS64 5.4.2.C is either a:
1324 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1325 all the members are floats and has at most 4 members.
1326 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1327 all the members are short vectors and has at most 4 members.
1330 Note that HFAs and HVAs can include nested structures and arrays. */
1333 aapcs_is_vfp_call_or_return_candidate (struct type
*type
, int *count
,
1334 struct type
**fundamental_type
)
1336 if (type
== nullptr)
1339 *fundamental_type
= nullptr;
1341 int ag_count
= aapcs_is_vfp_call_or_return_candidate_1 (type
,
1344 if (ag_count
> 0 && ag_count
<= HA_MAX_NUM_FLDS
)
1353 /* AArch64 function call information structure. */
1354 struct aarch64_call_info
1356 /* the current argument number. */
1359 /* The next general purpose register number, equivalent to NGRN as
1360 described in the AArch64 Procedure Call Standard. */
1363 /* The next SIMD and floating point register number, equivalent to
1364 NSRN as described in the AArch64 Procedure Call Standard. */
1367 /* The next stacked argument address, equivalent to NSAA as
1368 described in the AArch64 Procedure Call Standard. */
1371 /* Stack item vector. */
1372 VEC(stack_item_t
) *si
;
1375 /* Pass a value in a sequence of consecutive X registers. The caller
1376 is responsbile for ensuring sufficient registers are available. */
1379 pass_in_x (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1380 struct aarch64_call_info
*info
, struct type
*type
,
1383 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1384 int len
= TYPE_LENGTH (type
);
1385 enum type_code typecode
= TYPE_CODE (type
);
1386 int regnum
= AARCH64_X0_REGNUM
+ info
->ngrn
;
1387 const bfd_byte
*buf
= value_contents (arg
);
1393 int partial_len
= len
< X_REGISTER_SIZE
? len
: X_REGISTER_SIZE
;
1394 CORE_ADDR regval
= extract_unsigned_integer (buf
, partial_len
,
1398 /* Adjust sub-word struct/union args when big-endian. */
1399 if (byte_order
== BFD_ENDIAN_BIG
1400 && partial_len
< X_REGISTER_SIZE
1401 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1402 regval
<<= ((X_REGISTER_SIZE
- partial_len
) * TARGET_CHAR_BIT
);
1406 debug_printf ("arg %d in %s = 0x%s\n", info
->argnum
,
1407 gdbarch_register_name (gdbarch
, regnum
),
1408 phex (regval
, X_REGISTER_SIZE
));
1410 regcache_cooked_write_unsigned (regcache
, regnum
, regval
);
1417 /* Attempt to marshall a value in a V register. Return 1 if
1418 successful, or 0 if insufficient registers are available. This
1419 function, unlike the equivalent pass_in_x() function does not
1420 handle arguments spread across multiple registers. */
1423 pass_in_v (struct gdbarch
*gdbarch
,
1424 struct regcache
*regcache
,
1425 struct aarch64_call_info
*info
,
1426 int len
, const bfd_byte
*buf
)
1430 int regnum
= AARCH64_V0_REGNUM
+ info
->nsrn
;
1431 gdb_byte reg
[V_REGISTER_SIZE
];
1436 memset (reg
, 0, sizeof (reg
));
1437 /* PCS C.1, the argument is allocated to the least significant
1438 bits of V register. */
1439 memcpy (reg
, buf
, len
);
1440 regcache
->cooked_write (regnum
, reg
);
1444 debug_printf ("arg %d in %s\n", info
->argnum
,
1445 gdbarch_register_name (gdbarch
, regnum
));
1453 /* Marshall an argument onto the stack. */
1456 pass_on_stack (struct aarch64_call_info
*info
, struct type
*type
,
1459 const bfd_byte
*buf
= value_contents (arg
);
1460 int len
= TYPE_LENGTH (type
);
1466 align
= aarch64_type_align (type
);
1468 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1469 Natural alignment of the argument's type. */
1470 align
= align_up (align
, 8);
1472 /* The AArch64 PCS requires at most doubleword alignment. */
1478 debug_printf ("arg %d len=%d @ sp + %d\n", info
->argnum
, len
,
1484 VEC_safe_push (stack_item_t
, info
->si
, &item
);
1487 if (info
->nsaa
& (align
- 1))
1489 /* Push stack alignment padding. */
1490 int pad
= align
- (info
->nsaa
& (align
- 1));
1495 VEC_safe_push (stack_item_t
, info
->si
, &item
);
1500 /* Marshall an argument into a sequence of one or more consecutive X
1501 registers or, if insufficient X registers are available then onto
1505 pass_in_x_or_stack (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1506 struct aarch64_call_info
*info
, struct type
*type
,
1509 int len
= TYPE_LENGTH (type
);
1510 int nregs
= (len
+ X_REGISTER_SIZE
- 1) / X_REGISTER_SIZE
;
1512 /* PCS C.13 - Pass in registers if we have enough spare */
1513 if (info
->ngrn
+ nregs
<= 8)
1515 pass_in_x (gdbarch
, regcache
, info
, type
, arg
);
1516 info
->ngrn
+= nregs
;
1521 pass_on_stack (info
, type
, arg
);
1525 /* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1526 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1527 registers. A return value of false is an error state as the value will have
1528 been partially passed to the stack. */
1530 pass_in_v_vfp_candidate (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1531 struct aarch64_call_info
*info
, struct type
*arg_type
,
1534 switch (TYPE_CODE (arg_type
))
1537 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1538 value_contents (arg
));
1541 case TYPE_CODE_COMPLEX
:
1543 const bfd_byte
*buf
= value_contents (arg
);
1544 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (arg_type
));
1546 if (!pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1550 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1551 buf
+ TYPE_LENGTH (target_type
));
1554 case TYPE_CODE_ARRAY
:
1555 if (TYPE_VECTOR (arg_type
))
1556 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1557 value_contents (arg
));
1560 case TYPE_CODE_STRUCT
:
1561 case TYPE_CODE_UNION
:
1562 for (int i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
1564 struct value
*field
= value_primitive_field (arg
, 0, i
, arg_type
);
1565 struct type
*field_type
= check_typedef (value_type (field
));
1567 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, info
, field_type
,
1578 /* Implement the "push_dummy_call" gdbarch method. */
1581 aarch64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1582 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1584 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1585 CORE_ADDR struct_addr
)
1588 struct aarch64_call_info info
;
1589 struct type
*func_type
;
1590 struct type
*return_type
;
1591 int lang_struct_return
;
1593 memset (&info
, 0, sizeof (info
));
1595 /* We need to know what the type of the called function is in order
1596 to determine the number of named/anonymous arguments for the
1597 actual argument placement, and the return type in order to handle
1598 return value correctly.
1600 The generic code above us views the decision of return in memory
1601 or return in registers as a two stage processes. The language
1602 handler is consulted first and may decide to return in memory (eg
1603 class with copy constructor returned by value), this will cause
1604 the generic code to allocate space AND insert an initial leading
1607 If the language code does not decide to pass in memory then the
1608 target code is consulted.
1610 If the language code decides to pass in memory we want to move
1611 the pointer inserted as the initial argument from the argument
1612 list and into X8, the conventional AArch64 struct return pointer
1615 This is slightly awkward, ideally the flag "lang_struct_return"
1616 would be passed to the targets implementation of push_dummy_call.
1617 Rather that change the target interface we call the language code
1618 directly ourselves. */
1620 func_type
= check_typedef (value_type (function
));
1622 /* Dereference function pointer types. */
1623 if (TYPE_CODE (func_type
) == TYPE_CODE_PTR
)
1624 func_type
= TYPE_TARGET_TYPE (func_type
);
1626 gdb_assert (TYPE_CODE (func_type
) == TYPE_CODE_FUNC
1627 || TYPE_CODE (func_type
) == TYPE_CODE_METHOD
);
1629 /* If language_pass_by_reference () returned true we will have been
1630 given an additional initial argument, a hidden pointer to the
1631 return slot in memory. */
1632 return_type
= TYPE_TARGET_TYPE (func_type
);
1633 lang_struct_return
= language_pass_by_reference (return_type
);
1635 /* Set the return address. For the AArch64, the return breakpoint
1636 is always at BP_ADDR. */
1637 regcache_cooked_write_unsigned (regcache
, AARCH64_LR_REGNUM
, bp_addr
);
1639 /* If we were given an initial argument for the return slot because
1640 lang_struct_return was true, lose it. */
1641 if (lang_struct_return
)
1647 /* The struct_return pointer occupies X8. */
1648 if (struct_return
|| lang_struct_return
)
1652 debug_printf ("struct return in %s = 0x%s\n",
1653 gdbarch_register_name (gdbarch
,
1654 AARCH64_STRUCT_RETURN_REGNUM
),
1655 paddress (gdbarch
, struct_addr
));
1657 regcache_cooked_write_unsigned (regcache
, AARCH64_STRUCT_RETURN_REGNUM
,
1661 for (argnum
= 0; argnum
< nargs
; argnum
++)
1663 struct value
*arg
= args
[argnum
];
1664 struct type
*arg_type
, *fundamental_type
;
1667 arg_type
= check_typedef (value_type (arg
));
1668 len
= TYPE_LENGTH (arg_type
);
1670 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1671 if there are enough spare registers. */
1672 if (aapcs_is_vfp_call_or_return_candidate (arg_type
, &elements
,
1675 if (info
.nsrn
+ elements
<= 8)
1677 /* We know that we have sufficient registers available therefore
1678 this will never need to fallback to the stack. */
1679 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, &info
, arg_type
,
1681 gdb_assert_not_reached ("Failed to push args");
1686 pass_on_stack (&info
, arg_type
, arg
);
1691 switch (TYPE_CODE (arg_type
))
1694 case TYPE_CODE_BOOL
:
1695 case TYPE_CODE_CHAR
:
1696 case TYPE_CODE_RANGE
:
1697 case TYPE_CODE_ENUM
:
1700 /* Promote to 32 bit integer. */
1701 if (TYPE_UNSIGNED (arg_type
))
1702 arg_type
= builtin_type (gdbarch
)->builtin_uint32
;
1704 arg_type
= builtin_type (gdbarch
)->builtin_int32
;
1705 arg
= value_cast (arg_type
, arg
);
1707 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1710 case TYPE_CODE_STRUCT
:
1711 case TYPE_CODE_ARRAY
:
1712 case TYPE_CODE_UNION
:
1715 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1716 invisible reference. */
1718 /* Allocate aligned storage. */
1719 sp
= align_down (sp
- len
, 16);
1721 /* Write the real data into the stack. */
1722 write_memory (sp
, value_contents (arg
), len
);
1724 /* Construct the indirection. */
1725 arg_type
= lookup_pointer_type (arg_type
);
1726 arg
= value_from_pointer (arg_type
, sp
);
1727 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1730 /* PCS C.15 / C.18 multiple values pass. */
1731 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1735 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1740 /* Make sure stack retains 16 byte alignment. */
1742 sp
-= 16 - (info
.nsaa
& 15);
1744 while (!VEC_empty (stack_item_t
, info
.si
))
1746 stack_item_t
*si
= VEC_last (stack_item_t
, info
.si
);
1749 if (si
->data
!= NULL
)
1750 write_memory (sp
, si
->data
, si
->len
);
1751 VEC_pop (stack_item_t
, info
.si
);
1754 VEC_free (stack_item_t
, info
.si
);
1756 /* Finally, update the SP register. */
1757 regcache_cooked_write_unsigned (regcache
, AARCH64_SP_REGNUM
, sp
);
1762 /* Implement the "frame_align" gdbarch method. */
1765 aarch64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1767 /* Align the stack to sixteen bytes. */
1768 return sp
& ~(CORE_ADDR
) 15;
1771 /* Return the type for an AdvSISD Q register. */
1773 static struct type
*
1774 aarch64_vnq_type (struct gdbarch
*gdbarch
)
1776 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1778 if (tdep
->vnq_type
== NULL
)
1783 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
1786 elem
= builtin_type (gdbarch
)->builtin_uint128
;
1787 append_composite_type_field (t
, "u", elem
);
1789 elem
= builtin_type (gdbarch
)->builtin_int128
;
1790 append_composite_type_field (t
, "s", elem
);
1795 return tdep
->vnq_type
;
1798 /* Return the type for an AdvSISD D register. */
1800 static struct type
*
1801 aarch64_vnd_type (struct gdbarch
*gdbarch
)
1803 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1805 if (tdep
->vnd_type
== NULL
)
1810 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
1813 elem
= builtin_type (gdbarch
)->builtin_double
;
1814 append_composite_type_field (t
, "f", elem
);
1816 elem
= builtin_type (gdbarch
)->builtin_uint64
;
1817 append_composite_type_field (t
, "u", elem
);
1819 elem
= builtin_type (gdbarch
)->builtin_int64
;
1820 append_composite_type_field (t
, "s", elem
);
1825 return tdep
->vnd_type
;
1828 /* Return the type for an AdvSISD S register. */
1830 static struct type
*
1831 aarch64_vns_type (struct gdbarch
*gdbarch
)
1833 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1835 if (tdep
->vns_type
== NULL
)
1840 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
1843 elem
= builtin_type (gdbarch
)->builtin_float
;
1844 append_composite_type_field (t
, "f", elem
);
1846 elem
= builtin_type (gdbarch
)->builtin_uint32
;
1847 append_composite_type_field (t
, "u", elem
);
1849 elem
= builtin_type (gdbarch
)->builtin_int32
;
1850 append_composite_type_field (t
, "s", elem
);
1855 return tdep
->vns_type
;
1858 /* Return the type for an AdvSISD H register. */
1860 static struct type
*
1861 aarch64_vnh_type (struct gdbarch
*gdbarch
)
1863 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1865 if (tdep
->vnh_type
== NULL
)
1870 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
1873 elem
= builtin_type (gdbarch
)->builtin_uint16
;
1874 append_composite_type_field (t
, "u", elem
);
1876 elem
= builtin_type (gdbarch
)->builtin_int16
;
1877 append_composite_type_field (t
, "s", elem
);
1882 return tdep
->vnh_type
;
1885 /* Return the type for an AdvSISD B register. */
1887 static struct type
*
1888 aarch64_vnb_type (struct gdbarch
*gdbarch
)
1890 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1892 if (tdep
->vnb_type
== NULL
)
1897 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
1900 elem
= builtin_type (gdbarch
)->builtin_uint8
;
1901 append_composite_type_field (t
, "u", elem
);
1903 elem
= builtin_type (gdbarch
)->builtin_int8
;
1904 append_composite_type_field (t
, "s", elem
);
1909 return tdep
->vnb_type
;
1912 /* Return the type for an AdvSISD V register. */
1914 static struct type
*
1915 aarch64_vnv_type (struct gdbarch
*gdbarch
)
1917 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1919 if (tdep
->vnv_type
== NULL
)
1921 struct type
*t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnv",
1924 append_composite_type_field (t
, "d", aarch64_vnd_type (gdbarch
));
1925 append_composite_type_field (t
, "s", aarch64_vns_type (gdbarch
));
1926 append_composite_type_field (t
, "h", aarch64_vnh_type (gdbarch
));
1927 append_composite_type_field (t
, "b", aarch64_vnb_type (gdbarch
));
1928 append_composite_type_field (t
, "q", aarch64_vnq_type (gdbarch
));
1933 return tdep
->vnv_type
;
1936 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
1939 aarch64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
1941 if (reg
>= AARCH64_DWARF_X0
&& reg
<= AARCH64_DWARF_X0
+ 30)
1942 return AARCH64_X0_REGNUM
+ reg
- AARCH64_DWARF_X0
;
1944 if (reg
== AARCH64_DWARF_SP
)
1945 return AARCH64_SP_REGNUM
;
1947 if (reg
>= AARCH64_DWARF_V0
&& reg
<= AARCH64_DWARF_V0
+ 31)
1948 return AARCH64_V0_REGNUM
+ reg
- AARCH64_DWARF_V0
;
1950 if (reg
== AARCH64_DWARF_SVE_VG
)
1951 return AARCH64_SVE_VG_REGNUM
;
1953 if (reg
== AARCH64_DWARF_SVE_FFR
)
1954 return AARCH64_SVE_FFR_REGNUM
;
1956 if (reg
>= AARCH64_DWARF_SVE_P0
&& reg
<= AARCH64_DWARF_SVE_P0
+ 15)
1957 return AARCH64_SVE_P0_REGNUM
+ reg
- AARCH64_DWARF_SVE_P0
;
1959 if (reg
>= AARCH64_DWARF_SVE_Z0
&& reg
<= AARCH64_DWARF_SVE_Z0
+ 15)
1960 return AARCH64_SVE_Z0_REGNUM
+ reg
- AARCH64_DWARF_SVE_Z0
;
1965 /* Implement the "print_insn" gdbarch method. */
1968 aarch64_gdb_print_insn (bfd_vma memaddr
, disassemble_info
*info
)
1970 info
->symbols
= NULL
;
1971 return default_print_insn (memaddr
, info
);
1974 /* AArch64 BRK software debug mode instruction.
1975 Note that AArch64 code is always little-endian.
1976 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
1977 constexpr gdb_byte aarch64_default_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
1979 typedef BP_MANIPULATION (aarch64_default_breakpoint
) aarch64_breakpoint
;
1981 /* Extract from an array REGS containing the (raw) register state a
1982 function return value of type TYPE, and copy that, in virtual
1983 format, into VALBUF. */
1986 aarch64_extract_return_value (struct type
*type
, struct regcache
*regs
,
1989 struct gdbarch
*gdbarch
= regs
->arch ();
1990 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1992 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1994 bfd_byte buf
[V_REGISTER_SIZE
];
1995 int len
= TYPE_LENGTH (type
);
1997 regs
->cooked_read (AARCH64_V0_REGNUM
, buf
);
1998 memcpy (valbuf
, buf
, len
);
2000 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2001 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2002 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2003 || TYPE_CODE (type
) == TYPE_CODE_PTR
2004 || TYPE_IS_REFERENCE (type
)
2005 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2007 /* If the the type is a plain integer, then the access is
2008 straight-forward. Otherwise we have to play around a bit
2010 int len
= TYPE_LENGTH (type
);
2011 int regno
= AARCH64_X0_REGNUM
;
2016 /* By using store_unsigned_integer we avoid having to do
2017 anything special for small big-endian values. */
2018 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2019 store_unsigned_integer (valbuf
,
2020 (len
> X_REGISTER_SIZE
2021 ? X_REGISTER_SIZE
: len
), byte_order
, tmp
);
2022 len
-= X_REGISTER_SIZE
;
2023 valbuf
+= X_REGISTER_SIZE
;
2026 else if (TYPE_CODE (type
) == TYPE_CODE_COMPLEX
)
2028 int regno
= AARCH64_V0_REGNUM
;
2029 bfd_byte buf
[V_REGISTER_SIZE
];
2030 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (type
));
2031 int len
= TYPE_LENGTH (target_type
);
2033 regs
->cooked_read (regno
, buf
);
2034 memcpy (valbuf
, buf
, len
);
2036 regs
->cooked_read (regno
+ 1, buf
);
2037 memcpy (valbuf
, buf
, len
);
2040 else if (is_hfa_or_hva (type
))
2042 int elements
= TYPE_NFIELDS (type
);
2043 struct type
*member_type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2044 int len
= TYPE_LENGTH (member_type
);
2047 for (i
= 0; i
< elements
; i
++)
2049 int regno
= AARCH64_V0_REGNUM
+ i
;
2050 bfd_byte buf
[V_REGISTER_SIZE
];
2054 debug_printf ("read HFA or HVA return value element %d from %s\n",
2056 gdbarch_register_name (gdbarch
, regno
));
2058 regs
->cooked_read (regno
, buf
);
2060 memcpy (valbuf
, buf
, len
);
2064 else if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)
2065 && (TYPE_LENGTH (type
) == 16 || TYPE_LENGTH (type
) == 8))
2067 /* Short vector is returned in V register. */
2068 gdb_byte buf
[V_REGISTER_SIZE
];
2070 regs
->cooked_read (AARCH64_V0_REGNUM
, buf
);
2071 memcpy (valbuf
, buf
, TYPE_LENGTH (type
));
2075 /* For a structure or union the behaviour is as if the value had
2076 been stored to word-aligned memory and then loaded into
2077 registers with 64-bit load instruction(s). */
2078 int len
= TYPE_LENGTH (type
);
2079 int regno
= AARCH64_X0_REGNUM
;
2080 bfd_byte buf
[X_REGISTER_SIZE
];
2084 regs
->cooked_read (regno
++, buf
);
2085 memcpy (valbuf
, buf
, len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2086 len
-= X_REGISTER_SIZE
;
2087 valbuf
+= X_REGISTER_SIZE
;
2093 /* Will a function return an aggregate type in memory or in a
2094 register? Return 0 if an aggregate type can be returned in a
2095 register, 1 if it must be returned in memory. */
2098 aarch64_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2100 type
= check_typedef (type
);
2102 if (is_hfa_or_hva (type
))
2104 /* v0-v7 are used to return values and one register is allocated
2105 for one member. However, HFA or HVA has at most four members. */
2109 if (TYPE_LENGTH (type
) > 16)
2111 /* PCS B.6 Aggregates larger than 16 bytes are passed by
2112 invisible reference. */
2120 /* Write into appropriate registers a function return value of type
2121 TYPE, given in virtual format. */
2124 aarch64_store_return_value (struct type
*type
, struct regcache
*regs
,
2125 const gdb_byte
*valbuf
)
2127 struct gdbarch
*gdbarch
= regs
->arch ();
2128 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2130 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2132 bfd_byte buf
[V_REGISTER_SIZE
];
2133 int len
= TYPE_LENGTH (type
);
2135 memcpy (buf
, valbuf
, len
> V_REGISTER_SIZE
? V_REGISTER_SIZE
: len
);
2136 regs
->cooked_write (AARCH64_V0_REGNUM
, buf
);
2138 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2139 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2140 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2141 || TYPE_CODE (type
) == TYPE_CODE_PTR
2142 || TYPE_IS_REFERENCE (type
)
2143 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2145 if (TYPE_LENGTH (type
) <= X_REGISTER_SIZE
)
2147 /* Values of one word or less are zero/sign-extended and
2149 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2150 LONGEST val
= unpack_long (type
, valbuf
);
2152 store_signed_integer (tmpbuf
, X_REGISTER_SIZE
, byte_order
, val
);
2153 regs
->cooked_write (AARCH64_X0_REGNUM
, tmpbuf
);
2157 /* Integral values greater than one word are stored in
2158 consecutive registers starting with r0. This will always
2159 be a multiple of the regiser size. */
2160 int len
= TYPE_LENGTH (type
);
2161 int regno
= AARCH64_X0_REGNUM
;
2165 regs
->cooked_write (regno
++, valbuf
);
2166 len
-= X_REGISTER_SIZE
;
2167 valbuf
+= X_REGISTER_SIZE
;
2171 else if (is_hfa_or_hva (type
))
2173 int elements
= TYPE_NFIELDS (type
);
2174 struct type
*member_type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
2175 int len
= TYPE_LENGTH (member_type
);
2178 for (i
= 0; i
< elements
; i
++)
2180 int regno
= AARCH64_V0_REGNUM
+ i
;
2181 bfd_byte tmpbuf
[V_REGISTER_SIZE
];
2185 debug_printf ("write HFA or HVA return value element %d to %s\n",
2187 gdbarch_register_name (gdbarch
, regno
));
2190 memcpy (tmpbuf
, valbuf
, len
);
2191 regs
->cooked_write (regno
, tmpbuf
);
2195 else if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)
2196 && (TYPE_LENGTH (type
) == 8 || TYPE_LENGTH (type
) == 16))
2199 gdb_byte buf
[V_REGISTER_SIZE
];
2201 memcpy (buf
, valbuf
, TYPE_LENGTH (type
));
2202 regs
->cooked_write (AARCH64_V0_REGNUM
, buf
);
2206 /* For a structure or union the behaviour is as if the value had
2207 been stored to word-aligned memory and then loaded into
2208 registers with 64-bit load instruction(s). */
2209 int len
= TYPE_LENGTH (type
);
2210 int regno
= AARCH64_X0_REGNUM
;
2211 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2215 memcpy (tmpbuf
, valbuf
,
2216 len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2217 regs
->cooked_write (regno
++, tmpbuf
);
2218 len
-= X_REGISTER_SIZE
;
2219 valbuf
+= X_REGISTER_SIZE
;
2224 /* Implement the "return_value" gdbarch method. */
2226 static enum return_value_convention
2227 aarch64_return_value (struct gdbarch
*gdbarch
, struct value
*func_value
,
2228 struct type
*valtype
, struct regcache
*regcache
,
2229 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2232 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2233 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2234 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2236 if (aarch64_return_in_memory (gdbarch
, valtype
))
2239 debug_printf ("return value in memory\n");
2240 return RETURN_VALUE_STRUCT_CONVENTION
;
2245 aarch64_store_return_value (valtype
, regcache
, writebuf
);
2248 aarch64_extract_return_value (valtype
, regcache
, readbuf
);
2251 debug_printf ("return value in registers\n");
2253 return RETURN_VALUE_REGISTER_CONVENTION
;
2256 /* Implement the "get_longjmp_target" gdbarch method. */
2259 aarch64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2262 gdb_byte buf
[X_REGISTER_SIZE
];
2263 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2264 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2265 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2267 jb_addr
= get_frame_register_unsigned (frame
, AARCH64_X0_REGNUM
);
2269 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2273 *pc
= extract_unsigned_integer (buf
, X_REGISTER_SIZE
, byte_order
);
2277 /* Implement the "gen_return_address" gdbarch method. */
2280 aarch64_gen_return_address (struct gdbarch
*gdbarch
,
2281 struct agent_expr
*ax
, struct axs_value
*value
,
2284 value
->type
= register_type (gdbarch
, AARCH64_LR_REGNUM
);
2285 value
->kind
= axs_lvalue_register
;
2286 value
->u
.reg
= AARCH64_LR_REGNUM
;
2290 /* Return the pseudo register name corresponding to register regnum. */
2293 aarch64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
2295 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2297 static const char *const q_name
[] =
2299 "q0", "q1", "q2", "q3",
2300 "q4", "q5", "q6", "q7",
2301 "q8", "q9", "q10", "q11",
2302 "q12", "q13", "q14", "q15",
2303 "q16", "q17", "q18", "q19",
2304 "q20", "q21", "q22", "q23",
2305 "q24", "q25", "q26", "q27",
2306 "q28", "q29", "q30", "q31",
2309 static const char *const d_name
[] =
2311 "d0", "d1", "d2", "d3",
2312 "d4", "d5", "d6", "d7",
2313 "d8", "d9", "d10", "d11",
2314 "d12", "d13", "d14", "d15",
2315 "d16", "d17", "d18", "d19",
2316 "d20", "d21", "d22", "d23",
2317 "d24", "d25", "d26", "d27",
2318 "d28", "d29", "d30", "d31",
2321 static const char *const s_name
[] =
2323 "s0", "s1", "s2", "s3",
2324 "s4", "s5", "s6", "s7",
2325 "s8", "s9", "s10", "s11",
2326 "s12", "s13", "s14", "s15",
2327 "s16", "s17", "s18", "s19",
2328 "s20", "s21", "s22", "s23",
2329 "s24", "s25", "s26", "s27",
2330 "s28", "s29", "s30", "s31",
2333 static const char *const h_name
[] =
2335 "h0", "h1", "h2", "h3",
2336 "h4", "h5", "h6", "h7",
2337 "h8", "h9", "h10", "h11",
2338 "h12", "h13", "h14", "h15",
2339 "h16", "h17", "h18", "h19",
2340 "h20", "h21", "h22", "h23",
2341 "h24", "h25", "h26", "h27",
2342 "h28", "h29", "h30", "h31",
2345 static const char *const b_name
[] =
2347 "b0", "b1", "b2", "b3",
2348 "b4", "b5", "b6", "b7",
2349 "b8", "b9", "b10", "b11",
2350 "b12", "b13", "b14", "b15",
2351 "b16", "b17", "b18", "b19",
2352 "b20", "b21", "b22", "b23",
2353 "b24", "b25", "b26", "b27",
2354 "b28", "b29", "b30", "b31",
2357 regnum
-= gdbarch_num_regs (gdbarch
);
2359 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2360 return q_name
[regnum
- AARCH64_Q0_REGNUM
];
2362 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2363 return d_name
[regnum
- AARCH64_D0_REGNUM
];
2365 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2366 return s_name
[regnum
- AARCH64_S0_REGNUM
];
2368 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2369 return h_name
[regnum
- AARCH64_H0_REGNUM
];
2371 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2372 return b_name
[regnum
- AARCH64_B0_REGNUM
];
2374 if (tdep
->has_sve ())
2376 static const char *const sve_v_name
[] =
2378 "v0", "v1", "v2", "v3",
2379 "v4", "v5", "v6", "v7",
2380 "v8", "v9", "v10", "v11",
2381 "v12", "v13", "v14", "v15",
2382 "v16", "v17", "v18", "v19",
2383 "v20", "v21", "v22", "v23",
2384 "v24", "v25", "v26", "v27",
2385 "v28", "v29", "v30", "v31",
2388 if (regnum
>= AARCH64_SVE_V0_REGNUM
2389 && regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2390 return sve_v_name
[regnum
- AARCH64_SVE_V0_REGNUM
];
2393 internal_error (__FILE__
, __LINE__
,
2394 _("aarch64_pseudo_register_name: bad register number %d"),
2398 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
2400 static struct type
*
2401 aarch64_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2403 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2405 regnum
-= gdbarch_num_regs (gdbarch
);
2407 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2408 return aarch64_vnq_type (gdbarch
);
2410 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2411 return aarch64_vnd_type (gdbarch
);
2413 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2414 return aarch64_vns_type (gdbarch
);
2416 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2417 return aarch64_vnh_type (gdbarch
);
2419 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2420 return aarch64_vnb_type (gdbarch
);
2422 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2423 && regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2424 return aarch64_vnv_type (gdbarch
);
2426 internal_error (__FILE__
, __LINE__
,
2427 _("aarch64_pseudo_register_type: bad register number %d"),
2431 /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2434 aarch64_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2435 struct reggroup
*group
)
2437 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2439 regnum
-= gdbarch_num_regs (gdbarch
);
2441 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2442 return group
== all_reggroup
|| group
== vector_reggroup
;
2443 else if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2444 return (group
== all_reggroup
|| group
== vector_reggroup
2445 || group
== float_reggroup
);
2446 else if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2447 return (group
== all_reggroup
|| group
== vector_reggroup
2448 || group
== float_reggroup
);
2449 else if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2450 return group
== all_reggroup
|| group
== vector_reggroup
;
2451 else if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2452 return group
== all_reggroup
|| group
== vector_reggroup
;
2453 else if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2454 && regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2455 return group
== all_reggroup
|| group
== vector_reggroup
;
2457 return group
== all_reggroup
;
2460 /* Helper for aarch64_pseudo_read_value. */
2462 static struct value
*
2463 aarch64_pseudo_read_value_1 (struct gdbarch
*gdbarch
,
2464 readable_regcache
*regcache
, int regnum_offset
,
2465 int regsize
, struct value
*result_value
)
2467 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2469 /* Enough space for a full vector register. */
2470 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2471 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2473 if (regcache
->raw_read (v_regnum
, reg_buf
) != REG_VALID
)
2474 mark_value_bytes_unavailable (result_value
, 0,
2475 TYPE_LENGTH (value_type (result_value
)));
2477 memcpy (value_contents_raw (result_value
), reg_buf
, regsize
);
2479 return result_value
;
2482 /* Implement the "pseudo_register_read_value" gdbarch method. */
2484 static struct value
*
2485 aarch64_pseudo_read_value (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2488 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2489 struct value
*result_value
= allocate_value (register_type (gdbarch
, regnum
));
2491 VALUE_LVAL (result_value
) = lval_register
;
2492 VALUE_REGNUM (result_value
) = regnum
;
2494 regnum
-= gdbarch_num_regs (gdbarch
);
2496 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2497 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2498 regnum
- AARCH64_Q0_REGNUM
,
2499 Q_REGISTER_SIZE
, result_value
);
2501 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2502 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2503 regnum
- AARCH64_D0_REGNUM
,
2504 D_REGISTER_SIZE
, result_value
);
2506 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2507 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2508 regnum
- AARCH64_S0_REGNUM
,
2509 S_REGISTER_SIZE
, result_value
);
2511 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2512 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2513 regnum
- AARCH64_H0_REGNUM
,
2514 H_REGISTER_SIZE
, result_value
);
2516 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2517 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2518 regnum
- AARCH64_B0_REGNUM
,
2519 B_REGISTER_SIZE
, result_value
);
2521 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2522 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2523 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2524 regnum
- AARCH64_SVE_V0_REGNUM
,
2525 V_REGISTER_SIZE
, result_value
);
2527 gdb_assert_not_reached ("regnum out of bound");
2530 /* Helper for aarch64_pseudo_write. */
2533 aarch64_pseudo_write_1 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2534 int regnum_offset
, int regsize
, const gdb_byte
*buf
)
2536 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2538 /* Enough space for a full vector register. */
2539 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2540 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2542 /* Ensure the register buffer is zero, we want gdb writes of the
2543 various 'scalar' pseudo registers to behavior like architectural
2544 writes, register width bytes are written the remainder are set to
2546 memset (reg_buf
, 0, register_size (gdbarch
, AARCH64_V0_REGNUM
));
2548 memcpy (reg_buf
, buf
, regsize
);
2549 regcache
->raw_write (v_regnum
, reg_buf
);
2552 /* Implement the "pseudo_register_write" gdbarch method. */
2555 aarch64_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2556 int regnum
, const gdb_byte
*buf
)
2558 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2559 regnum
-= gdbarch_num_regs (gdbarch
);
2561 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2562 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2563 regnum
- AARCH64_Q0_REGNUM
, Q_REGISTER_SIZE
,
2566 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2567 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2568 regnum
- AARCH64_D0_REGNUM
, D_REGISTER_SIZE
,
2571 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2572 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2573 regnum
- AARCH64_S0_REGNUM
, S_REGISTER_SIZE
,
2576 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2577 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2578 regnum
- AARCH64_H0_REGNUM
, H_REGISTER_SIZE
,
2581 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2582 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2583 regnum
- AARCH64_B0_REGNUM
, B_REGISTER_SIZE
,
2586 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2587 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2588 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2589 regnum
- AARCH64_SVE_V0_REGNUM
,
2590 V_REGISTER_SIZE
, buf
);
2592 gdb_assert_not_reached ("regnum out of bound");
2595 /* Callback function for user_reg_add. */
2597 static struct value
*
2598 value_of_aarch64_user_reg (struct frame_info
*frame
, const void *baton
)
2600 const int *reg_p
= (const int *) baton
;
2602 return value_of_register (*reg_p
, frame
);
2606 /* Implement the "software_single_step" gdbarch method, needed to
2607 single step through atomic sequences on AArch64. */
2609 static std::vector
<CORE_ADDR
>
2610 aarch64_software_single_step (struct regcache
*regcache
)
2612 struct gdbarch
*gdbarch
= regcache
->arch ();
2613 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2614 const int insn_size
= 4;
2615 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2616 CORE_ADDR pc
= regcache_read_pc (regcache
);
2617 CORE_ADDR breaks
[2] = { CORE_ADDR_MAX
, CORE_ADDR_MAX
};
2619 CORE_ADDR closing_insn
= 0;
2620 uint32_t insn
= read_memory_unsigned_integer (loc
, insn_size
,
2621 byte_order_for_code
);
2624 int bc_insn_count
= 0; /* Conditional branch instruction count. */
2625 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2628 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2631 /* Look for a Load Exclusive instruction which begins the sequence. */
2632 if (inst
.opcode
->iclass
!= ldstexcl
|| bit (insn
, 22) == 0)
2635 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2638 insn
= read_memory_unsigned_integer (loc
, insn_size
,
2639 byte_order_for_code
);
2641 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2643 /* Check if the instruction is a conditional branch. */
2644 if (inst
.opcode
->iclass
== condbranch
)
2646 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_ADDR_PCREL19
);
2648 if (bc_insn_count
>= 1)
2651 /* It is, so we'll try to set a breakpoint at the destination. */
2652 breaks
[1] = loc
+ inst
.operands
[0].imm
.value
;
2658 /* Look for the Store Exclusive which closes the atomic sequence. */
2659 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22) == 0)
2666 /* We didn't find a closing Store Exclusive instruction, fall back. */
2670 /* Insert breakpoint after the end of the atomic sequence. */
2671 breaks
[0] = loc
+ insn_size
;
2673 /* Check for duplicated breakpoints, and also check that the second
2674 breakpoint is not within the atomic sequence. */
2676 && (breaks
[1] == breaks
[0]
2677 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
2678 last_breakpoint
= 0;
2680 std::vector
<CORE_ADDR
> next_pcs
;
2682 /* Insert the breakpoint at the end of the sequence, and one at the
2683 destination of the conditional branch, if it exists. */
2684 for (index
= 0; index
<= last_breakpoint
; index
++)
2685 next_pcs
.push_back (breaks
[index
]);
2690 struct aarch64_displaced_step_closure
: public displaced_step_closure
2692 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2693 is being displaced stepping. */
2696 /* PC adjustment offset after displaced stepping. */
2697 int32_t pc_adjust
= 0;
2700 /* Data when visiting instructions for displaced stepping. */
2702 struct aarch64_displaced_step_data
2704 struct aarch64_insn_data base
;
2706 /* The address where the instruction will be executed at. */
2708 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2709 uint32_t insn_buf
[DISPLACED_MODIFIED_INSNS
];
2710 /* Number of instructions in INSN_BUF. */
2711 unsigned insn_count
;
2712 /* Registers when doing displaced stepping. */
2713 struct regcache
*regs
;
2715 aarch64_displaced_step_closure
*dsc
;
2718 /* Implementation of aarch64_insn_visitor method "b". */
2721 aarch64_displaced_step_b (const int is_bl
, const int32_t offset
,
2722 struct aarch64_insn_data
*data
)
2724 struct aarch64_displaced_step_data
*dsd
2725 = (struct aarch64_displaced_step_data
*) data
;
2726 int64_t new_offset
= data
->insn_addr
- dsd
->new_addr
+ offset
;
2728 if (can_encode_int32 (new_offset
, 28))
2730 /* Emit B rather than BL, because executing BL on a new address
2731 will get the wrong address into LR. In order to avoid this,
2732 we emit B, and update LR if the instruction is BL. */
2733 emit_b (dsd
->insn_buf
, 0, new_offset
);
2739 emit_nop (dsd
->insn_buf
);
2741 dsd
->dsc
->pc_adjust
= offset
;
2747 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_LR_REGNUM
,
2748 data
->insn_addr
+ 4);
2752 /* Implementation of aarch64_insn_visitor method "b_cond". */
2755 aarch64_displaced_step_b_cond (const unsigned cond
, const int32_t offset
,
2756 struct aarch64_insn_data
*data
)
2758 struct aarch64_displaced_step_data
*dsd
2759 = (struct aarch64_displaced_step_data
*) data
;
2761 /* GDB has to fix up PC after displaced step this instruction
2762 differently according to the condition is true or false. Instead
2763 of checking COND against conditional flags, we can use
2764 the following instructions, and GDB can tell how to fix up PC
2765 according to the PC value.
2767 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2773 emit_bcond (dsd
->insn_buf
, cond
, 8);
2775 dsd
->dsc
->pc_adjust
= offset
;
2776 dsd
->insn_count
= 1;
2779 /* Dynamically allocate a new register. If we know the register
2780 statically, we should make it a global as above instead of using this
2783 static struct aarch64_register
2784 aarch64_register (unsigned num
, int is64
)
2786 return (struct aarch64_register
) { num
, is64
};
2789 /* Implementation of aarch64_insn_visitor method "cb". */
2792 aarch64_displaced_step_cb (const int32_t offset
, const int is_cbnz
,
2793 const unsigned rn
, int is64
,
2794 struct aarch64_insn_data
*data
)
2796 struct aarch64_displaced_step_data
*dsd
2797 = (struct aarch64_displaced_step_data
*) data
;
2799 /* The offset is out of range for a compare and branch
2800 instruction. We can use the following instructions instead:
2802 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2807 emit_cb (dsd
->insn_buf
, is_cbnz
, aarch64_register (rn
, is64
), 8);
2808 dsd
->insn_count
= 1;
2810 dsd
->dsc
->pc_adjust
= offset
;
2813 /* Implementation of aarch64_insn_visitor method "tb". */
2816 aarch64_displaced_step_tb (const int32_t offset
, int is_tbnz
,
2817 const unsigned rt
, unsigned bit
,
2818 struct aarch64_insn_data
*data
)
2820 struct aarch64_displaced_step_data
*dsd
2821 = (struct aarch64_displaced_step_data
*) data
;
2823 /* The offset is out of range for a test bit and branch
2824 instruction We can use the following instructions instead:
2826 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2832 emit_tb (dsd
->insn_buf
, is_tbnz
, bit
, aarch64_register (rt
, 1), 8);
2833 dsd
->insn_count
= 1;
2835 dsd
->dsc
->pc_adjust
= offset
;
2838 /* Implementation of aarch64_insn_visitor method "adr". */
2841 aarch64_displaced_step_adr (const int32_t offset
, const unsigned rd
,
2842 const int is_adrp
, struct aarch64_insn_data
*data
)
2844 struct aarch64_displaced_step_data
*dsd
2845 = (struct aarch64_displaced_step_data
*) data
;
2846 /* We know exactly the address the ADR{P,} instruction will compute.
2847 We can just write it to the destination register. */
2848 CORE_ADDR address
= data
->insn_addr
+ offset
;
2852 /* Clear the lower 12 bits of the offset to get the 4K page. */
2853 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
2857 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
2860 dsd
->dsc
->pc_adjust
= 4;
2861 emit_nop (dsd
->insn_buf
);
2862 dsd
->insn_count
= 1;
2865 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
2868 aarch64_displaced_step_ldr_literal (const int32_t offset
, const int is_sw
,
2869 const unsigned rt
, const int is64
,
2870 struct aarch64_insn_data
*data
)
2872 struct aarch64_displaced_step_data
*dsd
2873 = (struct aarch64_displaced_step_data
*) data
;
2874 CORE_ADDR address
= data
->insn_addr
+ offset
;
2875 struct aarch64_memory_operand zero
= { MEMORY_OPERAND_OFFSET
, 0 };
2877 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rt
,
2881 dsd
->insn_count
= emit_ldrsw (dsd
->insn_buf
, aarch64_register (rt
, 1),
2882 aarch64_register (rt
, 1), zero
);
2884 dsd
->insn_count
= emit_ldr (dsd
->insn_buf
, aarch64_register (rt
, is64
),
2885 aarch64_register (rt
, 1), zero
);
2887 dsd
->dsc
->pc_adjust
= 4;
2890 /* Implementation of aarch64_insn_visitor method "others". */
2893 aarch64_displaced_step_others (const uint32_t insn
,
2894 struct aarch64_insn_data
*data
)
2896 struct aarch64_displaced_step_data
*dsd
2897 = (struct aarch64_displaced_step_data
*) data
;
2899 aarch64_emit_insn (dsd
->insn_buf
, insn
);
2900 dsd
->insn_count
= 1;
2902 if ((insn
& 0xfffffc1f) == 0xd65f0000)
2905 dsd
->dsc
->pc_adjust
= 0;
2908 dsd
->dsc
->pc_adjust
= 4;
2911 static const struct aarch64_insn_visitor visitor
=
2913 aarch64_displaced_step_b
,
2914 aarch64_displaced_step_b_cond
,
2915 aarch64_displaced_step_cb
,
2916 aarch64_displaced_step_tb
,
2917 aarch64_displaced_step_adr
,
2918 aarch64_displaced_step_ldr_literal
,
2919 aarch64_displaced_step_others
,
2922 /* Implement the "displaced_step_copy_insn" gdbarch method. */
2924 struct displaced_step_closure
*
2925 aarch64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
2926 CORE_ADDR from
, CORE_ADDR to
,
2927 struct regcache
*regs
)
2929 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2930 uint32_t insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
2931 struct aarch64_displaced_step_data dsd
;
2934 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2937 /* Look for a Load Exclusive instruction which begins the sequence. */
2938 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22))
2940 /* We can't displaced step atomic sequences. */
2944 std::unique_ptr
<aarch64_displaced_step_closure
> dsc
2945 (new aarch64_displaced_step_closure
);
2946 dsd
.base
.insn_addr
= from
;
2949 dsd
.dsc
= dsc
.get ();
2951 aarch64_relocate_instruction (insn
, &visitor
,
2952 (struct aarch64_insn_data
*) &dsd
);
2953 gdb_assert (dsd
.insn_count
<= DISPLACED_MODIFIED_INSNS
);
2955 if (dsd
.insn_count
!= 0)
2959 /* Instruction can be relocated to scratch pad. Copy
2960 relocated instruction(s) there. */
2961 for (i
= 0; i
< dsd
.insn_count
; i
++)
2963 if (debug_displaced
)
2965 debug_printf ("displaced: writing insn ");
2966 debug_printf ("%.8x", dsd
.insn_buf
[i
]);
2967 debug_printf (" at %s\n", paddress (gdbarch
, to
+ i
* 4));
2969 write_memory_unsigned_integer (to
+ i
* 4, 4, byte_order_for_code
,
2970 (ULONGEST
) dsd
.insn_buf
[i
]);
2978 return dsc
.release ();
2981 /* Implement the "displaced_step_fixup" gdbarch method. */
2984 aarch64_displaced_step_fixup (struct gdbarch
*gdbarch
,
2985 struct displaced_step_closure
*dsc_
,
2986 CORE_ADDR from
, CORE_ADDR to
,
2987 struct regcache
*regs
)
2989 aarch64_displaced_step_closure
*dsc
= (aarch64_displaced_step_closure
*) dsc_
;
2995 regcache_cooked_read_unsigned (regs
, AARCH64_PC_REGNUM
, &pc
);
2998 /* Condition is true. */
3000 else if (pc
- to
== 4)
3002 /* Condition is false. */
3006 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
3009 if (dsc
->pc_adjust
!= 0)
3011 if (debug_displaced
)
3013 debug_printf ("displaced: fixup: set PC to %s:%d\n",
3014 paddress (gdbarch
, from
), dsc
->pc_adjust
);
3016 regcache_cooked_write_unsigned (regs
, AARCH64_PC_REGNUM
,
3017 from
+ dsc
->pc_adjust
);
3021 /* Implement the "displaced_step_hw_singlestep" gdbarch method. */
3024 aarch64_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
3025 struct displaced_step_closure
*closure
)
3030 /* Get the correct target description for the given VQ value.
3031 If VQ is zero then it is assumed SVE is not supported.
3032 (It is not possible to set VQ to zero on an SVE system). */
3035 aarch64_read_description (uint64_t vq
)
3037 if (vq
> AARCH64_MAX_SVE_VQ
)
3038 error (_("VQ is %" PRIu64
", maximum supported value is %d"), vq
,
3039 AARCH64_MAX_SVE_VQ
);
3041 struct target_desc
*tdesc
= tdesc_aarch64_list
[vq
];
3045 tdesc
= aarch64_create_target_description (vq
);
3046 tdesc_aarch64_list
[vq
] = tdesc
;
3052 /* Return the VQ used when creating the target description TDESC. */
3055 aarch64_get_tdesc_vq (const struct target_desc
*tdesc
)
3057 const struct tdesc_feature
*feature_sve
;
3059 if (!tdesc_has_registers (tdesc
))
3062 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3064 if (feature_sve
== nullptr)
3067 uint64_t vl
= tdesc_register_bitsize (feature_sve
,
3068 aarch64_sve_register_names
[0]) / 8;
3069 return sve_vq_from_vl (vl
);
3073 /* Initialize the current architecture based on INFO. If possible,
3074 re-use an architecture from ARCHES, which is a list of
3075 architectures already created during this debugging session.
3077 Called e.g. at program startup, when reading a core file, and when
3078 reading a binary file. */
3080 static struct gdbarch
*
3081 aarch64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3083 struct gdbarch_tdep
*tdep
;
3084 struct gdbarch
*gdbarch
;
3085 struct gdbarch_list
*best_arch
;
3086 struct tdesc_arch_data
*tdesc_data
= NULL
;
3087 const struct target_desc
*tdesc
= info
.target_desc
;
3090 const struct tdesc_feature
*feature_core
;
3091 const struct tdesc_feature
*feature_fpu
;
3092 const struct tdesc_feature
*feature_sve
;
3094 int num_pseudo_regs
= 0;
3096 /* Ensure we always have a target description. */
3097 if (!tdesc_has_registers (tdesc
))
3098 tdesc
= aarch64_read_description (0);
3101 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.core");
3102 feature_fpu
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.fpu");
3103 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3105 if (feature_core
== NULL
)
3108 tdesc_data
= tdesc_data_alloc ();
3110 /* Validate the description provides the mandatory core R registers
3111 and allocate their numbers. */
3112 for (i
= 0; i
< ARRAY_SIZE (aarch64_r_register_names
); i
++)
3113 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
,
3114 AARCH64_X0_REGNUM
+ i
,
3115 aarch64_r_register_names
[i
]);
3117 num_regs
= AARCH64_X0_REGNUM
+ i
;
3119 /* Add the V registers. */
3120 if (feature_fpu
!= NULL
)
3122 if (feature_sve
!= NULL
)
3123 error (_("Program contains both fpu and SVE features."));
3125 /* Validate the description provides the mandatory V registers
3126 and allocate their numbers. */
3127 for (i
= 0; i
< ARRAY_SIZE (aarch64_v_register_names
); i
++)
3128 valid_p
&= tdesc_numbered_register (feature_fpu
, tdesc_data
,
3129 AARCH64_V0_REGNUM
+ i
,
3130 aarch64_v_register_names
[i
]);
3132 num_regs
= AARCH64_V0_REGNUM
+ i
;
3135 /* Add the SVE registers. */
3136 if (feature_sve
!= NULL
)
3138 /* Validate the description provides the mandatory SVE registers
3139 and allocate their numbers. */
3140 for (i
= 0; i
< ARRAY_SIZE (aarch64_sve_register_names
); i
++)
3141 valid_p
&= tdesc_numbered_register (feature_sve
, tdesc_data
,
3142 AARCH64_SVE_Z0_REGNUM
+ i
,
3143 aarch64_sve_register_names
[i
]);
3145 num_regs
= AARCH64_SVE_Z0_REGNUM
+ i
;
3146 num_pseudo_regs
+= 32; /* add the Vn register pseudos. */
3149 if (feature_fpu
!= NULL
|| feature_sve
!= NULL
)
3151 num_pseudo_regs
+= 32; /* add the Qn scalar register pseudos */
3152 num_pseudo_regs
+= 32; /* add the Dn scalar register pseudos */
3153 num_pseudo_regs
+= 32; /* add the Sn scalar register pseudos */
3154 num_pseudo_regs
+= 32; /* add the Hn scalar register pseudos */
3155 num_pseudo_regs
+= 32; /* add the Bn scalar register pseudos */
3160 tdesc_data_cleanup (tdesc_data
);
3164 /* AArch64 code is always little-endian. */
3165 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
3167 /* If there is already a candidate, use it. */
3168 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
3170 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
3172 /* Found a match. */
3176 if (best_arch
!= NULL
)
3178 if (tdesc_data
!= NULL
)
3179 tdesc_data_cleanup (tdesc_data
);
3180 return best_arch
->gdbarch
;
3183 tdep
= XCNEW (struct gdbarch_tdep
);
3184 gdbarch
= gdbarch_alloc (&info
, tdep
);
3186 /* This should be low enough for everything. */
3187 tdep
->lowest_pc
= 0x20;
3188 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
3189 tdep
->jb_elt_size
= 8;
3190 tdep
->vq
= aarch64_get_tdesc_vq (tdesc
);
3192 set_gdbarch_push_dummy_call (gdbarch
, aarch64_push_dummy_call
);
3193 set_gdbarch_frame_align (gdbarch
, aarch64_frame_align
);
3195 /* Frame handling. */
3196 set_gdbarch_dummy_id (gdbarch
, aarch64_dummy_id
);
3197 set_gdbarch_unwind_pc (gdbarch
, aarch64_unwind_pc
);
3198 set_gdbarch_unwind_sp (gdbarch
, aarch64_unwind_sp
);
3200 /* Advance PC across function entry code. */
3201 set_gdbarch_skip_prologue (gdbarch
, aarch64_skip_prologue
);
3203 /* The stack grows downward. */
3204 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3206 /* Breakpoint manipulation. */
3207 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
3208 aarch64_breakpoint::kind_from_pc
);
3209 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
3210 aarch64_breakpoint::bp_from_kind
);
3211 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3212 set_gdbarch_software_single_step (gdbarch
, aarch64_software_single_step
);
3214 /* Information about registers, etc. */
3215 set_gdbarch_sp_regnum (gdbarch
, AARCH64_SP_REGNUM
);
3216 set_gdbarch_pc_regnum (gdbarch
, AARCH64_PC_REGNUM
);
3217 set_gdbarch_num_regs (gdbarch
, num_regs
);
3219 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudo_regs
);
3220 set_gdbarch_pseudo_register_read_value (gdbarch
, aarch64_pseudo_read_value
);
3221 set_gdbarch_pseudo_register_write (gdbarch
, aarch64_pseudo_write
);
3222 set_tdesc_pseudo_register_name (gdbarch
, aarch64_pseudo_register_name
);
3223 set_tdesc_pseudo_register_type (gdbarch
, aarch64_pseudo_register_type
);
3224 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3225 aarch64_pseudo_register_reggroup_p
);
3228 set_gdbarch_short_bit (gdbarch
, 16);
3229 set_gdbarch_int_bit (gdbarch
, 32);
3230 set_gdbarch_float_bit (gdbarch
, 32);
3231 set_gdbarch_double_bit (gdbarch
, 64);
3232 set_gdbarch_long_double_bit (gdbarch
, 128);
3233 set_gdbarch_long_bit (gdbarch
, 64);
3234 set_gdbarch_long_long_bit (gdbarch
, 64);
3235 set_gdbarch_ptr_bit (gdbarch
, 64);
3236 set_gdbarch_char_signed (gdbarch
, 0);
3237 set_gdbarch_wchar_signed (gdbarch
, 0);
3238 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3239 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3240 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
3242 /* Internal <-> external register number maps. */
3243 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, aarch64_dwarf_reg_to_regnum
);
3245 /* Returning results. */
3246 set_gdbarch_return_value (gdbarch
, aarch64_return_value
);
3249 set_gdbarch_print_insn (gdbarch
, aarch64_gdb_print_insn
);
3251 /* Virtual tables. */
3252 set_gdbarch_vbit_in_delta (gdbarch
, 1);
3254 /* Hook in the ABI-specific overrides, if they have been registered. */
3255 info
.target_desc
= tdesc
;
3256 info
.tdesc_data
= tdesc_data
;
3257 gdbarch_init_osabi (info
, gdbarch
);
3259 dwarf2_frame_set_init_reg (gdbarch
, aarch64_dwarf2_frame_init_reg
);
3261 /* Add some default predicates. */
3262 frame_unwind_append_unwinder (gdbarch
, &aarch64_stub_unwind
);
3263 dwarf2_append_unwinders (gdbarch
);
3264 frame_unwind_append_unwinder (gdbarch
, &aarch64_prologue_unwind
);
3266 frame_base_set_default (gdbarch
, &aarch64_normal_base
);
3268 /* Now we have tuned the configuration, set a few final things,
3269 based on what the OS ABI has told us. */
3271 if (tdep
->jb_pc
>= 0)
3272 set_gdbarch_get_longjmp_target (gdbarch
, aarch64_get_longjmp_target
);
3274 set_gdbarch_gen_return_address (gdbarch
, aarch64_gen_return_address
);
3276 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
3278 /* Add standard register aliases. */
3279 for (i
= 0; i
< ARRAY_SIZE (aarch64_register_aliases
); i
++)
3280 user_reg_add (gdbarch
, aarch64_register_aliases
[i
].name
,
3281 value_of_aarch64_user_reg
,
3282 &aarch64_register_aliases
[i
].regnum
);
3288 aarch64_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3290 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3295 fprintf_unfiltered (file
, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3296 paddress (gdbarch
, tdep
->lowest_pc
));
3302 static void aarch64_process_record_test (void);
3307 _initialize_aarch64_tdep (void)
3309 gdbarch_register (bfd_arch_aarch64
, aarch64_gdbarch_init
,
3312 /* Debug this file's internals. */
3313 add_setshow_boolean_cmd ("aarch64", class_maintenance
, &aarch64_debug
, _("\
3314 Set AArch64 debugging."), _("\
3315 Show AArch64 debugging."), _("\
3316 When on, AArch64 specific debugging is enabled."),
3319 &setdebuglist
, &showdebuglist
);
3322 selftests::register_test ("aarch64-analyze-prologue",
3323 selftests::aarch64_analyze_prologue_test
);
3324 selftests::register_test ("aarch64-process-record",
3325 selftests::aarch64_process_record_test
);
3326 selftests::record_xml_tdesc ("aarch64.xml",
3327 aarch64_create_target_description (0));
3331 /* AArch64 process record-replay related structures, defines etc. */
3333 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3336 unsigned int reg_len = LENGTH; \
3339 REGS = XNEWVEC (uint32_t, reg_len); \
3340 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3345 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3348 unsigned int mem_len = LENGTH; \
3351 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3352 memcpy(&MEMS->len, &RECORD_BUF[0], \
3353 sizeof(struct aarch64_mem_r) * LENGTH); \
3358 /* AArch64 record/replay structures and enumerations. */
3360 struct aarch64_mem_r
3362 uint64_t len
; /* Record length. */
3363 uint64_t addr
; /* Memory address. */
3366 enum aarch64_record_result
3368 AARCH64_RECORD_SUCCESS
,
3369 AARCH64_RECORD_UNSUPPORTED
,
3370 AARCH64_RECORD_UNKNOWN
3373 typedef struct insn_decode_record_t
3375 struct gdbarch
*gdbarch
;
3376 struct regcache
*regcache
;
3377 CORE_ADDR this_addr
; /* Address of insn to be recorded. */
3378 uint32_t aarch64_insn
; /* Insn to be recorded. */
3379 uint32_t mem_rec_count
; /* Count of memory records. */
3380 uint32_t reg_rec_count
; /* Count of register records. */
3381 uint32_t *aarch64_regs
; /* Registers to be recorded. */
3382 struct aarch64_mem_r
*aarch64_mems
; /* Memory locations to be recorded. */
3383 } insn_decode_record
;
3385 /* Record handler for data processing - register instructions. */
3388 aarch64_record_data_proc_reg (insn_decode_record
*aarch64_insn_r
)
3390 uint8_t reg_rd
, insn_bits24_27
, insn_bits21_23
;
3391 uint32_t record_buf
[4];
3393 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3394 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3395 insn_bits21_23
= bits (aarch64_insn_r
->aarch64_insn
, 21, 23);
3397 if (!bit (aarch64_insn_r
->aarch64_insn
, 28))
3401 /* Logical (shifted register). */
3402 if (insn_bits24_27
== 0x0a)
3403 setflags
= (bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03);
3405 else if (insn_bits24_27
== 0x0b)
3406 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3408 return AARCH64_RECORD_UNKNOWN
;
3410 record_buf
[0] = reg_rd
;
3411 aarch64_insn_r
->reg_rec_count
= 1;
3413 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3417 if (insn_bits24_27
== 0x0b)
3419 /* Data-processing (3 source). */
3420 record_buf
[0] = reg_rd
;
3421 aarch64_insn_r
->reg_rec_count
= 1;
3423 else if (insn_bits24_27
== 0x0a)
3425 if (insn_bits21_23
== 0x00)
3427 /* Add/subtract (with carry). */
3428 record_buf
[0] = reg_rd
;
3429 aarch64_insn_r
->reg_rec_count
= 1;
3430 if (bit (aarch64_insn_r
->aarch64_insn
, 29))
3432 record_buf
[1] = AARCH64_CPSR_REGNUM
;
3433 aarch64_insn_r
->reg_rec_count
= 2;
3436 else if (insn_bits21_23
== 0x02)
3438 /* Conditional compare (register) and conditional compare
3439 (immediate) instructions. */
3440 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3441 aarch64_insn_r
->reg_rec_count
= 1;
3443 else if (insn_bits21_23
== 0x04 || insn_bits21_23
== 0x06)
3445 /* CConditional select. */
3446 /* Data-processing (2 source). */
3447 /* Data-processing (1 source). */
3448 record_buf
[0] = reg_rd
;
3449 aarch64_insn_r
->reg_rec_count
= 1;
3452 return AARCH64_RECORD_UNKNOWN
;
3456 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3458 return AARCH64_RECORD_SUCCESS
;
3461 /* Record handler for data processing - immediate instructions. */
3464 aarch64_record_data_proc_imm (insn_decode_record
*aarch64_insn_r
)
3466 uint8_t reg_rd
, insn_bit23
, insn_bits24_27
, setflags
;
3467 uint32_t record_buf
[4];
3469 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3470 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3471 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3473 if (insn_bits24_27
== 0x00 /* PC rel addressing. */
3474 || insn_bits24_27
== 0x03 /* Bitfield and Extract. */
3475 || (insn_bits24_27
== 0x02 && insn_bit23
)) /* Move wide (immediate). */
3477 record_buf
[0] = reg_rd
;
3478 aarch64_insn_r
->reg_rec_count
= 1;
3480 else if (insn_bits24_27
== 0x01)
3482 /* Add/Subtract (immediate). */
3483 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3484 record_buf
[0] = reg_rd
;
3485 aarch64_insn_r
->reg_rec_count
= 1;
3487 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3489 else if (insn_bits24_27
== 0x02 && !insn_bit23
)
3491 /* Logical (immediate). */
3492 setflags
= bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03;
3493 record_buf
[0] = reg_rd
;
3494 aarch64_insn_r
->reg_rec_count
= 1;
3496 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3499 return AARCH64_RECORD_UNKNOWN
;
3501 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3503 return AARCH64_RECORD_SUCCESS
;
3506 /* Record handler for branch, exception generation and system instructions. */
3509 aarch64_record_branch_except_sys (insn_decode_record
*aarch64_insn_r
)
3511 struct gdbarch_tdep
*tdep
= gdbarch_tdep (aarch64_insn_r
->gdbarch
);
3512 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits22_23
;
3513 uint32_t record_buf
[4];
3515 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3516 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
3517 insn_bits22_23
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3519 if (insn_bits28_31
== 0x0d)
3521 /* Exception generation instructions. */
3522 if (insn_bits24_27
== 0x04)
3524 if (!bits (aarch64_insn_r
->aarch64_insn
, 2, 4)
3525 && !bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
3526 && bits (aarch64_insn_r
->aarch64_insn
, 0, 1) == 0x01)
3528 ULONGEST svc_number
;
3530 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, 8,
3532 return tdep
->aarch64_syscall_record (aarch64_insn_r
->regcache
,
3536 return AARCH64_RECORD_UNSUPPORTED
;
3538 /* System instructions. */
3539 else if (insn_bits24_27
== 0x05 && insn_bits22_23
== 0x00)
3541 uint32_t reg_rt
, reg_crn
;
3543 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3544 reg_crn
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3546 /* Record rt in case of sysl and mrs instructions. */
3547 if (bit (aarch64_insn_r
->aarch64_insn
, 21))
3549 record_buf
[0] = reg_rt
;
3550 aarch64_insn_r
->reg_rec_count
= 1;
3552 /* Record cpsr for hint and msr(immediate) instructions. */
3553 else if (reg_crn
== 0x02 || reg_crn
== 0x04)
3555 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3556 aarch64_insn_r
->reg_rec_count
= 1;
3559 /* Unconditional branch (register). */
3560 else if((insn_bits24_27
& 0x0e) == 0x06)
3562 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3563 if (bits (aarch64_insn_r
->aarch64_insn
, 21, 22) == 0x01)
3564 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3567 return AARCH64_RECORD_UNKNOWN
;
3569 /* Unconditional branch (immediate). */
3570 else if ((insn_bits28_31
& 0x07) == 0x01 && (insn_bits24_27
& 0x0c) == 0x04)
3572 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3573 if (bit (aarch64_insn_r
->aarch64_insn
, 31))
3574 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3577 /* Compare & branch (immediate), Test & branch (immediate) and
3578 Conditional branch (immediate). */
3579 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3581 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3583 return AARCH64_RECORD_SUCCESS
;
3586 /* Record handler for advanced SIMD load and store instructions. */
3589 aarch64_record_asimd_load_store (insn_decode_record
*aarch64_insn_r
)
3592 uint64_t addr_offset
= 0;
3593 uint32_t record_buf
[24];
3594 uint64_t record_buf_mem
[24];
3595 uint32_t reg_rn
, reg_rt
;
3596 uint32_t reg_index
= 0, mem_index
= 0;
3597 uint8_t opcode_bits
, size_bits
;
3599 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3600 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3601 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3602 opcode_bits
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3603 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
, &address
);
3606 debug_printf ("Process record: Advanced SIMD load/store\n");
3608 /* Load/store single structure. */
3609 if (bit (aarch64_insn_r
->aarch64_insn
, 24))
3611 uint8_t sindex
, scale
, selem
, esize
, replicate
= 0;
3612 scale
= opcode_bits
>> 2;
3613 selem
= ((opcode_bits
& 0x02) |
3614 bit (aarch64_insn_r
->aarch64_insn
, 21)) + 1;
3618 if (size_bits
& 0x01)
3619 return AARCH64_RECORD_UNKNOWN
;
3622 if ((size_bits
>> 1) & 0x01)
3623 return AARCH64_RECORD_UNKNOWN
;
3624 if (size_bits
& 0x01)
3626 if (!((opcode_bits
>> 1) & 0x01))
3629 return AARCH64_RECORD_UNKNOWN
;
3633 if (bit (aarch64_insn_r
->aarch64_insn
, 22) && !(opcode_bits
& 0x01))
3640 return AARCH64_RECORD_UNKNOWN
;
3646 for (sindex
= 0; sindex
< selem
; sindex
++)
3648 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3649 reg_rt
= (reg_rt
+ 1) % 32;
3653 for (sindex
= 0; sindex
< selem
; sindex
++)
3655 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3656 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3659 record_buf_mem
[mem_index
++] = esize
/ 8;
3660 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3662 addr_offset
= addr_offset
+ (esize
/ 8);
3663 reg_rt
= (reg_rt
+ 1) % 32;
3667 /* Load/store multiple structure. */
3670 uint8_t selem
, esize
, rpt
, elements
;
3671 uint8_t eindex
, rindex
;
3673 esize
= 8 << size_bits
;
3674 if (bit (aarch64_insn_r
->aarch64_insn
, 30))
3675 elements
= 128 / esize
;
3677 elements
= 64 / esize
;
3679 switch (opcode_bits
)
3681 /*LD/ST4 (4 Registers). */
3686 /*LD/ST1 (4 Registers). */
3691 /*LD/ST3 (3 Registers). */
3696 /*LD/ST1 (3 Registers). */
3701 /*LD/ST1 (1 Register). */
3706 /*LD/ST2 (2 Registers). */
3711 /*LD/ST1 (2 Registers). */
3717 return AARCH64_RECORD_UNSUPPORTED
;
3720 for (rindex
= 0; rindex
< rpt
; rindex
++)
3721 for (eindex
= 0; eindex
< elements
; eindex
++)
3723 uint8_t reg_tt
, sindex
;
3724 reg_tt
= (reg_rt
+ rindex
) % 32;
3725 for (sindex
= 0; sindex
< selem
; sindex
++)
3727 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3728 record_buf
[reg_index
++] = reg_tt
+ AARCH64_V0_REGNUM
;
3731 record_buf_mem
[mem_index
++] = esize
/ 8;
3732 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3734 addr_offset
= addr_offset
+ (esize
/ 8);
3735 reg_tt
= (reg_tt
+ 1) % 32;
3740 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
3741 record_buf
[reg_index
++] = reg_rn
;
3743 aarch64_insn_r
->reg_rec_count
= reg_index
;
3744 aarch64_insn_r
->mem_rec_count
= mem_index
/ 2;
3745 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
3747 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3749 return AARCH64_RECORD_SUCCESS
;
3752 /* Record handler for load and store instructions. */
3755 aarch64_record_load_store (insn_decode_record
*aarch64_insn_r
)
3757 uint8_t insn_bits24_27
, insn_bits28_29
, insn_bits10_11
;
3758 uint8_t insn_bit23
, insn_bit21
;
3759 uint8_t opc
, size_bits
, ld_flag
, vector_flag
;
3760 uint32_t reg_rn
, reg_rt
, reg_rt2
;
3761 uint64_t datasize
, offset
;
3762 uint32_t record_buf
[8];
3763 uint64_t record_buf_mem
[8];
3766 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3767 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3768 insn_bits28_29
= bits (aarch64_insn_r
->aarch64_insn
, 28, 29);
3769 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
3770 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3771 ld_flag
= bit (aarch64_insn_r
->aarch64_insn
, 22);
3772 vector_flag
= bit (aarch64_insn_r
->aarch64_insn
, 26);
3773 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3774 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3775 reg_rt2
= bits (aarch64_insn_r
->aarch64_insn
, 10, 14);
3776 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 30, 31);
3778 /* Load/store exclusive. */
3779 if (insn_bits24_27
== 0x08 && insn_bits28_29
== 0x00)
3782 debug_printf ("Process record: load/store exclusive\n");
3786 record_buf
[0] = reg_rt
;
3787 aarch64_insn_r
->reg_rec_count
= 1;
3790 record_buf
[1] = reg_rt2
;
3791 aarch64_insn_r
->reg_rec_count
= 2;
3797 datasize
= (8 << size_bits
) * 2;
3799 datasize
= (8 << size_bits
);
3800 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3802 record_buf_mem
[0] = datasize
/ 8;
3803 record_buf_mem
[1] = address
;
3804 aarch64_insn_r
->mem_rec_count
= 1;
3807 /* Save register rs. */
3808 record_buf
[0] = bits (aarch64_insn_r
->aarch64_insn
, 16, 20);
3809 aarch64_insn_r
->reg_rec_count
= 1;
3813 /* Load register (literal) instructions decoding. */
3814 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x01)
3817 debug_printf ("Process record: load register (literal)\n");
3819 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3821 record_buf
[0] = reg_rt
;
3822 aarch64_insn_r
->reg_rec_count
= 1;
3824 /* All types of load/store pair instructions decoding. */
3825 else if ((insn_bits24_27
& 0x0a) == 0x08 && insn_bits28_29
== 0x02)
3828 debug_printf ("Process record: load/store pair\n");
3834 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3835 record_buf
[1] = reg_rt2
+ AARCH64_V0_REGNUM
;
3839 record_buf
[0] = reg_rt
;
3840 record_buf
[1] = reg_rt2
;
3842 aarch64_insn_r
->reg_rec_count
= 2;
3847 imm7_off
= bits (aarch64_insn_r
->aarch64_insn
, 15, 21);
3849 size_bits
= size_bits
>> 1;
3850 datasize
= 8 << (2 + size_bits
);
3851 offset
= (imm7_off
& 0x40) ? (~imm7_off
& 0x007f) + 1 : imm7_off
;
3852 offset
= offset
<< (2 + size_bits
);
3853 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3855 if (!((insn_bits24_27
& 0x0b) == 0x08 && insn_bit23
))
3857 if (imm7_off
& 0x40)
3858 address
= address
- offset
;
3860 address
= address
+ offset
;
3863 record_buf_mem
[0] = datasize
/ 8;
3864 record_buf_mem
[1] = address
;
3865 record_buf_mem
[2] = datasize
/ 8;
3866 record_buf_mem
[3] = address
+ (datasize
/ 8);
3867 aarch64_insn_r
->mem_rec_count
= 2;
3869 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
3870 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
3872 /* Load/store register (unsigned immediate) instructions. */
3873 else if ((insn_bits24_27
& 0x0b) == 0x09 && insn_bits28_29
== 0x03)
3875 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3885 if (size_bits
== 0x3 && vector_flag
== 0x0 && opc
== 0x2)
3887 /* PRFM (immediate) */
3888 return AARCH64_RECORD_SUCCESS
;
3890 else if (size_bits
== 0x2 && vector_flag
== 0x0 && opc
== 0x2)
3892 /* LDRSW (immediate) */
3906 debug_printf ("Process record: load/store (unsigned immediate):"
3907 " size %x V %d opc %x\n", size_bits
, vector_flag
,
3913 offset
= bits (aarch64_insn_r
->aarch64_insn
, 10, 21);
3914 datasize
= 8 << size_bits
;
3915 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3917 offset
= offset
<< size_bits
;
3918 address
= address
+ offset
;
3920 record_buf_mem
[0] = datasize
>> 3;
3921 record_buf_mem
[1] = address
;
3922 aarch64_insn_r
->mem_rec_count
= 1;
3927 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3929 record_buf
[0] = reg_rt
;
3930 aarch64_insn_r
->reg_rec_count
= 1;
3933 /* Load/store register (register offset) instructions. */
3934 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
3935 && insn_bits10_11
== 0x02 && insn_bit21
)
3938 debug_printf ("Process record: load/store (register offset)\n");
3939 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3946 if (size_bits
!= 0x03)
3949 return AARCH64_RECORD_UNKNOWN
;
3953 ULONGEST reg_rm_val
;
3955 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
,
3956 bits (aarch64_insn_r
->aarch64_insn
, 16, 20), ®_rm_val
);
3957 if (bit (aarch64_insn_r
->aarch64_insn
, 12))
3958 offset
= reg_rm_val
<< size_bits
;
3960 offset
= reg_rm_val
;
3961 datasize
= 8 << size_bits
;
3962 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3964 address
= address
+ offset
;
3965 record_buf_mem
[0] = datasize
>> 3;
3966 record_buf_mem
[1] = address
;
3967 aarch64_insn_r
->mem_rec_count
= 1;
3972 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3974 record_buf
[0] = reg_rt
;
3975 aarch64_insn_r
->reg_rec_count
= 1;
3978 /* Load/store register (immediate and unprivileged) instructions. */
3979 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
3984 debug_printf ("Process record: load/store "
3985 "(immediate and unprivileged)\n");
3987 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3994 if (size_bits
!= 0x03)
3997 return AARCH64_RECORD_UNKNOWN
;
4002 imm9_off
= bits (aarch64_insn_r
->aarch64_insn
, 12, 20);
4003 offset
= (imm9_off
& 0x0100) ? (((~imm9_off
) & 0x01ff) + 1) : imm9_off
;
4004 datasize
= 8 << size_bits
;
4005 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4007 if (insn_bits10_11
!= 0x01)
4009 if (imm9_off
& 0x0100)
4010 address
= address
- offset
;
4012 address
= address
+ offset
;
4014 record_buf_mem
[0] = datasize
>> 3;
4015 record_buf_mem
[1] = address
;
4016 aarch64_insn_r
->mem_rec_count
= 1;
4021 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4023 record_buf
[0] = reg_rt
;
4024 aarch64_insn_r
->reg_rec_count
= 1;
4026 if (insn_bits10_11
== 0x01 || insn_bits10_11
== 0x03)
4027 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
4029 /* Advanced SIMD load/store instructions. */
4031 return aarch64_record_asimd_load_store (aarch64_insn_r
);
4033 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
4035 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4037 return AARCH64_RECORD_SUCCESS
;
4040 /* Record handler for data processing SIMD and floating point instructions. */
4043 aarch64_record_data_proc_simd_fp (insn_decode_record
*aarch64_insn_r
)
4045 uint8_t insn_bit21
, opcode
, rmode
, reg_rd
;
4046 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits10_11
, insn_bits12_15
;
4047 uint8_t insn_bits11_14
;
4048 uint32_t record_buf
[2];
4050 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
4051 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
4052 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
4053 insn_bits12_15
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
4054 insn_bits11_14
= bits (aarch64_insn_r
->aarch64_insn
, 11, 14);
4055 opcode
= bits (aarch64_insn_r
->aarch64_insn
, 16, 18);
4056 rmode
= bits (aarch64_insn_r
->aarch64_insn
, 19, 20);
4057 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
4058 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
4061 debug_printf ("Process record: data processing SIMD/FP: ");
4063 if ((insn_bits28_31
& 0x05) == 0x01 && insn_bits24_27
== 0x0e)
4065 /* Floating point - fixed point conversion instructions. */
4069 debug_printf ("FP - fixed point conversion");
4071 if ((opcode
>> 1) == 0x0 && rmode
== 0x03)
4072 record_buf
[0] = reg_rd
;
4074 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4076 /* Floating point - conditional compare instructions. */
4077 else if (insn_bits10_11
== 0x01)
4080 debug_printf ("FP - conditional compare");
4082 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4084 /* Floating point - data processing (2-source) and
4085 conditional select instructions. */
4086 else if (insn_bits10_11
== 0x02 || insn_bits10_11
== 0x03)
4089 debug_printf ("FP - DP (2-source)");
4091 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4093 else if (insn_bits10_11
== 0x00)
4095 /* Floating point - immediate instructions. */
4096 if ((insn_bits12_15
& 0x01) == 0x01
4097 || (insn_bits12_15
& 0x07) == 0x04)
4100 debug_printf ("FP - immediate");
4101 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4103 /* Floating point - compare instructions. */
4104 else if ((insn_bits12_15
& 0x03) == 0x02)
4107 debug_printf ("FP - immediate");
4108 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4110 /* Floating point - integer conversions instructions. */
4111 else if (insn_bits12_15
== 0x00)
4113 /* Convert float to integer instruction. */
4114 if (!(opcode
>> 1) || ((opcode
>> 1) == 0x02 && !rmode
))
4117 debug_printf ("float to int conversion");
4119 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4121 /* Convert integer to float instruction. */
4122 else if ((opcode
>> 1) == 0x01 && !rmode
)
4125 debug_printf ("int to float conversion");
4127 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4129 /* Move float to integer instruction. */
4130 else if ((opcode
>> 1) == 0x03)
4133 debug_printf ("move float to int");
4135 if (!(opcode
& 0x01))
4136 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4138 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4141 return AARCH64_RECORD_UNKNOWN
;
4144 return AARCH64_RECORD_UNKNOWN
;
4147 return AARCH64_RECORD_UNKNOWN
;
4149 else if ((insn_bits28_31
& 0x09) == 0x00 && insn_bits24_27
== 0x0e)
4152 debug_printf ("SIMD copy");
4154 /* Advanced SIMD copy instructions. */
4155 if (!bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
4156 && !bit (aarch64_insn_r
->aarch64_insn
, 15)
4157 && bit (aarch64_insn_r
->aarch64_insn
, 10))
4159 if (insn_bits11_14
== 0x05 || insn_bits11_14
== 0x07)
4160 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4162 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4165 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4167 /* All remaining floating point or advanced SIMD instructions. */
4171 debug_printf ("all remain");
4173 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4177 debug_printf ("\n");
4179 aarch64_insn_r
->reg_rec_count
++;
4180 gdb_assert (aarch64_insn_r
->reg_rec_count
== 1);
4181 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4183 return AARCH64_RECORD_SUCCESS
;
4186 /* Decodes insns type and invokes its record handler. */
4189 aarch64_record_decode_insn_handler (insn_decode_record
*aarch64_insn_r
)
4191 uint32_t ins_bit25
, ins_bit26
, ins_bit27
, ins_bit28
;
4193 ins_bit25
= bit (aarch64_insn_r
->aarch64_insn
, 25);
4194 ins_bit26
= bit (aarch64_insn_r
->aarch64_insn
, 26);
4195 ins_bit27
= bit (aarch64_insn_r
->aarch64_insn
, 27);
4196 ins_bit28
= bit (aarch64_insn_r
->aarch64_insn
, 28);
4198 /* Data processing - immediate instructions. */
4199 if (!ins_bit26
&& !ins_bit27
&& ins_bit28
)
4200 return aarch64_record_data_proc_imm (aarch64_insn_r
);
4202 /* Branch, exception generation and system instructions. */
4203 if (ins_bit26
&& !ins_bit27
&& ins_bit28
)
4204 return aarch64_record_branch_except_sys (aarch64_insn_r
);
4206 /* Load and store instructions. */
4207 if (!ins_bit25
&& ins_bit27
)
4208 return aarch64_record_load_store (aarch64_insn_r
);
4210 /* Data processing - register instructions. */
4211 if (ins_bit25
&& !ins_bit26
&& ins_bit27
)
4212 return aarch64_record_data_proc_reg (aarch64_insn_r
);
4214 /* Data processing - SIMD and floating point instructions. */
4215 if (ins_bit25
&& ins_bit26
&& ins_bit27
)
4216 return aarch64_record_data_proc_simd_fp (aarch64_insn_r
);
4218 return AARCH64_RECORD_UNSUPPORTED
;
4221 /* Cleans up local record registers and memory allocations. */
4224 deallocate_reg_mem (insn_decode_record
*record
)
4226 xfree (record
->aarch64_regs
);
4227 xfree (record
->aarch64_mems
);
4231 namespace selftests
{
4234 aarch64_process_record_test (void)
4236 struct gdbarch_info info
;
4239 gdbarch_info_init (&info
);
4240 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
4242 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
4243 SELF_CHECK (gdbarch
!= NULL
);
4245 insn_decode_record aarch64_record
;
4247 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4248 aarch64_record
.regcache
= NULL
;
4249 aarch64_record
.this_addr
= 0;
4250 aarch64_record
.gdbarch
= gdbarch
;
4252 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4253 aarch64_record
.aarch64_insn
= 0xf9800020;
4254 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4255 SELF_CHECK (ret
== AARCH64_RECORD_SUCCESS
);
4256 SELF_CHECK (aarch64_record
.reg_rec_count
== 0);
4257 SELF_CHECK (aarch64_record
.mem_rec_count
== 0);
4259 deallocate_reg_mem (&aarch64_record
);
4262 } // namespace selftests
4263 #endif /* GDB_SELF_TEST */
4265 /* Parse the current instruction and record the values of the registers and
4266 memory that will be changed in current instruction to record_arch_list
4267 return -1 if something is wrong. */
4270 aarch64_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4271 CORE_ADDR insn_addr
)
4273 uint32_t rec_no
= 0;
4274 uint8_t insn_size
= 4;
4276 gdb_byte buf
[insn_size
];
4277 insn_decode_record aarch64_record
;
4279 memset (&buf
[0], 0, insn_size
);
4280 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4281 target_read_memory (insn_addr
, &buf
[0], insn_size
);
4282 aarch64_record
.aarch64_insn
4283 = (uint32_t) extract_unsigned_integer (&buf
[0],
4285 gdbarch_byte_order (gdbarch
));
4286 aarch64_record
.regcache
= regcache
;
4287 aarch64_record
.this_addr
= insn_addr
;
4288 aarch64_record
.gdbarch
= gdbarch
;
4290 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4291 if (ret
== AARCH64_RECORD_UNSUPPORTED
)
4293 printf_unfiltered (_("Process record does not support instruction "
4294 "0x%0x at address %s.\n"),
4295 aarch64_record
.aarch64_insn
,
4296 paddress (gdbarch
, insn_addr
));
4302 /* Record registers. */
4303 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4305 /* Always record register CPSR. */
4306 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4307 AARCH64_CPSR_REGNUM
);
4308 if (aarch64_record
.aarch64_regs
)
4309 for (rec_no
= 0; rec_no
< aarch64_record
.reg_rec_count
; rec_no
++)
4310 if (record_full_arch_list_add_reg (aarch64_record
.regcache
,
4311 aarch64_record
.aarch64_regs
[rec_no
]))
4314 /* Record memories. */
4315 if (aarch64_record
.aarch64_mems
)
4316 for (rec_no
= 0; rec_no
< aarch64_record
.mem_rec_count
; rec_no
++)
4317 if (record_full_arch_list_add_mem
4318 ((CORE_ADDR
)aarch64_record
.aarch64_mems
[rec_no
].addr
,
4319 aarch64_record
.aarch64_mems
[rec_no
].len
))
4322 if (record_full_arch_list_add_end ())
4326 deallocate_reg_mem (&aarch64_record
);