1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "reggroups.h"
31 #include "arch-utils.h"
33 #include "frame-unwind.h"
34 #include "frame-base.h"
35 #include "trad-frame.h"
37 #include "dwarf2-frame.h"
39 #include "prologue-value.h"
40 #include "target-descriptions.h"
41 #include "user-regs.h"
48 #include "aarch64-tdep.h"
51 #include "elf/aarch64.h"
56 #include "record-full.h"
57 #include "arch/aarch64-insn.h"
59 #include "opcode/aarch64.h"
62 #define submask(x) ((1L << ((x) + 1)) - 1)
63 #define bit(obj,st) (((obj) >> (st)) & 1)
64 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
66 /* Pseudo register base numbers. */
67 #define AARCH64_Q0_REGNUM 0
68 #define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + AARCH64_D_REGISTER_COUNT)
69 #define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32)
70 #define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
71 #define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
73 /* All possible aarch64 target descriptors. */
74 struct target_desc
*tdesc_aarch64_list
[AARCH64_MAX_SVE_VQ
+ 1];
76 /* The standard register names, and all the valid aliases for them. */
79 const char *const name
;
81 } aarch64_register_aliases
[] =
83 /* 64-bit register names. */
84 {"fp", AARCH64_FP_REGNUM
},
85 {"lr", AARCH64_LR_REGNUM
},
86 {"sp", AARCH64_SP_REGNUM
},
88 /* 32-bit register names. */
89 {"w0", AARCH64_X0_REGNUM
+ 0},
90 {"w1", AARCH64_X0_REGNUM
+ 1},
91 {"w2", AARCH64_X0_REGNUM
+ 2},
92 {"w3", AARCH64_X0_REGNUM
+ 3},
93 {"w4", AARCH64_X0_REGNUM
+ 4},
94 {"w5", AARCH64_X0_REGNUM
+ 5},
95 {"w6", AARCH64_X0_REGNUM
+ 6},
96 {"w7", AARCH64_X0_REGNUM
+ 7},
97 {"w8", AARCH64_X0_REGNUM
+ 8},
98 {"w9", AARCH64_X0_REGNUM
+ 9},
99 {"w10", AARCH64_X0_REGNUM
+ 10},
100 {"w11", AARCH64_X0_REGNUM
+ 11},
101 {"w12", AARCH64_X0_REGNUM
+ 12},
102 {"w13", AARCH64_X0_REGNUM
+ 13},
103 {"w14", AARCH64_X0_REGNUM
+ 14},
104 {"w15", AARCH64_X0_REGNUM
+ 15},
105 {"w16", AARCH64_X0_REGNUM
+ 16},
106 {"w17", AARCH64_X0_REGNUM
+ 17},
107 {"w18", AARCH64_X0_REGNUM
+ 18},
108 {"w19", AARCH64_X0_REGNUM
+ 19},
109 {"w20", AARCH64_X0_REGNUM
+ 20},
110 {"w21", AARCH64_X0_REGNUM
+ 21},
111 {"w22", AARCH64_X0_REGNUM
+ 22},
112 {"w23", AARCH64_X0_REGNUM
+ 23},
113 {"w24", AARCH64_X0_REGNUM
+ 24},
114 {"w25", AARCH64_X0_REGNUM
+ 25},
115 {"w26", AARCH64_X0_REGNUM
+ 26},
116 {"w27", AARCH64_X0_REGNUM
+ 27},
117 {"w28", AARCH64_X0_REGNUM
+ 28},
118 {"w29", AARCH64_X0_REGNUM
+ 29},
119 {"w30", AARCH64_X0_REGNUM
+ 30},
122 {"ip0", AARCH64_X0_REGNUM
+ 16},
123 {"ip1", AARCH64_X0_REGNUM
+ 17}
126 /* The required core 'R' registers. */
127 static const char *const aarch64_r_register_names
[] =
129 /* These registers must appear in consecutive RAW register number
130 order and they must begin with AARCH64_X0_REGNUM! */
131 "x0", "x1", "x2", "x3",
132 "x4", "x5", "x6", "x7",
133 "x8", "x9", "x10", "x11",
134 "x12", "x13", "x14", "x15",
135 "x16", "x17", "x18", "x19",
136 "x20", "x21", "x22", "x23",
137 "x24", "x25", "x26", "x27",
138 "x28", "x29", "x30", "sp",
142 /* The FP/SIMD 'V' registers. */
143 static const char *const aarch64_v_register_names
[] =
145 /* These registers must appear in consecutive RAW register number
146 order and they must begin with AARCH64_V0_REGNUM! */
147 "v0", "v1", "v2", "v3",
148 "v4", "v5", "v6", "v7",
149 "v8", "v9", "v10", "v11",
150 "v12", "v13", "v14", "v15",
151 "v16", "v17", "v18", "v19",
152 "v20", "v21", "v22", "v23",
153 "v24", "v25", "v26", "v27",
154 "v28", "v29", "v30", "v31",
159 /* The SVE 'Z' and 'P' registers. */
160 static const char *const aarch64_sve_register_names
[] =
162 /* These registers must appear in consecutive RAW register number
163 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
164 "z0", "z1", "z2", "z3",
165 "z4", "z5", "z6", "z7",
166 "z8", "z9", "z10", "z11",
167 "z12", "z13", "z14", "z15",
168 "z16", "z17", "z18", "z19",
169 "z20", "z21", "z22", "z23",
170 "z24", "z25", "z26", "z27",
171 "z28", "z29", "z30", "z31",
173 "p0", "p1", "p2", "p3",
174 "p4", "p5", "p6", "p7",
175 "p8", "p9", "p10", "p11",
176 "p12", "p13", "p14", "p15",
180 /* AArch64 prologue cache structure. */
181 struct aarch64_prologue_cache
183 /* The program counter at the start of the function. It is used to
184 identify this frame as a prologue frame. */
187 /* The program counter at the time this frame was created; i.e. where
188 this function was called from. It is used to identify this frame as a
192 /* The stack pointer at the time this frame was created; i.e. the
193 caller's stack pointer when this function was called. It is used
194 to identify this frame. */
197 /* Is the target available to read from? */
200 /* The frame base for this frame is just prev_sp - frame size.
201 FRAMESIZE is the distance from the frame pointer to the
202 initial stack pointer. */
205 /* The register used to hold the frame pointer for this frame. */
208 /* Saved register offsets. */
209 struct trad_frame_saved_reg
*saved_regs
;
213 show_aarch64_debug (struct ui_file
*file
, int from_tty
,
214 struct cmd_list_element
*c
, const char *value
)
216 fprintf_filtered (file
, _("AArch64 debugging is %s.\n"), value
);
221 /* Abstract instruction reader. */
223 class abstract_instruction_reader
226 /* Read in one instruction. */
227 virtual ULONGEST
read (CORE_ADDR memaddr
, int len
,
228 enum bfd_endian byte_order
) = 0;
231 /* Instruction reader from real target. */
233 class instruction_reader
: public abstract_instruction_reader
236 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
239 return read_code_unsigned_integer (memaddr
, len
, byte_order
);
245 /* Analyze a prologue, looking for a recognizable stack frame
246 and frame pointer. Scan until we encounter a store that could
247 clobber the stack frame unexpectedly, or an unknown instruction. */
250 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
251 CORE_ADDR start
, CORE_ADDR limit
,
252 struct aarch64_prologue_cache
*cache
,
253 abstract_instruction_reader
& reader
)
255 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
257 /* Track X registers and D registers in prologue. */
258 pv_t regs
[AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
];
260 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
; i
++)
261 regs
[i
] = pv_register (i
, 0);
262 pv_area
stack (AARCH64_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
264 for (; start
< limit
; start
+= 4)
269 insn
= reader
.read (start
, 4, byte_order_for_code
);
271 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
274 if (inst
.opcode
->iclass
== addsub_imm
275 && (inst
.opcode
->op
== OP_ADD
276 || strcmp ("sub", inst
.opcode
->name
) == 0))
278 unsigned rd
= inst
.operands
[0].reg
.regno
;
279 unsigned rn
= inst
.operands
[1].reg
.regno
;
281 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 3);
282 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd_SP
);
283 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn_SP
);
284 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_AIMM
);
286 if (inst
.opcode
->op
== OP_ADD
)
288 regs
[rd
] = pv_add_constant (regs
[rn
],
289 inst
.operands
[2].imm
.value
);
293 regs
[rd
] = pv_add_constant (regs
[rn
],
294 -inst
.operands
[2].imm
.value
);
297 else if (inst
.opcode
->iclass
== pcreladdr
298 && inst
.operands
[1].type
== AARCH64_OPND_ADDR_ADRP
)
300 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
301 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
303 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
305 else if (inst
.opcode
->iclass
== branch_imm
)
307 /* Stop analysis on branch. */
310 else if (inst
.opcode
->iclass
== condbranch
)
312 /* Stop analysis on branch. */
315 else if (inst
.opcode
->iclass
== branch_reg
)
317 /* Stop analysis on branch. */
320 else if (inst
.opcode
->iclass
== compbranch
)
322 /* Stop analysis on branch. */
325 else if (inst
.opcode
->op
== OP_MOVZ
)
327 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
328 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
330 else if (inst
.opcode
->iclass
== log_shift
331 && strcmp (inst
.opcode
->name
, "orr") == 0)
333 unsigned rd
= inst
.operands
[0].reg
.regno
;
334 unsigned rn
= inst
.operands
[1].reg
.regno
;
335 unsigned rm
= inst
.operands
[2].reg
.regno
;
337 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
338 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn
);
339 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_Rm_SFT
);
341 if (inst
.operands
[2].shifter
.amount
== 0
342 && rn
== AARCH64_SP_REGNUM
)
348 debug_printf ("aarch64: prologue analysis gave up "
349 "addr=%s opcode=0x%x (orr x register)\n",
350 core_addr_to_string_nz (start
), insn
);
355 else if (inst
.opcode
->op
== OP_STUR
)
357 unsigned rt
= inst
.operands
[0].reg
.regno
;
358 unsigned rn
= inst
.operands
[1].addr
.base_regno
;
360 = (aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
) == 8);
362 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
363 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
);
364 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_ADDR_SIMM9
);
365 gdb_assert (!inst
.operands
[1].addr
.offset
.is_reg
);
367 stack
.store (pv_add_constant (regs
[rn
],
368 inst
.operands
[1].addr
.offset
.imm
),
369 is64
? 8 : 4, regs
[rt
]);
371 else if ((inst
.opcode
->iclass
== ldstpair_off
372 || (inst
.opcode
->iclass
== ldstpair_indexed
373 && inst
.operands
[2].addr
.preind
))
374 && strcmp ("stp", inst
.opcode
->name
) == 0)
376 /* STP with addressing mode Pre-indexed and Base register. */
379 unsigned rn
= inst
.operands
[2].addr
.base_regno
;
380 int32_t imm
= inst
.operands
[2].addr
.offset
.imm
;
382 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
383 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
384 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rt2
385 || inst
.operands
[1].type
== AARCH64_OPND_Ft2
);
386 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_ADDR_SIMM7
);
387 gdb_assert (!inst
.operands
[2].addr
.offset
.is_reg
);
389 /* If recording this store would invalidate the store area
390 (perhaps because rn is not known) then we should abandon
391 further prologue analysis. */
392 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
)))
395 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
+ 8)))
398 rt1
= inst
.operands
[0].reg
.regno
;
399 rt2
= inst
.operands
[1].reg
.regno
;
400 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
402 /* Only bottom 64-bit of each V register (D register) need
404 gdb_assert (inst
.operands
[0].qualifier
== AARCH64_OPND_QLF_S_D
);
405 rt1
+= AARCH64_X_REGISTER_COUNT
;
406 rt2
+= AARCH64_X_REGISTER_COUNT
;
409 stack
.store (pv_add_constant (regs
[rn
], imm
), 8,
411 stack
.store (pv_add_constant (regs
[rn
], imm
+ 8), 8,
414 if (inst
.operands
[2].addr
.writeback
)
415 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
418 else if ((inst
.opcode
->iclass
== ldst_imm9
/* Signed immediate. */
419 || (inst
.opcode
->iclass
== ldst_pos
/* Unsigned immediate. */
420 && (inst
.opcode
->op
== OP_STR_POS
421 || inst
.opcode
->op
== OP_STRF_POS
)))
422 && inst
.operands
[1].addr
.base_regno
== AARCH64_SP_REGNUM
423 && strcmp ("str", inst
.opcode
->name
) == 0)
425 /* STR (immediate) */
426 unsigned int rt
= inst
.operands
[0].reg
.regno
;
427 int32_t imm
= inst
.operands
[1].addr
.offset
.imm
;
428 unsigned int rn
= inst
.operands
[1].addr
.base_regno
;
430 = (aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
) == 8);
431 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
432 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
434 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
436 /* Only bottom 64-bit of each V register (D register) need
438 gdb_assert (inst
.operands
[0].qualifier
== AARCH64_OPND_QLF_S_D
);
439 rt
+= AARCH64_X_REGISTER_COUNT
;
442 stack
.store (pv_add_constant (regs
[rn
], imm
),
443 is64
? 8 : 4, regs
[rt
]);
444 if (inst
.operands
[1].addr
.writeback
)
445 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
447 else if (inst
.opcode
->iclass
== testbranch
)
449 /* Stop analysis on branch. */
456 debug_printf ("aarch64: prologue analysis gave up addr=%s"
458 core_addr_to_string_nz (start
), insn
);
467 if (pv_is_register (regs
[AARCH64_FP_REGNUM
], AARCH64_SP_REGNUM
))
469 /* Frame pointer is fp. Frame size is constant. */
470 cache
->framereg
= AARCH64_FP_REGNUM
;
471 cache
->framesize
= -regs
[AARCH64_FP_REGNUM
].k
;
473 else if (pv_is_register (regs
[AARCH64_SP_REGNUM
], AARCH64_SP_REGNUM
))
475 /* Try the stack pointer. */
476 cache
->framesize
= -regs
[AARCH64_SP_REGNUM
].k
;
477 cache
->framereg
= AARCH64_SP_REGNUM
;
481 /* We're just out of luck. We don't know where the frame is. */
482 cache
->framereg
= -1;
483 cache
->framesize
= 0;
486 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
490 if (stack
.find_reg (gdbarch
, i
, &offset
))
491 cache
->saved_regs
[i
].addr
= offset
;
494 for (i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
496 int regnum
= gdbarch_num_regs (gdbarch
);
499 if (stack
.find_reg (gdbarch
, i
+ AARCH64_X_REGISTER_COUNT
,
501 cache
->saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
= offset
;
508 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
509 CORE_ADDR start
, CORE_ADDR limit
,
510 struct aarch64_prologue_cache
*cache
)
512 instruction_reader reader
;
514 return aarch64_analyze_prologue (gdbarch
, start
, limit
, cache
,
520 namespace selftests
{
522 /* Instruction reader from manually cooked instruction sequences. */
524 class instruction_reader_test
: public abstract_instruction_reader
527 template<size_t SIZE
>
528 explicit instruction_reader_test (const uint32_t (&insns
)[SIZE
])
529 : m_insns (insns
), m_insns_size (SIZE
)
532 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
535 SELF_CHECK (len
== 4);
536 SELF_CHECK (memaddr
% 4 == 0);
537 SELF_CHECK (memaddr
/ 4 < m_insns_size
);
539 return m_insns
[memaddr
/ 4];
543 const uint32_t *m_insns
;
548 aarch64_analyze_prologue_test (void)
550 struct gdbarch_info info
;
552 gdbarch_info_init (&info
);
553 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
555 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
556 SELF_CHECK (gdbarch
!= NULL
);
558 /* Test the simple prologue in which frame pointer is used. */
560 struct aarch64_prologue_cache cache
;
561 cache
.saved_regs
= trad_frame_alloc_saved_regs (gdbarch
);
563 static const uint32_t insns
[] = {
564 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
565 0x910003fd, /* mov x29, sp */
566 0x97ffffe6, /* bl 0x400580 */
568 instruction_reader_test
reader (insns
);
570 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
571 SELF_CHECK (end
== 4 * 2);
573 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
574 SELF_CHECK (cache
.framesize
== 272);
576 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
578 if (i
== AARCH64_FP_REGNUM
)
579 SELF_CHECK (cache
.saved_regs
[i
].addr
== -272);
580 else if (i
== AARCH64_LR_REGNUM
)
581 SELF_CHECK (cache
.saved_regs
[i
].addr
== -264);
583 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
586 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
588 int regnum
= gdbarch_num_regs (gdbarch
);
590 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
595 /* Test a prologue in which STR is used and frame pointer is not
598 struct aarch64_prologue_cache cache
;
599 cache
.saved_regs
= trad_frame_alloc_saved_regs (gdbarch
);
601 static const uint32_t insns
[] = {
602 0xf81d0ff3, /* str x19, [sp, #-48]! */
603 0xb9002fe0, /* str w0, [sp, #44] */
604 0xf90013e1, /* str x1, [sp, #32]*/
605 0xfd000fe0, /* str d0, [sp, #24] */
606 0xaa0203f3, /* mov x19, x2 */
607 0xf94013e0, /* ldr x0, [sp, #32] */
609 instruction_reader_test
reader (insns
);
611 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
613 SELF_CHECK (end
== 4 * 5);
615 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
616 SELF_CHECK (cache
.framesize
== 48);
618 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
621 SELF_CHECK (cache
.saved_regs
[i
].addr
== -16);
623 SELF_CHECK (cache
.saved_regs
[i
].addr
== -48);
625 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
628 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
630 int regnum
= gdbarch_num_regs (gdbarch
);
633 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
636 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
641 } // namespace selftests
642 #endif /* GDB_SELF_TEST */
644 /* Implement the "skip_prologue" gdbarch method. */
647 aarch64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
649 CORE_ADDR func_addr
, limit_pc
;
651 /* See if we can determine the end of the prologue via the symbol
652 table. If so, then return either PC, or the PC after the
653 prologue, whichever is greater. */
654 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
656 CORE_ADDR post_prologue_pc
657 = skip_prologue_using_sal (gdbarch
, func_addr
);
659 if (post_prologue_pc
!= 0)
660 return std::max (pc
, post_prologue_pc
);
663 /* Can't determine prologue from the symbol table, need to examine
666 /* Find an upper limit on the function prologue using the debug
667 information. If the debug information could not be used to
668 provide that bound, then use an arbitrary large number as the
670 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
672 limit_pc
= pc
+ 128; /* Magic. */
674 /* Try disassembling prologue. */
675 return aarch64_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
678 /* Scan the function prologue for THIS_FRAME and populate the prologue
682 aarch64_scan_prologue (struct frame_info
*this_frame
,
683 struct aarch64_prologue_cache
*cache
)
685 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
686 CORE_ADDR prologue_start
;
687 CORE_ADDR prologue_end
;
688 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
689 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
691 cache
->prev_pc
= prev_pc
;
693 /* Assume we do not find a frame. */
694 cache
->framereg
= -1;
695 cache
->framesize
= 0;
697 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
700 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
704 /* No line info so use the current PC. */
705 prologue_end
= prev_pc
;
707 else if (sal
.end
< prologue_end
)
709 /* The next line begins after the function end. */
710 prologue_end
= sal
.end
;
713 prologue_end
= std::min (prologue_end
, prev_pc
);
714 aarch64_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
720 frame_loc
= get_frame_register_unsigned (this_frame
, AARCH64_FP_REGNUM
);
724 cache
->framereg
= AARCH64_FP_REGNUM
;
725 cache
->framesize
= 16;
726 cache
->saved_regs
[29].addr
= 0;
727 cache
->saved_regs
[30].addr
= 8;
731 /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
732 function may throw an exception if the inferior's registers or memory is
736 aarch64_make_prologue_cache_1 (struct frame_info
*this_frame
,
737 struct aarch64_prologue_cache
*cache
)
739 CORE_ADDR unwound_fp
;
742 aarch64_scan_prologue (this_frame
, cache
);
744 if (cache
->framereg
== -1)
747 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
751 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
753 /* Calculate actual addresses of saved registers using offsets
754 determined by aarch64_analyze_prologue. */
755 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
756 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
757 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
759 cache
->func
= get_frame_func (this_frame
);
761 cache
->available_p
= 1;
764 /* Allocate and fill in *THIS_CACHE with information about the prologue of
765 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
766 Return a pointer to the current aarch64_prologue_cache in
769 static struct aarch64_prologue_cache
*
770 aarch64_make_prologue_cache (struct frame_info
*this_frame
, void **this_cache
)
772 struct aarch64_prologue_cache
*cache
;
774 if (*this_cache
!= NULL
)
775 return (struct aarch64_prologue_cache
*) *this_cache
;
777 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
778 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
783 aarch64_make_prologue_cache_1 (this_frame
, cache
);
785 CATCH (ex
, RETURN_MASK_ERROR
)
787 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
788 throw_exception (ex
);
795 /* Implement the "stop_reason" frame_unwind method. */
797 static enum unwind_stop_reason
798 aarch64_prologue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
801 struct aarch64_prologue_cache
*cache
802 = aarch64_make_prologue_cache (this_frame
, this_cache
);
804 if (!cache
->available_p
)
805 return UNWIND_UNAVAILABLE
;
807 /* Halt the backtrace at "_start". */
808 if (cache
->prev_pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
809 return UNWIND_OUTERMOST
;
811 /* We've hit a wall, stop. */
812 if (cache
->prev_sp
== 0)
813 return UNWIND_OUTERMOST
;
815 return UNWIND_NO_REASON
;
818 /* Our frame ID for a normal frame is the current function's starting
819 PC and the caller's SP when we were called. */
822 aarch64_prologue_this_id (struct frame_info
*this_frame
,
823 void **this_cache
, struct frame_id
*this_id
)
825 struct aarch64_prologue_cache
*cache
826 = aarch64_make_prologue_cache (this_frame
, this_cache
);
828 if (!cache
->available_p
)
829 *this_id
= frame_id_build_unavailable_stack (cache
->func
);
831 *this_id
= frame_id_build (cache
->prev_sp
, cache
->func
);
834 /* Implement the "prev_register" frame_unwind method. */
836 static struct value
*
837 aarch64_prologue_prev_register (struct frame_info
*this_frame
,
838 void **this_cache
, int prev_regnum
)
840 struct aarch64_prologue_cache
*cache
841 = aarch64_make_prologue_cache (this_frame
, this_cache
);
843 /* If we are asked to unwind the PC, then we need to return the LR
844 instead. The prologue may save PC, but it will point into this
845 frame's prologue, not the next frame's resume location. */
846 if (prev_regnum
== AARCH64_PC_REGNUM
)
850 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
851 return frame_unwind_got_constant (this_frame
, prev_regnum
, lr
);
854 /* SP is generally not saved to the stack, but this frame is
855 identified by the next frame's stack pointer at the time of the
856 call. The value was already reconstructed into PREV_SP. */
869 if (prev_regnum
== AARCH64_SP_REGNUM
)
870 return frame_unwind_got_constant (this_frame
, prev_regnum
,
873 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
877 /* AArch64 prologue unwinder. */
878 struct frame_unwind aarch64_prologue_unwind
=
881 aarch64_prologue_frame_unwind_stop_reason
,
882 aarch64_prologue_this_id
,
883 aarch64_prologue_prev_register
,
885 default_frame_sniffer
888 /* Allocate and fill in *THIS_CACHE with information about the prologue of
889 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
890 Return a pointer to the current aarch64_prologue_cache in
893 static struct aarch64_prologue_cache
*
894 aarch64_make_stub_cache (struct frame_info
*this_frame
, void **this_cache
)
896 struct aarch64_prologue_cache
*cache
;
898 if (*this_cache
!= NULL
)
899 return (struct aarch64_prologue_cache
*) *this_cache
;
901 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
902 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
907 cache
->prev_sp
= get_frame_register_unsigned (this_frame
,
909 cache
->prev_pc
= get_frame_pc (this_frame
);
910 cache
->available_p
= 1;
912 CATCH (ex
, RETURN_MASK_ERROR
)
914 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
915 throw_exception (ex
);
922 /* Implement the "stop_reason" frame_unwind method. */
924 static enum unwind_stop_reason
925 aarch64_stub_frame_unwind_stop_reason (struct frame_info
*this_frame
,
928 struct aarch64_prologue_cache
*cache
929 = aarch64_make_stub_cache (this_frame
, this_cache
);
931 if (!cache
->available_p
)
932 return UNWIND_UNAVAILABLE
;
934 return UNWIND_NO_REASON
;
937 /* Our frame ID for a stub frame is the current SP and LR. */
940 aarch64_stub_this_id (struct frame_info
*this_frame
,
941 void **this_cache
, struct frame_id
*this_id
)
943 struct aarch64_prologue_cache
*cache
944 = aarch64_make_stub_cache (this_frame
, this_cache
);
946 if (cache
->available_p
)
947 *this_id
= frame_id_build (cache
->prev_sp
, cache
->prev_pc
);
949 *this_id
= frame_id_build_unavailable_stack (cache
->prev_pc
);
952 /* Implement the "sniffer" frame_unwind method. */
955 aarch64_stub_unwind_sniffer (const struct frame_unwind
*self
,
956 struct frame_info
*this_frame
,
957 void **this_prologue_cache
)
959 CORE_ADDR addr_in_block
;
962 addr_in_block
= get_frame_address_in_block (this_frame
);
963 if (in_plt_section (addr_in_block
)
964 /* We also use the stub winder if the target memory is unreadable
965 to avoid having the prologue unwinder trying to read it. */
966 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
972 /* AArch64 stub unwinder. */
973 struct frame_unwind aarch64_stub_unwind
=
976 aarch64_stub_frame_unwind_stop_reason
,
977 aarch64_stub_this_id
,
978 aarch64_prologue_prev_register
,
980 aarch64_stub_unwind_sniffer
983 /* Return the frame base address of *THIS_FRAME. */
986 aarch64_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
988 struct aarch64_prologue_cache
*cache
989 = aarch64_make_prologue_cache (this_frame
, this_cache
);
991 return cache
->prev_sp
- cache
->framesize
;
994 /* AArch64 default frame base information. */
995 struct frame_base aarch64_normal_base
=
997 &aarch64_prologue_unwind
,
998 aarch64_normal_frame_base
,
999 aarch64_normal_frame_base
,
1000 aarch64_normal_frame_base
1003 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1004 dummy frame. The frame ID's base needs to match the TOS value
1005 saved by save_dummy_frame_tos () and returned from
1006 aarch64_push_dummy_call, and the PC needs to match the dummy
1007 frame's breakpoint. */
1009 static struct frame_id
1010 aarch64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1012 return frame_id_build (get_frame_register_unsigned (this_frame
,
1014 get_frame_pc (this_frame
));
1017 /* Implement the "unwind_pc" gdbarch method. */
1020 aarch64_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1023 = frame_unwind_register_unsigned (this_frame
, AARCH64_PC_REGNUM
);
1028 /* Implement the "unwind_sp" gdbarch method. */
1031 aarch64_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1033 return frame_unwind_register_unsigned (this_frame
, AARCH64_SP_REGNUM
);
1036 /* Return the value of the REGNUM register in the previous frame of
1039 static struct value
*
1040 aarch64_dwarf2_prev_register (struct frame_info
*this_frame
,
1041 void **this_cache
, int regnum
)
1047 case AARCH64_PC_REGNUM
:
1048 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
1049 return frame_unwind_got_constant (this_frame
, regnum
, lr
);
1052 internal_error (__FILE__
, __LINE__
,
1053 _("Unexpected register %d"), regnum
);
1057 /* Implement the "init_reg" dwarf2_frame_ops method. */
1060 aarch64_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1061 struct dwarf2_frame_state_reg
*reg
,
1062 struct frame_info
*this_frame
)
1066 case AARCH64_PC_REGNUM
:
1067 reg
->how
= DWARF2_FRAME_REG_FN
;
1068 reg
->loc
.fn
= aarch64_dwarf2_prev_register
;
1070 case AARCH64_SP_REGNUM
:
1071 reg
->how
= DWARF2_FRAME_REG_CFA
;
1076 /* When arguments must be pushed onto the stack, they go on in reverse
1077 order. The code below implements a FILO (stack) to do this. */
1081 /* Value to pass on stack. It can be NULL if this item is for stack
1083 const gdb_byte
*data
;
1085 /* Size in bytes of value to pass on stack. */
1089 DEF_VEC_O (stack_item_t
);
1091 /* Return the alignment (in bytes) of the given type. */
1094 aarch64_type_align (struct type
*t
)
1100 t
= check_typedef (t
);
1101 switch (TYPE_CODE (t
))
1104 /* Should never happen. */
1105 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1109 case TYPE_CODE_ENUM
:
1113 case TYPE_CODE_RANGE
:
1114 case TYPE_CODE_BITSTRING
:
1116 case TYPE_CODE_RVALUE_REF
:
1117 case TYPE_CODE_CHAR
:
1118 case TYPE_CODE_BOOL
:
1119 return TYPE_LENGTH (t
);
1121 case TYPE_CODE_ARRAY
:
1122 if (TYPE_VECTOR (t
))
1124 /* Use the natural alignment for vector types (the same for
1125 scalar type), but the maximum alignment is 128-bit. */
1126 if (TYPE_LENGTH (t
) > 16)
1129 return TYPE_LENGTH (t
);
1132 return aarch64_type_align (TYPE_TARGET_TYPE (t
));
1133 case TYPE_CODE_COMPLEX
:
1134 return aarch64_type_align (TYPE_TARGET_TYPE (t
));
1136 case TYPE_CODE_STRUCT
:
1137 case TYPE_CODE_UNION
:
1139 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1141 falign
= aarch64_type_align (TYPE_FIELD_TYPE (t
, n
));
1149 /* Return 1 if *TY is a homogeneous floating-point aggregate or
1150 homogeneous short-vector aggregate as defined in the AAPCS64 ABI
1151 document; otherwise return 0. */
1154 is_hfa_or_hva (struct type
*ty
)
1156 switch (TYPE_CODE (ty
))
1158 case TYPE_CODE_ARRAY
:
1160 struct type
*target_ty
= TYPE_TARGET_TYPE (ty
);
1162 if (TYPE_VECTOR (ty
))
1165 if (TYPE_LENGTH (ty
) <= 4 /* HFA or HVA has at most 4 members. */
1166 && (TYPE_CODE (target_ty
) == TYPE_CODE_FLT
/* HFA */
1167 || (TYPE_CODE (target_ty
) == TYPE_CODE_ARRAY
/* HVA */
1168 && TYPE_VECTOR (target_ty
))))
1173 case TYPE_CODE_UNION
:
1174 case TYPE_CODE_STRUCT
:
1176 /* HFA or HVA has at most four members. */
1177 if (TYPE_NFIELDS (ty
) > 0 && TYPE_NFIELDS (ty
) <= 4)
1179 struct type
*member0_type
;
1181 member0_type
= check_typedef (TYPE_FIELD_TYPE (ty
, 0));
1182 if (TYPE_CODE (member0_type
) == TYPE_CODE_FLT
1183 || (TYPE_CODE (member0_type
) == TYPE_CODE_ARRAY
1184 && TYPE_VECTOR (member0_type
)))
1188 for (i
= 0; i
< TYPE_NFIELDS (ty
); i
++)
1190 struct type
*member1_type
;
1192 member1_type
= check_typedef (TYPE_FIELD_TYPE (ty
, i
));
1193 if (TYPE_CODE (member0_type
) != TYPE_CODE (member1_type
)
1194 || (TYPE_LENGTH (member0_type
)
1195 != TYPE_LENGTH (member1_type
)))
1211 /* AArch64 function call information structure. */
1212 struct aarch64_call_info
1214 /* the current argument number. */
1217 /* The next general purpose register number, equivalent to NGRN as
1218 described in the AArch64 Procedure Call Standard. */
1221 /* The next SIMD and floating point register number, equivalent to
1222 NSRN as described in the AArch64 Procedure Call Standard. */
1225 /* The next stacked argument address, equivalent to NSAA as
1226 described in the AArch64 Procedure Call Standard. */
1229 /* Stack item vector. */
1230 VEC(stack_item_t
) *si
;
1233 /* Pass a value in a sequence of consecutive X registers. The caller
1234 is responsbile for ensuring sufficient registers are available. */
1237 pass_in_x (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1238 struct aarch64_call_info
*info
, struct type
*type
,
1241 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1242 int len
= TYPE_LENGTH (type
);
1243 enum type_code typecode
= TYPE_CODE (type
);
1244 int regnum
= AARCH64_X0_REGNUM
+ info
->ngrn
;
1245 const bfd_byte
*buf
= value_contents (arg
);
1251 int partial_len
= len
< X_REGISTER_SIZE
? len
: X_REGISTER_SIZE
;
1252 CORE_ADDR regval
= extract_unsigned_integer (buf
, partial_len
,
1256 /* Adjust sub-word struct/union args when big-endian. */
1257 if (byte_order
== BFD_ENDIAN_BIG
1258 && partial_len
< X_REGISTER_SIZE
1259 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1260 regval
<<= ((X_REGISTER_SIZE
- partial_len
) * TARGET_CHAR_BIT
);
1264 debug_printf ("arg %d in %s = 0x%s\n", info
->argnum
,
1265 gdbarch_register_name (gdbarch
, regnum
),
1266 phex (regval
, X_REGISTER_SIZE
));
1268 regcache_cooked_write_unsigned (regcache
, regnum
, regval
);
1275 /* Attempt to marshall a value in a V register. Return 1 if
1276 successful, or 0 if insufficient registers are available. This
1277 function, unlike the equivalent pass_in_x() function does not
1278 handle arguments spread across multiple registers. */
1281 pass_in_v (struct gdbarch
*gdbarch
,
1282 struct regcache
*regcache
,
1283 struct aarch64_call_info
*info
,
1284 int len
, const bfd_byte
*buf
)
1288 int regnum
= AARCH64_V0_REGNUM
+ info
->nsrn
;
1289 gdb_byte reg
[V_REGISTER_SIZE
];
1294 memset (reg
, 0, sizeof (reg
));
1295 /* PCS C.1, the argument is allocated to the least significant
1296 bits of V register. */
1297 memcpy (reg
, buf
, len
);
1298 regcache
->cooked_write (regnum
, reg
);
1302 debug_printf ("arg %d in %s\n", info
->argnum
,
1303 gdbarch_register_name (gdbarch
, regnum
));
1311 /* Marshall an argument onto the stack. */
1314 pass_on_stack (struct aarch64_call_info
*info
, struct type
*type
,
1317 const bfd_byte
*buf
= value_contents (arg
);
1318 int len
= TYPE_LENGTH (type
);
1324 align
= aarch64_type_align (type
);
1326 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1327 Natural alignment of the argument's type. */
1328 align
= align_up (align
, 8);
1330 /* The AArch64 PCS requires at most doubleword alignment. */
1336 debug_printf ("arg %d len=%d @ sp + %d\n", info
->argnum
, len
,
1342 VEC_safe_push (stack_item_t
, info
->si
, &item
);
1345 if (info
->nsaa
& (align
- 1))
1347 /* Push stack alignment padding. */
1348 int pad
= align
- (info
->nsaa
& (align
- 1));
1353 VEC_safe_push (stack_item_t
, info
->si
, &item
);
1358 /* Marshall an argument into a sequence of one or more consecutive X
1359 registers or, if insufficient X registers are available then onto
1363 pass_in_x_or_stack (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1364 struct aarch64_call_info
*info
, struct type
*type
,
1367 int len
= TYPE_LENGTH (type
);
1368 int nregs
= (len
+ X_REGISTER_SIZE
- 1) / X_REGISTER_SIZE
;
1370 /* PCS C.13 - Pass in registers if we have enough spare */
1371 if (info
->ngrn
+ nregs
<= 8)
1373 pass_in_x (gdbarch
, regcache
, info
, type
, arg
);
1374 info
->ngrn
+= nregs
;
1379 pass_on_stack (info
, type
, arg
);
1383 /* Pass a value in a V register, or on the stack if insufficient are
1387 pass_in_v_or_stack (struct gdbarch
*gdbarch
,
1388 struct regcache
*regcache
,
1389 struct aarch64_call_info
*info
,
1393 if (!pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (type
),
1394 value_contents (arg
)))
1395 pass_on_stack (info
, type
, arg
);
1398 /* Implement the "push_dummy_call" gdbarch method. */
1401 aarch64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1402 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1404 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1405 CORE_ADDR struct_addr
)
1408 struct aarch64_call_info info
;
1409 struct type
*func_type
;
1410 struct type
*return_type
;
1411 int lang_struct_return
;
1413 memset (&info
, 0, sizeof (info
));
1415 /* We need to know what the type of the called function is in order
1416 to determine the number of named/anonymous arguments for the
1417 actual argument placement, and the return type in order to handle
1418 return value correctly.
1420 The generic code above us views the decision of return in memory
1421 or return in registers as a two stage processes. The language
1422 handler is consulted first and may decide to return in memory (eg
1423 class with copy constructor returned by value), this will cause
1424 the generic code to allocate space AND insert an initial leading
1427 If the language code does not decide to pass in memory then the
1428 target code is consulted.
1430 If the language code decides to pass in memory we want to move
1431 the pointer inserted as the initial argument from the argument
1432 list and into X8, the conventional AArch64 struct return pointer
1435 This is slightly awkward, ideally the flag "lang_struct_return"
1436 would be passed to the targets implementation of push_dummy_call.
1437 Rather that change the target interface we call the language code
1438 directly ourselves. */
1440 func_type
= check_typedef (value_type (function
));
1442 /* Dereference function pointer types. */
1443 if (TYPE_CODE (func_type
) == TYPE_CODE_PTR
)
1444 func_type
= TYPE_TARGET_TYPE (func_type
);
1446 gdb_assert (TYPE_CODE (func_type
) == TYPE_CODE_FUNC
1447 || TYPE_CODE (func_type
) == TYPE_CODE_METHOD
);
1449 /* If language_pass_by_reference () returned true we will have been
1450 given an additional initial argument, a hidden pointer to the
1451 return slot in memory. */
1452 return_type
= TYPE_TARGET_TYPE (func_type
);
1453 lang_struct_return
= language_pass_by_reference (return_type
);
1455 /* Set the return address. For the AArch64, the return breakpoint
1456 is always at BP_ADDR. */
1457 regcache_cooked_write_unsigned (regcache
, AARCH64_LR_REGNUM
, bp_addr
);
1459 /* If we were given an initial argument for the return slot because
1460 lang_struct_return was true, lose it. */
1461 if (lang_struct_return
)
1467 /* The struct_return pointer occupies X8. */
1468 if (struct_return
|| lang_struct_return
)
1472 debug_printf ("struct return in %s = 0x%s\n",
1473 gdbarch_register_name (gdbarch
,
1474 AARCH64_STRUCT_RETURN_REGNUM
),
1475 paddress (gdbarch
, struct_addr
));
1477 regcache_cooked_write_unsigned (regcache
, AARCH64_STRUCT_RETURN_REGNUM
,
1481 for (argnum
= 0; argnum
< nargs
; argnum
++)
1483 struct value
*arg
= args
[argnum
];
1484 struct type
*arg_type
;
1487 arg_type
= check_typedef (value_type (arg
));
1488 len
= TYPE_LENGTH (arg_type
);
1490 switch (TYPE_CODE (arg_type
))
1493 case TYPE_CODE_BOOL
:
1494 case TYPE_CODE_CHAR
:
1495 case TYPE_CODE_RANGE
:
1496 case TYPE_CODE_ENUM
:
1499 /* Promote to 32 bit integer. */
1500 if (TYPE_UNSIGNED (arg_type
))
1501 arg_type
= builtin_type (gdbarch
)->builtin_uint32
;
1503 arg_type
= builtin_type (gdbarch
)->builtin_int32
;
1504 arg
= value_cast (arg_type
, arg
);
1506 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1509 case TYPE_CODE_COMPLEX
:
1512 const bfd_byte
*buf
= value_contents (arg
);
1513 struct type
*target_type
=
1514 check_typedef (TYPE_TARGET_TYPE (arg_type
));
1516 pass_in_v (gdbarch
, regcache
, &info
,
1517 TYPE_LENGTH (target_type
), buf
);
1518 pass_in_v (gdbarch
, regcache
, &info
,
1519 TYPE_LENGTH (target_type
),
1520 buf
+ TYPE_LENGTH (target_type
));
1525 pass_on_stack (&info
, arg_type
, arg
);
1529 pass_in_v_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1532 case TYPE_CODE_STRUCT
:
1533 case TYPE_CODE_ARRAY
:
1534 case TYPE_CODE_UNION
:
1535 if (is_hfa_or_hva (arg_type
))
1537 int elements
= TYPE_NFIELDS (arg_type
);
1539 /* Homogeneous Aggregates */
1540 if (info
.nsrn
+ elements
< 8)
1544 for (i
= 0; i
< elements
; i
++)
1546 /* We know that we have sufficient registers
1547 available therefore this will never fallback
1549 struct value
*field
=
1550 value_primitive_field (arg
, 0, i
, arg_type
);
1551 struct type
*field_type
=
1552 check_typedef (value_type (field
));
1554 pass_in_v_or_stack (gdbarch
, regcache
, &info
,
1561 pass_on_stack (&info
, arg_type
, arg
);
1564 else if (TYPE_CODE (arg_type
) == TYPE_CODE_ARRAY
1565 && TYPE_VECTOR (arg_type
) && (len
== 16 || len
== 8))
1567 /* Short vector types are passed in V registers. */
1568 pass_in_v_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1572 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1573 invisible reference. */
1575 /* Allocate aligned storage. */
1576 sp
= align_down (sp
- len
, 16);
1578 /* Write the real data into the stack. */
1579 write_memory (sp
, value_contents (arg
), len
);
1581 /* Construct the indirection. */
1582 arg_type
= lookup_pointer_type (arg_type
);
1583 arg
= value_from_pointer (arg_type
, sp
);
1584 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1587 /* PCS C.15 / C.18 multiple values pass. */
1588 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1592 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1597 /* Make sure stack retains 16 byte alignment. */
1599 sp
-= 16 - (info
.nsaa
& 15);
1601 while (!VEC_empty (stack_item_t
, info
.si
))
1603 stack_item_t
*si
= VEC_last (stack_item_t
, info
.si
);
1606 if (si
->data
!= NULL
)
1607 write_memory (sp
, si
->data
, si
->len
);
1608 VEC_pop (stack_item_t
, info
.si
);
1611 VEC_free (stack_item_t
, info
.si
);
1613 /* Finally, update the SP register. */
1614 regcache_cooked_write_unsigned (regcache
, AARCH64_SP_REGNUM
, sp
);
1619 /* Implement the "frame_align" gdbarch method. */
1622 aarch64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1624 /* Align the stack to sixteen bytes. */
1625 return sp
& ~(CORE_ADDR
) 15;
1628 /* Return the type for an AdvSISD Q register. */
1630 static struct type
*
1631 aarch64_vnq_type (struct gdbarch
*gdbarch
)
1633 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1635 if (tdep
->vnq_type
== NULL
)
1640 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
1643 elem
= builtin_type (gdbarch
)->builtin_uint128
;
1644 append_composite_type_field (t
, "u", elem
);
1646 elem
= builtin_type (gdbarch
)->builtin_int128
;
1647 append_composite_type_field (t
, "s", elem
);
1652 return tdep
->vnq_type
;
1655 /* Return the type for an AdvSISD D register. */
1657 static struct type
*
1658 aarch64_vnd_type (struct gdbarch
*gdbarch
)
1660 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1662 if (tdep
->vnd_type
== NULL
)
1667 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
1670 elem
= builtin_type (gdbarch
)->builtin_double
;
1671 append_composite_type_field (t
, "f", elem
);
1673 elem
= builtin_type (gdbarch
)->builtin_uint64
;
1674 append_composite_type_field (t
, "u", elem
);
1676 elem
= builtin_type (gdbarch
)->builtin_int64
;
1677 append_composite_type_field (t
, "s", elem
);
1682 return tdep
->vnd_type
;
1685 /* Return the type for an AdvSISD S register. */
1687 static struct type
*
1688 aarch64_vns_type (struct gdbarch
*gdbarch
)
1690 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1692 if (tdep
->vns_type
== NULL
)
1697 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
1700 elem
= builtin_type (gdbarch
)->builtin_float
;
1701 append_composite_type_field (t
, "f", elem
);
1703 elem
= builtin_type (gdbarch
)->builtin_uint32
;
1704 append_composite_type_field (t
, "u", elem
);
1706 elem
= builtin_type (gdbarch
)->builtin_int32
;
1707 append_composite_type_field (t
, "s", elem
);
1712 return tdep
->vns_type
;
1715 /* Return the type for an AdvSISD H register. */
1717 static struct type
*
1718 aarch64_vnh_type (struct gdbarch
*gdbarch
)
1720 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1722 if (tdep
->vnh_type
== NULL
)
1727 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
1730 elem
= builtin_type (gdbarch
)->builtin_uint16
;
1731 append_composite_type_field (t
, "u", elem
);
1733 elem
= builtin_type (gdbarch
)->builtin_int16
;
1734 append_composite_type_field (t
, "s", elem
);
1739 return tdep
->vnh_type
;
1742 /* Return the type for an AdvSISD B register. */
1744 static struct type
*
1745 aarch64_vnb_type (struct gdbarch
*gdbarch
)
1747 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1749 if (tdep
->vnb_type
== NULL
)
1754 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
1757 elem
= builtin_type (gdbarch
)->builtin_uint8
;
1758 append_composite_type_field (t
, "u", elem
);
1760 elem
= builtin_type (gdbarch
)->builtin_int8
;
1761 append_composite_type_field (t
, "s", elem
);
1766 return tdep
->vnb_type
;
1769 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
1772 aarch64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
1774 if (reg
>= AARCH64_DWARF_X0
&& reg
<= AARCH64_DWARF_X0
+ 30)
1775 return AARCH64_X0_REGNUM
+ reg
- AARCH64_DWARF_X0
;
1777 if (reg
== AARCH64_DWARF_SP
)
1778 return AARCH64_SP_REGNUM
;
1780 if (reg
>= AARCH64_DWARF_V0
&& reg
<= AARCH64_DWARF_V0
+ 31)
1781 return AARCH64_V0_REGNUM
+ reg
- AARCH64_DWARF_V0
;
1787 /* Implement the "print_insn" gdbarch method. */
1790 aarch64_gdb_print_insn (bfd_vma memaddr
, disassemble_info
*info
)
1792 info
->symbols
= NULL
;
1793 return default_print_insn (memaddr
, info
);
1796 /* AArch64 BRK software debug mode instruction.
1797 Note that AArch64 code is always little-endian.
1798 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
1799 constexpr gdb_byte aarch64_default_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
1801 typedef BP_MANIPULATION (aarch64_default_breakpoint
) aarch64_breakpoint
;
1803 /* Extract from an array REGS containing the (raw) register state a
1804 function return value of type TYPE, and copy that, in virtual
1805 format, into VALBUF. */
1808 aarch64_extract_return_value (struct type
*type
, struct regcache
*regs
,
1811 struct gdbarch
*gdbarch
= regs
->arch ();
1812 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1814 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1816 bfd_byte buf
[V_REGISTER_SIZE
];
1817 int len
= TYPE_LENGTH (type
);
1819 regs
->cooked_read (AARCH64_V0_REGNUM
, buf
);
1820 memcpy (valbuf
, buf
, len
);
1822 else if (TYPE_CODE (type
) == TYPE_CODE_INT
1823 || TYPE_CODE (type
) == TYPE_CODE_CHAR
1824 || TYPE_CODE (type
) == TYPE_CODE_BOOL
1825 || TYPE_CODE (type
) == TYPE_CODE_PTR
1826 || TYPE_IS_REFERENCE (type
)
1827 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
1829 /* If the the type is a plain integer, then the access is
1830 straight-forward. Otherwise we have to play around a bit
1832 int len
= TYPE_LENGTH (type
);
1833 int regno
= AARCH64_X0_REGNUM
;
1838 /* By using store_unsigned_integer we avoid having to do
1839 anything special for small big-endian values. */
1840 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
1841 store_unsigned_integer (valbuf
,
1842 (len
> X_REGISTER_SIZE
1843 ? X_REGISTER_SIZE
: len
), byte_order
, tmp
);
1844 len
-= X_REGISTER_SIZE
;
1845 valbuf
+= X_REGISTER_SIZE
;
1848 else if (TYPE_CODE (type
) == TYPE_CODE_COMPLEX
)
1850 int regno
= AARCH64_V0_REGNUM
;
1851 bfd_byte buf
[V_REGISTER_SIZE
];
1852 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (type
));
1853 int len
= TYPE_LENGTH (target_type
);
1855 regs
->cooked_read (regno
, buf
);
1856 memcpy (valbuf
, buf
, len
);
1858 regs
->cooked_read (regno
+ 1, buf
);
1859 memcpy (valbuf
, buf
, len
);
1862 else if (is_hfa_or_hva (type
))
1864 int elements
= TYPE_NFIELDS (type
);
1865 struct type
*member_type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
1866 int len
= TYPE_LENGTH (member_type
);
1869 for (i
= 0; i
< elements
; i
++)
1871 int regno
= AARCH64_V0_REGNUM
+ i
;
1872 bfd_byte buf
[V_REGISTER_SIZE
];
1876 debug_printf ("read HFA or HVA return value element %d from %s\n",
1878 gdbarch_register_name (gdbarch
, regno
));
1880 regs
->cooked_read (regno
, buf
);
1882 memcpy (valbuf
, buf
, len
);
1886 else if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)
1887 && (TYPE_LENGTH (type
) == 16 || TYPE_LENGTH (type
) == 8))
1889 /* Short vector is returned in V register. */
1890 gdb_byte buf
[V_REGISTER_SIZE
];
1892 regs
->cooked_read (AARCH64_V0_REGNUM
, buf
);
1893 memcpy (valbuf
, buf
, TYPE_LENGTH (type
));
1897 /* For a structure or union the behaviour is as if the value had
1898 been stored to word-aligned memory and then loaded into
1899 registers with 64-bit load instruction(s). */
1900 int len
= TYPE_LENGTH (type
);
1901 int regno
= AARCH64_X0_REGNUM
;
1902 bfd_byte buf
[X_REGISTER_SIZE
];
1906 regs
->cooked_read (regno
++, buf
);
1907 memcpy (valbuf
, buf
, len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
1908 len
-= X_REGISTER_SIZE
;
1909 valbuf
+= X_REGISTER_SIZE
;
1915 /* Will a function return an aggregate type in memory or in a
1916 register? Return 0 if an aggregate type can be returned in a
1917 register, 1 if it must be returned in memory. */
1920 aarch64_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
1922 type
= check_typedef (type
);
1924 if (is_hfa_or_hva (type
))
1926 /* v0-v7 are used to return values and one register is allocated
1927 for one member. However, HFA or HVA has at most four members. */
1931 if (TYPE_LENGTH (type
) > 16)
1933 /* PCS B.6 Aggregates larger than 16 bytes are passed by
1934 invisible reference. */
1942 /* Write into appropriate registers a function return value of type
1943 TYPE, given in virtual format. */
1946 aarch64_store_return_value (struct type
*type
, struct regcache
*regs
,
1947 const gdb_byte
*valbuf
)
1949 struct gdbarch
*gdbarch
= regs
->arch ();
1950 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1952 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1954 bfd_byte buf
[V_REGISTER_SIZE
];
1955 int len
= TYPE_LENGTH (type
);
1957 memcpy (buf
, valbuf
, len
> V_REGISTER_SIZE
? V_REGISTER_SIZE
: len
);
1958 regs
->cooked_write (AARCH64_V0_REGNUM
, buf
);
1960 else if (TYPE_CODE (type
) == TYPE_CODE_INT
1961 || TYPE_CODE (type
) == TYPE_CODE_CHAR
1962 || TYPE_CODE (type
) == TYPE_CODE_BOOL
1963 || TYPE_CODE (type
) == TYPE_CODE_PTR
1964 || TYPE_IS_REFERENCE (type
)
1965 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
1967 if (TYPE_LENGTH (type
) <= X_REGISTER_SIZE
)
1969 /* Values of one word or less are zero/sign-extended and
1971 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
1972 LONGEST val
= unpack_long (type
, valbuf
);
1974 store_signed_integer (tmpbuf
, X_REGISTER_SIZE
, byte_order
, val
);
1975 regs
->cooked_write (AARCH64_X0_REGNUM
, tmpbuf
);
1979 /* Integral values greater than one word are stored in
1980 consecutive registers starting with r0. This will always
1981 be a multiple of the regiser size. */
1982 int len
= TYPE_LENGTH (type
);
1983 int regno
= AARCH64_X0_REGNUM
;
1987 regs
->cooked_write (regno
++, valbuf
);
1988 len
-= X_REGISTER_SIZE
;
1989 valbuf
+= X_REGISTER_SIZE
;
1993 else if (is_hfa_or_hva (type
))
1995 int elements
= TYPE_NFIELDS (type
);
1996 struct type
*member_type
= check_typedef (TYPE_FIELD_TYPE (type
, 0));
1997 int len
= TYPE_LENGTH (member_type
);
2000 for (i
= 0; i
< elements
; i
++)
2002 int regno
= AARCH64_V0_REGNUM
+ i
;
2003 bfd_byte tmpbuf
[V_REGISTER_SIZE
];
2007 debug_printf ("write HFA or HVA return value element %d to %s\n",
2009 gdbarch_register_name (gdbarch
, regno
));
2012 memcpy (tmpbuf
, valbuf
, len
);
2013 regs
->cooked_write (regno
, tmpbuf
);
2017 else if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (type
)
2018 && (TYPE_LENGTH (type
) == 8 || TYPE_LENGTH (type
) == 16))
2021 gdb_byte buf
[V_REGISTER_SIZE
];
2023 memcpy (buf
, valbuf
, TYPE_LENGTH (type
));
2024 regs
->cooked_write (AARCH64_V0_REGNUM
, buf
);
2028 /* For a structure or union the behaviour is as if the value had
2029 been stored to word-aligned memory and then loaded into
2030 registers with 64-bit load instruction(s). */
2031 int len
= TYPE_LENGTH (type
);
2032 int regno
= AARCH64_X0_REGNUM
;
2033 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2037 memcpy (tmpbuf
, valbuf
,
2038 len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2039 regs
->cooked_write (regno
++, tmpbuf
);
2040 len
-= X_REGISTER_SIZE
;
2041 valbuf
+= X_REGISTER_SIZE
;
2046 /* Implement the "return_value" gdbarch method. */
2048 static enum return_value_convention
2049 aarch64_return_value (struct gdbarch
*gdbarch
, struct value
*func_value
,
2050 struct type
*valtype
, struct regcache
*regcache
,
2051 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2054 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2055 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2056 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2058 if (aarch64_return_in_memory (gdbarch
, valtype
))
2061 debug_printf ("return value in memory\n");
2062 return RETURN_VALUE_STRUCT_CONVENTION
;
2067 aarch64_store_return_value (valtype
, regcache
, writebuf
);
2070 aarch64_extract_return_value (valtype
, regcache
, readbuf
);
2073 debug_printf ("return value in registers\n");
2075 return RETURN_VALUE_REGISTER_CONVENTION
;
2078 /* Implement the "get_longjmp_target" gdbarch method. */
2081 aarch64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2084 gdb_byte buf
[X_REGISTER_SIZE
];
2085 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2086 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2087 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2089 jb_addr
= get_frame_register_unsigned (frame
, AARCH64_X0_REGNUM
);
2091 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2095 *pc
= extract_unsigned_integer (buf
, X_REGISTER_SIZE
, byte_order
);
2099 /* Implement the "gen_return_address" gdbarch method. */
2102 aarch64_gen_return_address (struct gdbarch
*gdbarch
,
2103 struct agent_expr
*ax
, struct axs_value
*value
,
2106 value
->type
= register_type (gdbarch
, AARCH64_LR_REGNUM
);
2107 value
->kind
= axs_lvalue_register
;
2108 value
->u
.reg
= AARCH64_LR_REGNUM
;
2112 /* Return the pseudo register name corresponding to register regnum. */
2115 aarch64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
2117 static const char *const q_name
[] =
2119 "q0", "q1", "q2", "q3",
2120 "q4", "q5", "q6", "q7",
2121 "q8", "q9", "q10", "q11",
2122 "q12", "q13", "q14", "q15",
2123 "q16", "q17", "q18", "q19",
2124 "q20", "q21", "q22", "q23",
2125 "q24", "q25", "q26", "q27",
2126 "q28", "q29", "q30", "q31",
2129 static const char *const d_name
[] =
2131 "d0", "d1", "d2", "d3",
2132 "d4", "d5", "d6", "d7",
2133 "d8", "d9", "d10", "d11",
2134 "d12", "d13", "d14", "d15",
2135 "d16", "d17", "d18", "d19",
2136 "d20", "d21", "d22", "d23",
2137 "d24", "d25", "d26", "d27",
2138 "d28", "d29", "d30", "d31",
2141 static const char *const s_name
[] =
2143 "s0", "s1", "s2", "s3",
2144 "s4", "s5", "s6", "s7",
2145 "s8", "s9", "s10", "s11",
2146 "s12", "s13", "s14", "s15",
2147 "s16", "s17", "s18", "s19",
2148 "s20", "s21", "s22", "s23",
2149 "s24", "s25", "s26", "s27",
2150 "s28", "s29", "s30", "s31",
2153 static const char *const h_name
[] =
2155 "h0", "h1", "h2", "h3",
2156 "h4", "h5", "h6", "h7",
2157 "h8", "h9", "h10", "h11",
2158 "h12", "h13", "h14", "h15",
2159 "h16", "h17", "h18", "h19",
2160 "h20", "h21", "h22", "h23",
2161 "h24", "h25", "h26", "h27",
2162 "h28", "h29", "h30", "h31",
2165 static const char *const b_name
[] =
2167 "b0", "b1", "b2", "b3",
2168 "b4", "b5", "b6", "b7",
2169 "b8", "b9", "b10", "b11",
2170 "b12", "b13", "b14", "b15",
2171 "b16", "b17", "b18", "b19",
2172 "b20", "b21", "b22", "b23",
2173 "b24", "b25", "b26", "b27",
2174 "b28", "b29", "b30", "b31",
2177 regnum
-= gdbarch_num_regs (gdbarch
);
2179 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2180 return q_name
[regnum
- AARCH64_Q0_REGNUM
];
2182 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2183 return d_name
[regnum
- AARCH64_D0_REGNUM
];
2185 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2186 return s_name
[regnum
- AARCH64_S0_REGNUM
];
2188 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2189 return h_name
[regnum
- AARCH64_H0_REGNUM
];
2191 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2192 return b_name
[regnum
- AARCH64_B0_REGNUM
];
2194 internal_error (__FILE__
, __LINE__
,
2195 _("aarch64_pseudo_register_name: bad register number %d"),
2199 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
2201 static struct type
*
2202 aarch64_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2204 regnum
-= gdbarch_num_regs (gdbarch
);
2206 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2207 return aarch64_vnq_type (gdbarch
);
2209 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2210 return aarch64_vnd_type (gdbarch
);
2212 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2213 return aarch64_vns_type (gdbarch
);
2215 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2216 return aarch64_vnh_type (gdbarch
);
2218 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2219 return aarch64_vnb_type (gdbarch
);
2221 internal_error (__FILE__
, __LINE__
,
2222 _("aarch64_pseudo_register_type: bad register number %d"),
2226 /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2229 aarch64_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2230 struct reggroup
*group
)
2232 regnum
-= gdbarch_num_regs (gdbarch
);
2234 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2235 return group
== all_reggroup
|| group
== vector_reggroup
;
2236 else if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2237 return (group
== all_reggroup
|| group
== vector_reggroup
2238 || group
== float_reggroup
);
2239 else if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2240 return (group
== all_reggroup
|| group
== vector_reggroup
2241 || group
== float_reggroup
);
2242 else if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2243 return group
== all_reggroup
|| group
== vector_reggroup
;
2244 else if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2245 return group
== all_reggroup
|| group
== vector_reggroup
;
2247 return group
== all_reggroup
;
2250 /* Helper for aarch64_pseudo_read_value. */
2252 static struct value
*
2253 aarch64_pseudo_read_value_1 (readable_regcache
*regcache
, int regnum_offset
,
2254 int regsize
, struct value
*result_value
)
2256 gdb_byte reg_buf
[V_REGISTER_SIZE
];
2257 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2259 if (regcache
->raw_read (v_regnum
, reg_buf
) != REG_VALID
)
2260 mark_value_bytes_unavailable (result_value
, 0,
2261 TYPE_LENGTH (value_type (result_value
)));
2263 memcpy (value_contents_raw (result_value
), reg_buf
, regsize
);
2264 return result_value
;
2267 /* Implement the "pseudo_register_read_value" gdbarch method. */
2269 static struct value
*
2270 aarch64_pseudo_read_value (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2273 struct value
*result_value
= allocate_value (register_type (gdbarch
, regnum
));
2275 VALUE_LVAL (result_value
) = lval_register
;
2276 VALUE_REGNUM (result_value
) = regnum
;
2278 regnum
-= gdbarch_num_regs (gdbarch
);
2280 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2281 return aarch64_pseudo_read_value_1 (regcache
, regnum
- AARCH64_Q0_REGNUM
,
2282 Q_REGISTER_SIZE
, result_value
);
2284 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2285 return aarch64_pseudo_read_value_1 (regcache
, regnum
- AARCH64_D0_REGNUM
,
2286 D_REGISTER_SIZE
, result_value
);
2288 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2289 return aarch64_pseudo_read_value_1 (regcache
, regnum
- AARCH64_S0_REGNUM
,
2290 S_REGISTER_SIZE
, result_value
);
2292 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2293 return aarch64_pseudo_read_value_1 (regcache
, regnum
- AARCH64_H0_REGNUM
,
2294 H_REGISTER_SIZE
, result_value
);
2296 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2297 return aarch64_pseudo_read_value_1 (regcache
, regnum
- AARCH64_B0_REGNUM
,
2298 B_REGISTER_SIZE
, result_value
);
2300 gdb_assert_not_reached ("regnum out of bound");
2303 /* Helper for aarch64_pseudo_write. */
2306 aarch64_pseudo_write_1 (struct regcache
*regcache
, int regnum_offset
,
2307 int regsize
, const gdb_byte
*buf
)
2309 gdb_byte reg_buf
[V_REGISTER_SIZE
];
2310 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2312 /* Ensure the register buffer is zero, we want gdb writes of the
2313 various 'scalar' pseudo registers to behavior like architectural
2314 writes, register width bytes are written the remainder are set to
2316 memset (reg_buf
, 0, sizeof (reg_buf
));
2318 memcpy (reg_buf
, buf
, regsize
);
2319 regcache
->raw_write (v_regnum
, reg_buf
);
2322 /* Implement the "pseudo_register_write" gdbarch method. */
2325 aarch64_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2326 int regnum
, const gdb_byte
*buf
)
2328 regnum
-= gdbarch_num_regs (gdbarch
);
2330 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2331 return aarch64_pseudo_write_1 (regcache
, regnum
- AARCH64_Q0_REGNUM
,
2332 Q_REGISTER_SIZE
, buf
);
2334 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2335 return aarch64_pseudo_write_1 (regcache
, regnum
- AARCH64_D0_REGNUM
,
2336 D_REGISTER_SIZE
, buf
);
2338 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2339 return aarch64_pseudo_write_1 (regcache
, regnum
- AARCH64_S0_REGNUM
,
2340 S_REGISTER_SIZE
, buf
);
2342 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2343 return aarch64_pseudo_write_1 (regcache
, regnum
- AARCH64_H0_REGNUM
,
2344 H_REGISTER_SIZE
, buf
);
2346 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2347 return aarch64_pseudo_write_1 (regcache
, regnum
- AARCH64_B0_REGNUM
,
2348 B_REGISTER_SIZE
, buf
);
2350 gdb_assert_not_reached ("regnum out of bound");
2353 /* Callback function for user_reg_add. */
2355 static struct value
*
2356 value_of_aarch64_user_reg (struct frame_info
*frame
, const void *baton
)
2358 const int *reg_p
= (const int *) baton
;
2360 return value_of_register (*reg_p
, frame
);
2364 /* Implement the "software_single_step" gdbarch method, needed to
2365 single step through atomic sequences on AArch64. */
2367 static std::vector
<CORE_ADDR
>
2368 aarch64_software_single_step (struct regcache
*regcache
)
2370 struct gdbarch
*gdbarch
= regcache
->arch ();
2371 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2372 const int insn_size
= 4;
2373 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2374 CORE_ADDR pc
= regcache_read_pc (regcache
);
2375 CORE_ADDR breaks
[2] = { -1, -1 };
2377 CORE_ADDR closing_insn
= 0;
2378 uint32_t insn
= read_memory_unsigned_integer (loc
, insn_size
,
2379 byte_order_for_code
);
2382 int bc_insn_count
= 0; /* Conditional branch instruction count. */
2383 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2386 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2389 /* Look for a Load Exclusive instruction which begins the sequence. */
2390 if (inst
.opcode
->iclass
!= ldstexcl
|| bit (insn
, 22) == 0)
2393 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2396 insn
= read_memory_unsigned_integer (loc
, insn_size
,
2397 byte_order_for_code
);
2399 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2401 /* Check if the instruction is a conditional branch. */
2402 if (inst
.opcode
->iclass
== condbranch
)
2404 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_ADDR_PCREL19
);
2406 if (bc_insn_count
>= 1)
2409 /* It is, so we'll try to set a breakpoint at the destination. */
2410 breaks
[1] = loc
+ inst
.operands
[0].imm
.value
;
2416 /* Look for the Store Exclusive which closes the atomic sequence. */
2417 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22) == 0)
2424 /* We didn't find a closing Store Exclusive instruction, fall back. */
2428 /* Insert breakpoint after the end of the atomic sequence. */
2429 breaks
[0] = loc
+ insn_size
;
2431 /* Check for duplicated breakpoints, and also check that the second
2432 breakpoint is not within the atomic sequence. */
2434 && (breaks
[1] == breaks
[0]
2435 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
2436 last_breakpoint
= 0;
2438 std::vector
<CORE_ADDR
> next_pcs
;
2440 /* Insert the breakpoint at the end of the sequence, and one at the
2441 destination of the conditional branch, if it exists. */
2442 for (index
= 0; index
<= last_breakpoint
; index
++)
2443 next_pcs
.push_back (breaks
[index
]);
2448 struct aarch64_displaced_step_closure
: public displaced_step_closure
2450 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2451 is being displaced stepping. */
2454 /* PC adjustment offset after displaced stepping. */
2455 int32_t pc_adjust
= 0;
2458 /* Data when visiting instructions for displaced stepping. */
2460 struct aarch64_displaced_step_data
2462 struct aarch64_insn_data base
;
2464 /* The address where the instruction will be executed at. */
2466 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2467 uint32_t insn_buf
[DISPLACED_MODIFIED_INSNS
];
2468 /* Number of instructions in INSN_BUF. */
2469 unsigned insn_count
;
2470 /* Registers when doing displaced stepping. */
2471 struct regcache
*regs
;
2473 aarch64_displaced_step_closure
*dsc
;
2476 /* Implementation of aarch64_insn_visitor method "b". */
2479 aarch64_displaced_step_b (const int is_bl
, const int32_t offset
,
2480 struct aarch64_insn_data
*data
)
2482 struct aarch64_displaced_step_data
*dsd
2483 = (struct aarch64_displaced_step_data
*) data
;
2484 int64_t new_offset
= data
->insn_addr
- dsd
->new_addr
+ offset
;
2486 if (can_encode_int32 (new_offset
, 28))
2488 /* Emit B rather than BL, because executing BL on a new address
2489 will get the wrong address into LR. In order to avoid this,
2490 we emit B, and update LR if the instruction is BL. */
2491 emit_b (dsd
->insn_buf
, 0, new_offset
);
2497 emit_nop (dsd
->insn_buf
);
2499 dsd
->dsc
->pc_adjust
= offset
;
2505 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_LR_REGNUM
,
2506 data
->insn_addr
+ 4);
2510 /* Implementation of aarch64_insn_visitor method "b_cond". */
2513 aarch64_displaced_step_b_cond (const unsigned cond
, const int32_t offset
,
2514 struct aarch64_insn_data
*data
)
2516 struct aarch64_displaced_step_data
*dsd
2517 = (struct aarch64_displaced_step_data
*) data
;
2519 /* GDB has to fix up PC after displaced step this instruction
2520 differently according to the condition is true or false. Instead
2521 of checking COND against conditional flags, we can use
2522 the following instructions, and GDB can tell how to fix up PC
2523 according to the PC value.
2525 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2531 emit_bcond (dsd
->insn_buf
, cond
, 8);
2533 dsd
->dsc
->pc_adjust
= offset
;
2534 dsd
->insn_count
= 1;
2537 /* Dynamically allocate a new register. If we know the register
2538 statically, we should make it a global as above instead of using this
2541 static struct aarch64_register
2542 aarch64_register (unsigned num
, int is64
)
2544 return (struct aarch64_register
) { num
, is64
};
2547 /* Implementation of aarch64_insn_visitor method "cb". */
2550 aarch64_displaced_step_cb (const int32_t offset
, const int is_cbnz
,
2551 const unsigned rn
, int is64
,
2552 struct aarch64_insn_data
*data
)
2554 struct aarch64_displaced_step_data
*dsd
2555 = (struct aarch64_displaced_step_data
*) data
;
2557 /* The offset is out of range for a compare and branch
2558 instruction. We can use the following instructions instead:
2560 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2565 emit_cb (dsd
->insn_buf
, is_cbnz
, aarch64_register (rn
, is64
), 8);
2566 dsd
->insn_count
= 1;
2568 dsd
->dsc
->pc_adjust
= offset
;
2571 /* Implementation of aarch64_insn_visitor method "tb". */
2574 aarch64_displaced_step_tb (const int32_t offset
, int is_tbnz
,
2575 const unsigned rt
, unsigned bit
,
2576 struct aarch64_insn_data
*data
)
2578 struct aarch64_displaced_step_data
*dsd
2579 = (struct aarch64_displaced_step_data
*) data
;
2581 /* The offset is out of range for a test bit and branch
2582 instruction We can use the following instructions instead:
2584 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2590 emit_tb (dsd
->insn_buf
, is_tbnz
, bit
, aarch64_register (rt
, 1), 8);
2591 dsd
->insn_count
= 1;
2593 dsd
->dsc
->pc_adjust
= offset
;
2596 /* Implementation of aarch64_insn_visitor method "adr". */
2599 aarch64_displaced_step_adr (const int32_t offset
, const unsigned rd
,
2600 const int is_adrp
, struct aarch64_insn_data
*data
)
2602 struct aarch64_displaced_step_data
*dsd
2603 = (struct aarch64_displaced_step_data
*) data
;
2604 /* We know exactly the address the ADR{P,} instruction will compute.
2605 We can just write it to the destination register. */
2606 CORE_ADDR address
= data
->insn_addr
+ offset
;
2610 /* Clear the lower 12 bits of the offset to get the 4K page. */
2611 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
2615 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
2618 dsd
->dsc
->pc_adjust
= 4;
2619 emit_nop (dsd
->insn_buf
);
2620 dsd
->insn_count
= 1;
2623 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
2626 aarch64_displaced_step_ldr_literal (const int32_t offset
, const int is_sw
,
2627 const unsigned rt
, const int is64
,
2628 struct aarch64_insn_data
*data
)
2630 struct aarch64_displaced_step_data
*dsd
2631 = (struct aarch64_displaced_step_data
*) data
;
2632 CORE_ADDR address
= data
->insn_addr
+ offset
;
2633 struct aarch64_memory_operand zero
= { MEMORY_OPERAND_OFFSET
, 0 };
2635 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rt
,
2639 dsd
->insn_count
= emit_ldrsw (dsd
->insn_buf
, aarch64_register (rt
, 1),
2640 aarch64_register (rt
, 1), zero
);
2642 dsd
->insn_count
= emit_ldr (dsd
->insn_buf
, aarch64_register (rt
, is64
),
2643 aarch64_register (rt
, 1), zero
);
2645 dsd
->dsc
->pc_adjust
= 4;
2648 /* Implementation of aarch64_insn_visitor method "others". */
2651 aarch64_displaced_step_others (const uint32_t insn
,
2652 struct aarch64_insn_data
*data
)
2654 struct aarch64_displaced_step_data
*dsd
2655 = (struct aarch64_displaced_step_data
*) data
;
2657 aarch64_emit_insn (dsd
->insn_buf
, insn
);
2658 dsd
->insn_count
= 1;
2660 if ((insn
& 0xfffffc1f) == 0xd65f0000)
2663 dsd
->dsc
->pc_adjust
= 0;
2666 dsd
->dsc
->pc_adjust
= 4;
2669 static const struct aarch64_insn_visitor visitor
=
2671 aarch64_displaced_step_b
,
2672 aarch64_displaced_step_b_cond
,
2673 aarch64_displaced_step_cb
,
2674 aarch64_displaced_step_tb
,
2675 aarch64_displaced_step_adr
,
2676 aarch64_displaced_step_ldr_literal
,
2677 aarch64_displaced_step_others
,
2680 /* Implement the "displaced_step_copy_insn" gdbarch method. */
2682 struct displaced_step_closure
*
2683 aarch64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
2684 CORE_ADDR from
, CORE_ADDR to
,
2685 struct regcache
*regs
)
2687 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2688 uint32_t insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
2689 struct aarch64_displaced_step_data dsd
;
2692 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2695 /* Look for a Load Exclusive instruction which begins the sequence. */
2696 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22))
2698 /* We can't displaced step atomic sequences. */
2702 std::unique_ptr
<aarch64_displaced_step_closure
> dsc
2703 (new aarch64_displaced_step_closure
);
2704 dsd
.base
.insn_addr
= from
;
2707 dsd
.dsc
= dsc
.get ();
2709 aarch64_relocate_instruction (insn
, &visitor
,
2710 (struct aarch64_insn_data
*) &dsd
);
2711 gdb_assert (dsd
.insn_count
<= DISPLACED_MODIFIED_INSNS
);
2713 if (dsd
.insn_count
!= 0)
2717 /* Instruction can be relocated to scratch pad. Copy
2718 relocated instruction(s) there. */
2719 for (i
= 0; i
< dsd
.insn_count
; i
++)
2721 if (debug_displaced
)
2723 debug_printf ("displaced: writing insn ");
2724 debug_printf ("%.8x", dsd
.insn_buf
[i
]);
2725 debug_printf (" at %s\n", paddress (gdbarch
, to
+ i
* 4));
2727 write_memory_unsigned_integer (to
+ i
* 4, 4, byte_order_for_code
,
2728 (ULONGEST
) dsd
.insn_buf
[i
]);
2736 return dsc
.release ();
2739 /* Implement the "displaced_step_fixup" gdbarch method. */
2742 aarch64_displaced_step_fixup (struct gdbarch
*gdbarch
,
2743 struct displaced_step_closure
*dsc_
,
2744 CORE_ADDR from
, CORE_ADDR to
,
2745 struct regcache
*regs
)
2747 aarch64_displaced_step_closure
*dsc
= (aarch64_displaced_step_closure
*) dsc_
;
2753 regcache_cooked_read_unsigned (regs
, AARCH64_PC_REGNUM
, &pc
);
2756 /* Condition is true. */
2758 else if (pc
- to
== 4)
2760 /* Condition is false. */
2764 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
2767 if (dsc
->pc_adjust
!= 0)
2769 if (debug_displaced
)
2771 debug_printf ("displaced: fixup: set PC to %s:%d\n",
2772 paddress (gdbarch
, from
), dsc
->pc_adjust
);
2774 regcache_cooked_write_unsigned (regs
, AARCH64_PC_REGNUM
,
2775 from
+ dsc
->pc_adjust
);
2779 /* Implement the "displaced_step_hw_singlestep" gdbarch method. */
2782 aarch64_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
2783 struct displaced_step_closure
*closure
)
2788 /* Get the correct target description for the given VQ value.
2789 If VQ is zero then it is assumed SVE is not supported.
2790 (It is not possible to set VQ to zero on an SVE system). */
2793 aarch64_read_description (uint64_t vq
)
2795 if (vq
> AARCH64_MAX_SVE_VQ
)
2796 error (_("VQ is %" PRIu64
", maximum supported value is %d"), vq
,
2797 AARCH64_MAX_SVE_VQ
);
2799 struct target_desc
*tdesc
= tdesc_aarch64_list
[vq
];
2803 tdesc
= aarch64_create_target_description (vq
);
2804 tdesc_aarch64_list
[vq
] = tdesc
;
2810 /* Return the VQ used when creating the target description TDESC. */
2813 aarch64_get_tdesc_vq (const struct target_desc
*tdesc
)
2815 const struct tdesc_feature
*feature_sve
;
2817 if (!tdesc_has_registers (tdesc
))
2820 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
2822 if (feature_sve
== nullptr)
2825 uint64_t vl
= tdesc_register_size (feature_sve
,
2826 aarch64_sve_register_names
[0]);
2827 return sve_vq_from_vl (vl
);
2831 /* Initialize the current architecture based on INFO. If possible,
2832 re-use an architecture from ARCHES, which is a list of
2833 architectures already created during this debugging session.
2835 Called e.g. at program startup, when reading a core file, and when
2836 reading a binary file. */
2838 static struct gdbarch
*
2839 aarch64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2841 struct gdbarch_tdep
*tdep
;
2842 struct gdbarch
*gdbarch
;
2843 struct gdbarch_list
*best_arch
;
2844 struct tdesc_arch_data
*tdesc_data
= NULL
;
2845 const struct target_desc
*tdesc
= info
.target_desc
;
2848 const struct tdesc_feature
*feature_core
;
2849 const struct tdesc_feature
*feature_fpu
;
2850 const struct tdesc_feature
*feature_sve
;
2852 int num_pseudo_regs
= 0;
2854 /* Ensure we always have a target description. */
2855 if (!tdesc_has_registers (tdesc
))
2856 tdesc
= aarch64_read_description (0);
2859 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.core");
2860 feature_fpu
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.fpu");
2861 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
2863 if (feature_core
== NULL
)
2866 tdesc_data
= tdesc_data_alloc ();
2868 /* Validate the description provides the mandatory core R registers
2869 and allocate their numbers. */
2870 for (i
= 0; i
< ARRAY_SIZE (aarch64_r_register_names
); i
++)
2871 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
,
2872 AARCH64_X0_REGNUM
+ i
,
2873 aarch64_r_register_names
[i
]);
2875 num_regs
= AARCH64_X0_REGNUM
+ i
;
2877 /* Add the V registers. */
2878 if (feature_fpu
!= NULL
)
2880 if (feature_sve
!= NULL
)
2881 error (_("Program contains both fpu and SVE features."));
2883 /* Validate the description provides the mandatory V registers
2884 and allocate their numbers. */
2885 for (i
= 0; i
< ARRAY_SIZE (aarch64_v_register_names
); i
++)
2886 valid_p
&= tdesc_numbered_register (feature_fpu
, tdesc_data
,
2887 AARCH64_V0_REGNUM
+ i
,
2888 aarch64_v_register_names
[i
]);
2890 num_regs
= AARCH64_V0_REGNUM
+ i
;
2893 /* Add the SVE registers. */
2894 if (feature_sve
!= NULL
)
2896 /* Validate the description provides the mandatory SVE registers
2897 and allocate their numbers. */
2898 for (i
= 0; i
< ARRAY_SIZE (aarch64_sve_register_names
); i
++)
2899 valid_p
&= tdesc_numbered_register (feature_sve
, tdesc_data
,
2900 AARCH64_SVE_Z0_REGNUM
+ i
,
2901 aarch64_sve_register_names
[i
]);
2903 num_regs
= AARCH64_SVE_Z0_REGNUM
+ i
;
2904 num_pseudo_regs
+= 32; /* add the Vn register pseudos. */
2907 if (feature_fpu
!= NULL
|| feature_sve
!= NULL
)
2909 num_pseudo_regs
+= 32; /* add the Qn scalar register pseudos */
2910 num_pseudo_regs
+= 32; /* add the Dn scalar register pseudos */
2911 num_pseudo_regs
+= 32; /* add the Sn scalar register pseudos */
2912 num_pseudo_regs
+= 32; /* add the Hn scalar register pseudos */
2913 num_pseudo_regs
+= 32; /* add the Bn scalar register pseudos */
2918 tdesc_data_cleanup (tdesc_data
);
2922 /* AArch64 code is always little-endian. */
2923 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
2925 /* If there is already a candidate, use it. */
2926 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
2928 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
2930 /* Found a match. */
2934 if (best_arch
!= NULL
)
2936 if (tdesc_data
!= NULL
)
2937 tdesc_data_cleanup (tdesc_data
);
2938 return best_arch
->gdbarch
;
2941 tdep
= XCNEW (struct gdbarch_tdep
);
2942 gdbarch
= gdbarch_alloc (&info
, tdep
);
2944 /* This should be low enough for everything. */
2945 tdep
->lowest_pc
= 0x20;
2946 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2947 tdep
->jb_elt_size
= 8;
2948 tdep
->vq
= aarch64_get_tdesc_vq (tdesc
);
2950 set_gdbarch_push_dummy_call (gdbarch
, aarch64_push_dummy_call
);
2951 set_gdbarch_frame_align (gdbarch
, aarch64_frame_align
);
2953 /* Frame handling. */
2954 set_gdbarch_dummy_id (gdbarch
, aarch64_dummy_id
);
2955 set_gdbarch_unwind_pc (gdbarch
, aarch64_unwind_pc
);
2956 set_gdbarch_unwind_sp (gdbarch
, aarch64_unwind_sp
);
2958 /* Advance PC across function entry code. */
2959 set_gdbarch_skip_prologue (gdbarch
, aarch64_skip_prologue
);
2961 /* The stack grows downward. */
2962 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2964 /* Breakpoint manipulation. */
2965 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
2966 aarch64_breakpoint::kind_from_pc
);
2967 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
2968 aarch64_breakpoint::bp_from_kind
);
2969 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
2970 set_gdbarch_software_single_step (gdbarch
, aarch64_software_single_step
);
2972 /* Information about registers, etc. */
2973 set_gdbarch_sp_regnum (gdbarch
, AARCH64_SP_REGNUM
);
2974 set_gdbarch_pc_regnum (gdbarch
, AARCH64_PC_REGNUM
);
2975 set_gdbarch_num_regs (gdbarch
, num_regs
);
2977 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudo_regs
);
2978 set_gdbarch_pseudo_register_read_value (gdbarch
, aarch64_pseudo_read_value
);
2979 set_gdbarch_pseudo_register_write (gdbarch
, aarch64_pseudo_write
);
2980 set_tdesc_pseudo_register_name (gdbarch
, aarch64_pseudo_register_name
);
2981 set_tdesc_pseudo_register_type (gdbarch
, aarch64_pseudo_register_type
);
2982 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
2983 aarch64_pseudo_register_reggroup_p
);
2986 set_gdbarch_short_bit (gdbarch
, 16);
2987 set_gdbarch_int_bit (gdbarch
, 32);
2988 set_gdbarch_float_bit (gdbarch
, 32);
2989 set_gdbarch_double_bit (gdbarch
, 64);
2990 set_gdbarch_long_double_bit (gdbarch
, 128);
2991 set_gdbarch_long_bit (gdbarch
, 64);
2992 set_gdbarch_long_long_bit (gdbarch
, 64);
2993 set_gdbarch_ptr_bit (gdbarch
, 64);
2994 set_gdbarch_char_signed (gdbarch
, 0);
2995 set_gdbarch_wchar_signed (gdbarch
, 0);
2996 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
2997 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
2998 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
3000 /* Internal <-> external register number maps. */
3001 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, aarch64_dwarf_reg_to_regnum
);
3003 /* Returning results. */
3004 set_gdbarch_return_value (gdbarch
, aarch64_return_value
);
3007 set_gdbarch_print_insn (gdbarch
, aarch64_gdb_print_insn
);
3009 /* Virtual tables. */
3010 set_gdbarch_vbit_in_delta (gdbarch
, 1);
3012 /* Hook in the ABI-specific overrides, if they have been registered. */
3013 info
.target_desc
= tdesc
;
3014 info
.tdesc_data
= tdesc_data
;
3015 gdbarch_init_osabi (info
, gdbarch
);
3017 dwarf2_frame_set_init_reg (gdbarch
, aarch64_dwarf2_frame_init_reg
);
3019 /* Add some default predicates. */
3020 frame_unwind_append_unwinder (gdbarch
, &aarch64_stub_unwind
);
3021 dwarf2_append_unwinders (gdbarch
);
3022 frame_unwind_append_unwinder (gdbarch
, &aarch64_prologue_unwind
);
3024 frame_base_set_default (gdbarch
, &aarch64_normal_base
);
3026 /* Now we have tuned the configuration, set a few final things,
3027 based on what the OS ABI has told us. */
3029 if (tdep
->jb_pc
>= 0)
3030 set_gdbarch_get_longjmp_target (gdbarch
, aarch64_get_longjmp_target
);
3032 set_gdbarch_gen_return_address (gdbarch
, aarch64_gen_return_address
);
3034 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
3036 /* Add standard register aliases. */
3037 for (i
= 0; i
< ARRAY_SIZE (aarch64_register_aliases
); i
++)
3038 user_reg_add (gdbarch
, aarch64_register_aliases
[i
].name
,
3039 value_of_aarch64_user_reg
,
3040 &aarch64_register_aliases
[i
].regnum
);
3046 aarch64_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3048 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3053 fprintf_unfiltered (file
, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3054 paddress (gdbarch
, tdep
->lowest_pc
));
3060 static void aarch64_process_record_test (void);
3065 _initialize_aarch64_tdep (void)
3067 gdbarch_register (bfd_arch_aarch64
, aarch64_gdbarch_init
,
3070 /* Debug this file's internals. */
3071 add_setshow_boolean_cmd ("aarch64", class_maintenance
, &aarch64_debug
, _("\
3072 Set AArch64 debugging."), _("\
3073 Show AArch64 debugging."), _("\
3074 When on, AArch64 specific debugging is enabled."),
3077 &setdebuglist
, &showdebuglist
);
3080 selftests::register_test ("aarch64-analyze-prologue",
3081 selftests::aarch64_analyze_prologue_test
);
3082 selftests::register_test ("aarch64-process-record",
3083 selftests::aarch64_process_record_test
);
3084 selftests::record_xml_tdesc ("aarch64.xml",
3085 aarch64_create_target_description (0));
3089 /* AArch64 process record-replay related structures, defines etc. */
3091 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3094 unsigned int reg_len = LENGTH; \
3097 REGS = XNEWVEC (uint32_t, reg_len); \
3098 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3103 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3106 unsigned int mem_len = LENGTH; \
3109 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3110 memcpy(&MEMS->len, &RECORD_BUF[0], \
3111 sizeof(struct aarch64_mem_r) * LENGTH); \
3116 /* AArch64 record/replay structures and enumerations. */
3118 struct aarch64_mem_r
3120 uint64_t len
; /* Record length. */
3121 uint64_t addr
; /* Memory address. */
3124 enum aarch64_record_result
3126 AARCH64_RECORD_SUCCESS
,
3127 AARCH64_RECORD_UNSUPPORTED
,
3128 AARCH64_RECORD_UNKNOWN
3131 typedef struct insn_decode_record_t
3133 struct gdbarch
*gdbarch
;
3134 struct regcache
*regcache
;
3135 CORE_ADDR this_addr
; /* Address of insn to be recorded. */
3136 uint32_t aarch64_insn
; /* Insn to be recorded. */
3137 uint32_t mem_rec_count
; /* Count of memory records. */
3138 uint32_t reg_rec_count
; /* Count of register records. */
3139 uint32_t *aarch64_regs
; /* Registers to be recorded. */
3140 struct aarch64_mem_r
*aarch64_mems
; /* Memory locations to be recorded. */
3141 } insn_decode_record
;
3143 /* Record handler for data processing - register instructions. */
3146 aarch64_record_data_proc_reg (insn_decode_record
*aarch64_insn_r
)
3148 uint8_t reg_rd
, insn_bits24_27
, insn_bits21_23
;
3149 uint32_t record_buf
[4];
3151 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3152 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3153 insn_bits21_23
= bits (aarch64_insn_r
->aarch64_insn
, 21, 23);
3155 if (!bit (aarch64_insn_r
->aarch64_insn
, 28))
3159 /* Logical (shifted register). */
3160 if (insn_bits24_27
== 0x0a)
3161 setflags
= (bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03);
3163 else if (insn_bits24_27
== 0x0b)
3164 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3166 return AARCH64_RECORD_UNKNOWN
;
3168 record_buf
[0] = reg_rd
;
3169 aarch64_insn_r
->reg_rec_count
= 1;
3171 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3175 if (insn_bits24_27
== 0x0b)
3177 /* Data-processing (3 source). */
3178 record_buf
[0] = reg_rd
;
3179 aarch64_insn_r
->reg_rec_count
= 1;
3181 else if (insn_bits24_27
== 0x0a)
3183 if (insn_bits21_23
== 0x00)
3185 /* Add/subtract (with carry). */
3186 record_buf
[0] = reg_rd
;
3187 aarch64_insn_r
->reg_rec_count
= 1;
3188 if (bit (aarch64_insn_r
->aarch64_insn
, 29))
3190 record_buf
[1] = AARCH64_CPSR_REGNUM
;
3191 aarch64_insn_r
->reg_rec_count
= 2;
3194 else if (insn_bits21_23
== 0x02)
3196 /* Conditional compare (register) and conditional compare
3197 (immediate) instructions. */
3198 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3199 aarch64_insn_r
->reg_rec_count
= 1;
3201 else if (insn_bits21_23
== 0x04 || insn_bits21_23
== 0x06)
3203 /* CConditional select. */
3204 /* Data-processing (2 source). */
3205 /* Data-processing (1 source). */
3206 record_buf
[0] = reg_rd
;
3207 aarch64_insn_r
->reg_rec_count
= 1;
3210 return AARCH64_RECORD_UNKNOWN
;
3214 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3216 return AARCH64_RECORD_SUCCESS
;
3219 /* Record handler for data processing - immediate instructions. */
3222 aarch64_record_data_proc_imm (insn_decode_record
*aarch64_insn_r
)
3224 uint8_t reg_rd
, insn_bit23
, insn_bits24_27
, setflags
;
3225 uint32_t record_buf
[4];
3227 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3228 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3229 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3231 if (insn_bits24_27
== 0x00 /* PC rel addressing. */
3232 || insn_bits24_27
== 0x03 /* Bitfield and Extract. */
3233 || (insn_bits24_27
== 0x02 && insn_bit23
)) /* Move wide (immediate). */
3235 record_buf
[0] = reg_rd
;
3236 aarch64_insn_r
->reg_rec_count
= 1;
3238 else if (insn_bits24_27
== 0x01)
3240 /* Add/Subtract (immediate). */
3241 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3242 record_buf
[0] = reg_rd
;
3243 aarch64_insn_r
->reg_rec_count
= 1;
3245 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3247 else if (insn_bits24_27
== 0x02 && !insn_bit23
)
3249 /* Logical (immediate). */
3250 setflags
= bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03;
3251 record_buf
[0] = reg_rd
;
3252 aarch64_insn_r
->reg_rec_count
= 1;
3254 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3257 return AARCH64_RECORD_UNKNOWN
;
3259 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3261 return AARCH64_RECORD_SUCCESS
;
3264 /* Record handler for branch, exception generation and system instructions. */
3267 aarch64_record_branch_except_sys (insn_decode_record
*aarch64_insn_r
)
3269 struct gdbarch_tdep
*tdep
= gdbarch_tdep (aarch64_insn_r
->gdbarch
);
3270 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits22_23
;
3271 uint32_t record_buf
[4];
3273 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3274 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
3275 insn_bits22_23
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3277 if (insn_bits28_31
== 0x0d)
3279 /* Exception generation instructions. */
3280 if (insn_bits24_27
== 0x04)
3282 if (!bits (aarch64_insn_r
->aarch64_insn
, 2, 4)
3283 && !bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
3284 && bits (aarch64_insn_r
->aarch64_insn
, 0, 1) == 0x01)
3286 ULONGEST svc_number
;
3288 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, 8,
3290 return tdep
->aarch64_syscall_record (aarch64_insn_r
->regcache
,
3294 return AARCH64_RECORD_UNSUPPORTED
;
3296 /* System instructions. */
3297 else if (insn_bits24_27
== 0x05 && insn_bits22_23
== 0x00)
3299 uint32_t reg_rt
, reg_crn
;
3301 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3302 reg_crn
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3304 /* Record rt in case of sysl and mrs instructions. */
3305 if (bit (aarch64_insn_r
->aarch64_insn
, 21))
3307 record_buf
[0] = reg_rt
;
3308 aarch64_insn_r
->reg_rec_count
= 1;
3310 /* Record cpsr for hint and msr(immediate) instructions. */
3311 else if (reg_crn
== 0x02 || reg_crn
== 0x04)
3313 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3314 aarch64_insn_r
->reg_rec_count
= 1;
3317 /* Unconditional branch (register). */
3318 else if((insn_bits24_27
& 0x0e) == 0x06)
3320 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3321 if (bits (aarch64_insn_r
->aarch64_insn
, 21, 22) == 0x01)
3322 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3325 return AARCH64_RECORD_UNKNOWN
;
3327 /* Unconditional branch (immediate). */
3328 else if ((insn_bits28_31
& 0x07) == 0x01 && (insn_bits24_27
& 0x0c) == 0x04)
3330 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3331 if (bit (aarch64_insn_r
->aarch64_insn
, 31))
3332 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3335 /* Compare & branch (immediate), Test & branch (immediate) and
3336 Conditional branch (immediate). */
3337 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3339 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3341 return AARCH64_RECORD_SUCCESS
;
3344 /* Record handler for advanced SIMD load and store instructions. */
3347 aarch64_record_asimd_load_store (insn_decode_record
*aarch64_insn_r
)
3350 uint64_t addr_offset
= 0;
3351 uint32_t record_buf
[24];
3352 uint64_t record_buf_mem
[24];
3353 uint32_t reg_rn
, reg_rt
;
3354 uint32_t reg_index
= 0, mem_index
= 0;
3355 uint8_t opcode_bits
, size_bits
;
3357 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3358 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3359 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3360 opcode_bits
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3361 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
, &address
);
3364 debug_printf ("Process record: Advanced SIMD load/store\n");
3366 /* Load/store single structure. */
3367 if (bit (aarch64_insn_r
->aarch64_insn
, 24))
3369 uint8_t sindex
, scale
, selem
, esize
, replicate
= 0;
3370 scale
= opcode_bits
>> 2;
3371 selem
= ((opcode_bits
& 0x02) |
3372 bit (aarch64_insn_r
->aarch64_insn
, 21)) + 1;
3376 if (size_bits
& 0x01)
3377 return AARCH64_RECORD_UNKNOWN
;
3380 if ((size_bits
>> 1) & 0x01)
3381 return AARCH64_RECORD_UNKNOWN
;
3382 if (size_bits
& 0x01)
3384 if (!((opcode_bits
>> 1) & 0x01))
3387 return AARCH64_RECORD_UNKNOWN
;
3391 if (bit (aarch64_insn_r
->aarch64_insn
, 22) && !(opcode_bits
& 0x01))
3398 return AARCH64_RECORD_UNKNOWN
;
3404 for (sindex
= 0; sindex
< selem
; sindex
++)
3406 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3407 reg_rt
= (reg_rt
+ 1) % 32;
3411 for (sindex
= 0; sindex
< selem
; sindex
++)
3413 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3414 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3417 record_buf_mem
[mem_index
++] = esize
/ 8;
3418 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3420 addr_offset
= addr_offset
+ (esize
/ 8);
3421 reg_rt
= (reg_rt
+ 1) % 32;
3425 /* Load/store multiple structure. */
3428 uint8_t selem
, esize
, rpt
, elements
;
3429 uint8_t eindex
, rindex
;
3431 esize
= 8 << size_bits
;
3432 if (bit (aarch64_insn_r
->aarch64_insn
, 30))
3433 elements
= 128 / esize
;
3435 elements
= 64 / esize
;
3437 switch (opcode_bits
)
3439 /*LD/ST4 (4 Registers). */
3444 /*LD/ST1 (4 Registers). */
3449 /*LD/ST3 (3 Registers). */
3454 /*LD/ST1 (3 Registers). */
3459 /*LD/ST1 (1 Register). */
3464 /*LD/ST2 (2 Registers). */
3469 /*LD/ST1 (2 Registers). */
3475 return AARCH64_RECORD_UNSUPPORTED
;
3478 for (rindex
= 0; rindex
< rpt
; rindex
++)
3479 for (eindex
= 0; eindex
< elements
; eindex
++)
3481 uint8_t reg_tt
, sindex
;
3482 reg_tt
= (reg_rt
+ rindex
) % 32;
3483 for (sindex
= 0; sindex
< selem
; sindex
++)
3485 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3486 record_buf
[reg_index
++] = reg_tt
+ AARCH64_V0_REGNUM
;
3489 record_buf_mem
[mem_index
++] = esize
/ 8;
3490 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3492 addr_offset
= addr_offset
+ (esize
/ 8);
3493 reg_tt
= (reg_tt
+ 1) % 32;
3498 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
3499 record_buf
[reg_index
++] = reg_rn
;
3501 aarch64_insn_r
->reg_rec_count
= reg_index
;
3502 aarch64_insn_r
->mem_rec_count
= mem_index
/ 2;
3503 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
3505 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3507 return AARCH64_RECORD_SUCCESS
;
3510 /* Record handler for load and store instructions. */
3513 aarch64_record_load_store (insn_decode_record
*aarch64_insn_r
)
3515 uint8_t insn_bits24_27
, insn_bits28_29
, insn_bits10_11
;
3516 uint8_t insn_bit23
, insn_bit21
;
3517 uint8_t opc
, size_bits
, ld_flag
, vector_flag
;
3518 uint32_t reg_rn
, reg_rt
, reg_rt2
;
3519 uint64_t datasize
, offset
;
3520 uint32_t record_buf
[8];
3521 uint64_t record_buf_mem
[8];
3524 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3525 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3526 insn_bits28_29
= bits (aarch64_insn_r
->aarch64_insn
, 28, 29);
3527 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
3528 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3529 ld_flag
= bit (aarch64_insn_r
->aarch64_insn
, 22);
3530 vector_flag
= bit (aarch64_insn_r
->aarch64_insn
, 26);
3531 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3532 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3533 reg_rt2
= bits (aarch64_insn_r
->aarch64_insn
, 10, 14);
3534 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 30, 31);
3536 /* Load/store exclusive. */
3537 if (insn_bits24_27
== 0x08 && insn_bits28_29
== 0x00)
3540 debug_printf ("Process record: load/store exclusive\n");
3544 record_buf
[0] = reg_rt
;
3545 aarch64_insn_r
->reg_rec_count
= 1;
3548 record_buf
[1] = reg_rt2
;
3549 aarch64_insn_r
->reg_rec_count
= 2;
3555 datasize
= (8 << size_bits
) * 2;
3557 datasize
= (8 << size_bits
);
3558 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3560 record_buf_mem
[0] = datasize
/ 8;
3561 record_buf_mem
[1] = address
;
3562 aarch64_insn_r
->mem_rec_count
= 1;
3565 /* Save register rs. */
3566 record_buf
[0] = bits (aarch64_insn_r
->aarch64_insn
, 16, 20);
3567 aarch64_insn_r
->reg_rec_count
= 1;
3571 /* Load register (literal) instructions decoding. */
3572 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x01)
3575 debug_printf ("Process record: load register (literal)\n");
3577 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3579 record_buf
[0] = reg_rt
;
3580 aarch64_insn_r
->reg_rec_count
= 1;
3582 /* All types of load/store pair instructions decoding. */
3583 else if ((insn_bits24_27
& 0x0a) == 0x08 && insn_bits28_29
== 0x02)
3586 debug_printf ("Process record: load/store pair\n");
3592 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3593 record_buf
[1] = reg_rt2
+ AARCH64_V0_REGNUM
;
3597 record_buf
[0] = reg_rt
;
3598 record_buf
[1] = reg_rt2
;
3600 aarch64_insn_r
->reg_rec_count
= 2;
3605 imm7_off
= bits (aarch64_insn_r
->aarch64_insn
, 15, 21);
3607 size_bits
= size_bits
>> 1;
3608 datasize
= 8 << (2 + size_bits
);
3609 offset
= (imm7_off
& 0x40) ? (~imm7_off
& 0x007f) + 1 : imm7_off
;
3610 offset
= offset
<< (2 + size_bits
);
3611 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3613 if (!((insn_bits24_27
& 0x0b) == 0x08 && insn_bit23
))
3615 if (imm7_off
& 0x40)
3616 address
= address
- offset
;
3618 address
= address
+ offset
;
3621 record_buf_mem
[0] = datasize
/ 8;
3622 record_buf_mem
[1] = address
;
3623 record_buf_mem
[2] = datasize
/ 8;
3624 record_buf_mem
[3] = address
+ (datasize
/ 8);
3625 aarch64_insn_r
->mem_rec_count
= 2;
3627 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
3628 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
3630 /* Load/store register (unsigned immediate) instructions. */
3631 else if ((insn_bits24_27
& 0x0b) == 0x09 && insn_bits28_29
== 0x03)
3633 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3643 if (size_bits
== 0x3 && vector_flag
== 0x0 && opc
== 0x2)
3645 /* PRFM (immediate) */
3646 return AARCH64_RECORD_SUCCESS
;
3648 else if (size_bits
== 0x2 && vector_flag
== 0x0 && opc
== 0x2)
3650 /* LDRSW (immediate) */
3664 debug_printf ("Process record: load/store (unsigned immediate):"
3665 " size %x V %d opc %x\n", size_bits
, vector_flag
,
3671 offset
= bits (aarch64_insn_r
->aarch64_insn
, 10, 21);
3672 datasize
= 8 << size_bits
;
3673 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3675 offset
= offset
<< size_bits
;
3676 address
= address
+ offset
;
3678 record_buf_mem
[0] = datasize
>> 3;
3679 record_buf_mem
[1] = address
;
3680 aarch64_insn_r
->mem_rec_count
= 1;
3685 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3687 record_buf
[0] = reg_rt
;
3688 aarch64_insn_r
->reg_rec_count
= 1;
3691 /* Load/store register (register offset) instructions. */
3692 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
3693 && insn_bits10_11
== 0x02 && insn_bit21
)
3696 debug_printf ("Process record: load/store (register offset)\n");
3697 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3704 if (size_bits
!= 0x03)
3707 return AARCH64_RECORD_UNKNOWN
;
3711 ULONGEST reg_rm_val
;
3713 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
,
3714 bits (aarch64_insn_r
->aarch64_insn
, 16, 20), ®_rm_val
);
3715 if (bit (aarch64_insn_r
->aarch64_insn
, 12))
3716 offset
= reg_rm_val
<< size_bits
;
3718 offset
= reg_rm_val
;
3719 datasize
= 8 << size_bits
;
3720 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3722 address
= address
+ offset
;
3723 record_buf_mem
[0] = datasize
>> 3;
3724 record_buf_mem
[1] = address
;
3725 aarch64_insn_r
->mem_rec_count
= 1;
3730 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3732 record_buf
[0] = reg_rt
;
3733 aarch64_insn_r
->reg_rec_count
= 1;
3736 /* Load/store register (immediate and unprivileged) instructions. */
3737 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
3742 debug_printf ("Process record: load/store "
3743 "(immediate and unprivileged)\n");
3745 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3752 if (size_bits
!= 0x03)
3755 return AARCH64_RECORD_UNKNOWN
;
3760 imm9_off
= bits (aarch64_insn_r
->aarch64_insn
, 12, 20);
3761 offset
= (imm9_off
& 0x0100) ? (((~imm9_off
) & 0x01ff) + 1) : imm9_off
;
3762 datasize
= 8 << size_bits
;
3763 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3765 if (insn_bits10_11
!= 0x01)
3767 if (imm9_off
& 0x0100)
3768 address
= address
- offset
;
3770 address
= address
+ offset
;
3772 record_buf_mem
[0] = datasize
>> 3;
3773 record_buf_mem
[1] = address
;
3774 aarch64_insn_r
->mem_rec_count
= 1;
3779 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3781 record_buf
[0] = reg_rt
;
3782 aarch64_insn_r
->reg_rec_count
= 1;
3784 if (insn_bits10_11
== 0x01 || insn_bits10_11
== 0x03)
3785 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
3787 /* Advanced SIMD load/store instructions. */
3789 return aarch64_record_asimd_load_store (aarch64_insn_r
);
3791 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
3793 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3795 return AARCH64_RECORD_SUCCESS
;
3798 /* Record handler for data processing SIMD and floating point instructions. */
3801 aarch64_record_data_proc_simd_fp (insn_decode_record
*aarch64_insn_r
)
3803 uint8_t insn_bit21
, opcode
, rmode
, reg_rd
;
3804 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits10_11
, insn_bits12_15
;
3805 uint8_t insn_bits11_14
;
3806 uint32_t record_buf
[2];
3808 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3809 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
3810 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3811 insn_bits12_15
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3812 insn_bits11_14
= bits (aarch64_insn_r
->aarch64_insn
, 11, 14);
3813 opcode
= bits (aarch64_insn_r
->aarch64_insn
, 16, 18);
3814 rmode
= bits (aarch64_insn_r
->aarch64_insn
, 19, 20);
3815 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3816 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
3819 debug_printf ("Process record: data processing SIMD/FP: ");
3821 if ((insn_bits28_31
& 0x05) == 0x01 && insn_bits24_27
== 0x0e)
3823 /* Floating point - fixed point conversion instructions. */
3827 debug_printf ("FP - fixed point conversion");
3829 if ((opcode
>> 1) == 0x0 && rmode
== 0x03)
3830 record_buf
[0] = reg_rd
;
3832 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
3834 /* Floating point - conditional compare instructions. */
3835 else if (insn_bits10_11
== 0x01)
3838 debug_printf ("FP - conditional compare");
3840 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3842 /* Floating point - data processing (2-source) and
3843 conditional select instructions. */
3844 else if (insn_bits10_11
== 0x02 || insn_bits10_11
== 0x03)
3847 debug_printf ("FP - DP (2-source)");
3849 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
3851 else if (insn_bits10_11
== 0x00)
3853 /* Floating point - immediate instructions. */
3854 if ((insn_bits12_15
& 0x01) == 0x01
3855 || (insn_bits12_15
& 0x07) == 0x04)
3858 debug_printf ("FP - immediate");
3859 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
3861 /* Floating point - compare instructions. */
3862 else if ((insn_bits12_15
& 0x03) == 0x02)
3865 debug_printf ("FP - immediate");
3866 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3868 /* Floating point - integer conversions instructions. */
3869 else if (insn_bits12_15
== 0x00)
3871 /* Convert float to integer instruction. */
3872 if (!(opcode
>> 1) || ((opcode
>> 1) == 0x02 && !rmode
))
3875 debug_printf ("float to int conversion");
3877 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
3879 /* Convert integer to float instruction. */
3880 else if ((opcode
>> 1) == 0x01 && !rmode
)
3883 debug_printf ("int to float conversion");
3885 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
3887 /* Move float to integer instruction. */
3888 else if ((opcode
>> 1) == 0x03)
3891 debug_printf ("move float to int");
3893 if (!(opcode
& 0x01))
3894 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
3896 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
3899 return AARCH64_RECORD_UNKNOWN
;
3902 return AARCH64_RECORD_UNKNOWN
;
3905 return AARCH64_RECORD_UNKNOWN
;
3907 else if ((insn_bits28_31
& 0x09) == 0x00 && insn_bits24_27
== 0x0e)
3910 debug_printf ("SIMD copy");
3912 /* Advanced SIMD copy instructions. */
3913 if (!bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
3914 && !bit (aarch64_insn_r
->aarch64_insn
, 15)
3915 && bit (aarch64_insn_r
->aarch64_insn
, 10))
3917 if (insn_bits11_14
== 0x05 || insn_bits11_14
== 0x07)
3918 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
3920 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
3923 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
3925 /* All remaining floating point or advanced SIMD instructions. */
3929 debug_printf ("all remain");
3931 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
3935 debug_printf ("\n");
3937 aarch64_insn_r
->reg_rec_count
++;
3938 gdb_assert (aarch64_insn_r
->reg_rec_count
== 1);
3939 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3941 return AARCH64_RECORD_SUCCESS
;
3944 /* Decodes insns type and invokes its record handler. */
3947 aarch64_record_decode_insn_handler (insn_decode_record
*aarch64_insn_r
)
3949 uint32_t ins_bit25
, ins_bit26
, ins_bit27
, ins_bit28
;
3951 ins_bit25
= bit (aarch64_insn_r
->aarch64_insn
, 25);
3952 ins_bit26
= bit (aarch64_insn_r
->aarch64_insn
, 26);
3953 ins_bit27
= bit (aarch64_insn_r
->aarch64_insn
, 27);
3954 ins_bit28
= bit (aarch64_insn_r
->aarch64_insn
, 28);
3956 /* Data processing - immediate instructions. */
3957 if (!ins_bit26
&& !ins_bit27
&& ins_bit28
)
3958 return aarch64_record_data_proc_imm (aarch64_insn_r
);
3960 /* Branch, exception generation and system instructions. */
3961 if (ins_bit26
&& !ins_bit27
&& ins_bit28
)
3962 return aarch64_record_branch_except_sys (aarch64_insn_r
);
3964 /* Load and store instructions. */
3965 if (!ins_bit25
&& ins_bit27
)
3966 return aarch64_record_load_store (aarch64_insn_r
);
3968 /* Data processing - register instructions. */
3969 if (ins_bit25
&& !ins_bit26
&& ins_bit27
)
3970 return aarch64_record_data_proc_reg (aarch64_insn_r
);
3972 /* Data processing - SIMD and floating point instructions. */
3973 if (ins_bit25
&& ins_bit26
&& ins_bit27
)
3974 return aarch64_record_data_proc_simd_fp (aarch64_insn_r
);
3976 return AARCH64_RECORD_UNSUPPORTED
;
3979 /* Cleans up local record registers and memory allocations. */
3982 deallocate_reg_mem (insn_decode_record
*record
)
3984 xfree (record
->aarch64_regs
);
3985 xfree (record
->aarch64_mems
);
3989 namespace selftests
{
3992 aarch64_process_record_test (void)
3994 struct gdbarch_info info
;
3997 gdbarch_info_init (&info
);
3998 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
4000 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
4001 SELF_CHECK (gdbarch
!= NULL
);
4003 insn_decode_record aarch64_record
;
4005 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4006 aarch64_record
.regcache
= NULL
;
4007 aarch64_record
.this_addr
= 0;
4008 aarch64_record
.gdbarch
= gdbarch
;
4010 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4011 aarch64_record
.aarch64_insn
= 0xf9800020;
4012 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4013 SELF_CHECK (ret
== AARCH64_RECORD_SUCCESS
);
4014 SELF_CHECK (aarch64_record
.reg_rec_count
== 0);
4015 SELF_CHECK (aarch64_record
.mem_rec_count
== 0);
4017 deallocate_reg_mem (&aarch64_record
);
4020 } // namespace selftests
4021 #endif /* GDB_SELF_TEST */
4023 /* Parse the current instruction and record the values of the registers and
4024 memory that will be changed in current instruction to record_arch_list
4025 return -1 if something is wrong. */
4028 aarch64_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4029 CORE_ADDR insn_addr
)
4031 uint32_t rec_no
= 0;
4032 uint8_t insn_size
= 4;
4034 gdb_byte buf
[insn_size
];
4035 insn_decode_record aarch64_record
;
4037 memset (&buf
[0], 0, insn_size
);
4038 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4039 target_read_memory (insn_addr
, &buf
[0], insn_size
);
4040 aarch64_record
.aarch64_insn
4041 = (uint32_t) extract_unsigned_integer (&buf
[0],
4043 gdbarch_byte_order (gdbarch
));
4044 aarch64_record
.regcache
= regcache
;
4045 aarch64_record
.this_addr
= insn_addr
;
4046 aarch64_record
.gdbarch
= gdbarch
;
4048 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4049 if (ret
== AARCH64_RECORD_UNSUPPORTED
)
4051 printf_unfiltered (_("Process record does not support instruction "
4052 "0x%0x at address %s.\n"),
4053 aarch64_record
.aarch64_insn
,
4054 paddress (gdbarch
, insn_addr
));
4060 /* Record registers. */
4061 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4063 /* Always record register CPSR. */
4064 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4065 AARCH64_CPSR_REGNUM
);
4066 if (aarch64_record
.aarch64_regs
)
4067 for (rec_no
= 0; rec_no
< aarch64_record
.reg_rec_count
; rec_no
++)
4068 if (record_full_arch_list_add_reg (aarch64_record
.regcache
,
4069 aarch64_record
.aarch64_regs
[rec_no
]))
4072 /* Record memories. */
4073 if (aarch64_record
.aarch64_mems
)
4074 for (rec_no
= 0; rec_no
< aarch64_record
.mem_rec_count
; rec_no
++)
4075 if (record_full_arch_list_add_mem
4076 ((CORE_ADDR
)aarch64_record
.aarch64_mems
[rec_no
].addr
,
4077 aarch64_record
.aarch64_mems
[rec_no
].len
))
4080 if (record_full_arch_list_add_end ())
4084 deallocate_reg_mem (&aarch64_record
);