1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2019 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "reggroups.h"
31 #include "arch-utils.h"
33 #include "frame-unwind.h"
34 #include "frame-base.h"
35 #include "trad-frame.h"
38 #include "dwarf2-frame.h"
40 #include "prologue-value.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
47 #include "common/selftest.h"
49 #include "aarch64-tdep.h"
50 #include "aarch64-ravenscar-thread.h"
53 #include "elf/aarch64.h"
55 #include "common/vec.h"
58 #include "record-full.h"
59 #include "arch/aarch64-insn.h"
61 #include "opcode/aarch64.h"
64 #define submask(x) ((1L << ((x) + 1)) - 1)
65 #define bit(obj,st) (((obj) >> (st)) & 1)
66 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
68 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
70 #define HA_MAX_NUM_FLDS 4
72 /* All possible aarch64 target descriptors. */
73 struct target_desc
*tdesc_aarch64_list
[AARCH64_MAX_SVE_VQ
+ 1][2/*pauth*/];
75 /* The standard register names, and all the valid aliases for them. */
78 const char *const name
;
80 } aarch64_register_aliases
[] =
82 /* 64-bit register names. */
83 {"fp", AARCH64_FP_REGNUM
},
84 {"lr", AARCH64_LR_REGNUM
},
85 {"sp", AARCH64_SP_REGNUM
},
87 /* 32-bit register names. */
88 {"w0", AARCH64_X0_REGNUM
+ 0},
89 {"w1", AARCH64_X0_REGNUM
+ 1},
90 {"w2", AARCH64_X0_REGNUM
+ 2},
91 {"w3", AARCH64_X0_REGNUM
+ 3},
92 {"w4", AARCH64_X0_REGNUM
+ 4},
93 {"w5", AARCH64_X0_REGNUM
+ 5},
94 {"w6", AARCH64_X0_REGNUM
+ 6},
95 {"w7", AARCH64_X0_REGNUM
+ 7},
96 {"w8", AARCH64_X0_REGNUM
+ 8},
97 {"w9", AARCH64_X0_REGNUM
+ 9},
98 {"w10", AARCH64_X0_REGNUM
+ 10},
99 {"w11", AARCH64_X0_REGNUM
+ 11},
100 {"w12", AARCH64_X0_REGNUM
+ 12},
101 {"w13", AARCH64_X0_REGNUM
+ 13},
102 {"w14", AARCH64_X0_REGNUM
+ 14},
103 {"w15", AARCH64_X0_REGNUM
+ 15},
104 {"w16", AARCH64_X0_REGNUM
+ 16},
105 {"w17", AARCH64_X0_REGNUM
+ 17},
106 {"w18", AARCH64_X0_REGNUM
+ 18},
107 {"w19", AARCH64_X0_REGNUM
+ 19},
108 {"w20", AARCH64_X0_REGNUM
+ 20},
109 {"w21", AARCH64_X0_REGNUM
+ 21},
110 {"w22", AARCH64_X0_REGNUM
+ 22},
111 {"w23", AARCH64_X0_REGNUM
+ 23},
112 {"w24", AARCH64_X0_REGNUM
+ 24},
113 {"w25", AARCH64_X0_REGNUM
+ 25},
114 {"w26", AARCH64_X0_REGNUM
+ 26},
115 {"w27", AARCH64_X0_REGNUM
+ 27},
116 {"w28", AARCH64_X0_REGNUM
+ 28},
117 {"w29", AARCH64_X0_REGNUM
+ 29},
118 {"w30", AARCH64_X0_REGNUM
+ 30},
121 {"ip0", AARCH64_X0_REGNUM
+ 16},
122 {"ip1", AARCH64_X0_REGNUM
+ 17}
125 /* The required core 'R' registers. */
126 static const char *const aarch64_r_register_names
[] =
128 /* These registers must appear in consecutive RAW register number
129 order and they must begin with AARCH64_X0_REGNUM! */
130 "x0", "x1", "x2", "x3",
131 "x4", "x5", "x6", "x7",
132 "x8", "x9", "x10", "x11",
133 "x12", "x13", "x14", "x15",
134 "x16", "x17", "x18", "x19",
135 "x20", "x21", "x22", "x23",
136 "x24", "x25", "x26", "x27",
137 "x28", "x29", "x30", "sp",
141 /* The FP/SIMD 'V' registers. */
142 static const char *const aarch64_v_register_names
[] =
144 /* These registers must appear in consecutive RAW register number
145 order and they must begin with AARCH64_V0_REGNUM! */
146 "v0", "v1", "v2", "v3",
147 "v4", "v5", "v6", "v7",
148 "v8", "v9", "v10", "v11",
149 "v12", "v13", "v14", "v15",
150 "v16", "v17", "v18", "v19",
151 "v20", "v21", "v22", "v23",
152 "v24", "v25", "v26", "v27",
153 "v28", "v29", "v30", "v31",
158 /* The SVE 'Z' and 'P' registers. */
159 static const char *const aarch64_sve_register_names
[] =
161 /* These registers must appear in consecutive RAW register number
162 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
163 "z0", "z1", "z2", "z3",
164 "z4", "z5", "z6", "z7",
165 "z8", "z9", "z10", "z11",
166 "z12", "z13", "z14", "z15",
167 "z16", "z17", "z18", "z19",
168 "z20", "z21", "z22", "z23",
169 "z24", "z25", "z26", "z27",
170 "z28", "z29", "z30", "z31",
172 "p0", "p1", "p2", "p3",
173 "p4", "p5", "p6", "p7",
174 "p8", "p9", "p10", "p11",
175 "p12", "p13", "p14", "p15",
179 static const char *const aarch64_pauth_register_names
[] =
181 /* Authentication mask for data pointer. */
183 /* Authentication mask for code pointer. */
187 /* AArch64 prologue cache structure. */
188 struct aarch64_prologue_cache
190 /* The program counter at the start of the function. It is used to
191 identify this frame as a prologue frame. */
194 /* The program counter at the time this frame was created; i.e. where
195 this function was called from. It is used to identify this frame as a
199 /* The stack pointer at the time this frame was created; i.e. the
200 caller's stack pointer when this function was called. It is used
201 to identify this frame. */
204 /* Is the target available to read from? */
207 /* The frame base for this frame is just prev_sp - frame size.
208 FRAMESIZE is the distance from the frame pointer to the
209 initial stack pointer. */
212 /* The register used to hold the frame pointer for this frame. */
215 /* Saved register offsets. */
216 struct trad_frame_saved_reg
*saved_regs
;
220 show_aarch64_debug (struct ui_file
*file
, int from_tty
,
221 struct cmd_list_element
*c
, const char *value
)
223 fprintf_filtered (file
, _("AArch64 debugging is %s.\n"), value
);
228 /* Abstract instruction reader. */
230 class abstract_instruction_reader
233 /* Read in one instruction. */
234 virtual ULONGEST
read (CORE_ADDR memaddr
, int len
,
235 enum bfd_endian byte_order
) = 0;
238 /* Instruction reader from real target. */
240 class instruction_reader
: public abstract_instruction_reader
243 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
246 return read_code_unsigned_integer (memaddr
, len
, byte_order
);
252 /* If address signing is enabled, mask off the signature bits from ADDR, using
253 the register values in THIS_FRAME. */
256 aarch64_frame_unmask_address (struct gdbarch_tdep
*tdep
,
257 struct frame_info
*this_frame
,
260 if (tdep
->has_pauth ()
261 && frame_unwind_register_unsigned (this_frame
,
262 tdep
->pauth_ra_state_regnum
))
264 int cmask_num
= AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
);
265 CORE_ADDR cmask
= frame_unwind_register_unsigned (this_frame
, cmask_num
);
266 addr
= addr
& ~cmask
;
272 /* Analyze a prologue, looking for a recognizable stack frame
273 and frame pointer. Scan until we encounter a store that could
274 clobber the stack frame unexpectedly, or an unknown instruction. */
277 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
278 CORE_ADDR start
, CORE_ADDR limit
,
279 struct aarch64_prologue_cache
*cache
,
280 abstract_instruction_reader
& reader
)
282 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
284 /* Track X registers and D registers in prologue. */
285 pv_t regs
[AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
];
287 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
; i
++)
288 regs
[i
] = pv_register (i
, 0);
289 pv_area
stack (AARCH64_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
291 for (; start
< limit
; start
+= 4)
296 insn
= reader
.read (start
, 4, byte_order_for_code
);
298 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
301 if (inst
.opcode
->iclass
== addsub_imm
302 && (inst
.opcode
->op
== OP_ADD
303 || strcmp ("sub", inst
.opcode
->name
) == 0))
305 unsigned rd
= inst
.operands
[0].reg
.regno
;
306 unsigned rn
= inst
.operands
[1].reg
.regno
;
308 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 3);
309 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd_SP
);
310 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn_SP
);
311 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_AIMM
);
313 if (inst
.opcode
->op
== OP_ADD
)
315 regs
[rd
] = pv_add_constant (regs
[rn
],
316 inst
.operands
[2].imm
.value
);
320 regs
[rd
] = pv_add_constant (regs
[rn
],
321 -inst
.operands
[2].imm
.value
);
324 else if (inst
.opcode
->iclass
== pcreladdr
325 && inst
.operands
[1].type
== AARCH64_OPND_ADDR_ADRP
)
327 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
328 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
330 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
332 else if (inst
.opcode
->iclass
== branch_imm
)
334 /* Stop analysis on branch. */
337 else if (inst
.opcode
->iclass
== condbranch
)
339 /* Stop analysis on branch. */
342 else if (inst
.opcode
->iclass
== branch_reg
)
344 /* Stop analysis on branch. */
347 else if (inst
.opcode
->iclass
== compbranch
)
349 /* Stop analysis on branch. */
352 else if (inst
.opcode
->op
== OP_MOVZ
)
354 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
355 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
357 else if (inst
.opcode
->iclass
== log_shift
358 && strcmp (inst
.opcode
->name
, "orr") == 0)
360 unsigned rd
= inst
.operands
[0].reg
.regno
;
361 unsigned rn
= inst
.operands
[1].reg
.regno
;
362 unsigned rm
= inst
.operands
[2].reg
.regno
;
364 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
365 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn
);
366 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_Rm_SFT
);
368 if (inst
.operands
[2].shifter
.amount
== 0
369 && rn
== AARCH64_SP_REGNUM
)
375 debug_printf ("aarch64: prologue analysis gave up "
376 "addr=%s opcode=0x%x (orr x register)\n",
377 core_addr_to_string_nz (start
), insn
);
382 else if (inst
.opcode
->op
== OP_STUR
)
384 unsigned rt
= inst
.operands
[0].reg
.regno
;
385 unsigned rn
= inst
.operands
[1].addr
.base_regno
;
387 = (aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
) == 8);
389 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
390 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
);
391 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_ADDR_SIMM9
);
392 gdb_assert (!inst
.operands
[1].addr
.offset
.is_reg
);
394 stack
.store (pv_add_constant (regs
[rn
],
395 inst
.operands
[1].addr
.offset
.imm
),
396 is64
? 8 : 4, regs
[rt
]);
398 else if ((inst
.opcode
->iclass
== ldstpair_off
399 || (inst
.opcode
->iclass
== ldstpair_indexed
400 && inst
.operands
[2].addr
.preind
))
401 && strcmp ("stp", inst
.opcode
->name
) == 0)
403 /* STP with addressing mode Pre-indexed and Base register. */
406 unsigned rn
= inst
.operands
[2].addr
.base_regno
;
407 int32_t imm
= inst
.operands
[2].addr
.offset
.imm
;
409 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
410 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
411 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rt2
412 || inst
.operands
[1].type
== AARCH64_OPND_Ft2
);
413 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_ADDR_SIMM7
);
414 gdb_assert (!inst
.operands
[2].addr
.offset
.is_reg
);
416 /* If recording this store would invalidate the store area
417 (perhaps because rn is not known) then we should abandon
418 further prologue analysis. */
419 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
)))
422 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
+ 8)))
425 rt1
= inst
.operands
[0].reg
.regno
;
426 rt2
= inst
.operands
[1].reg
.regno
;
427 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
429 /* Only bottom 64-bit of each V register (D register) need
431 gdb_assert (inst
.operands
[0].qualifier
== AARCH64_OPND_QLF_S_D
);
432 rt1
+= AARCH64_X_REGISTER_COUNT
;
433 rt2
+= AARCH64_X_REGISTER_COUNT
;
436 stack
.store (pv_add_constant (regs
[rn
], imm
), 8,
438 stack
.store (pv_add_constant (regs
[rn
], imm
+ 8), 8,
441 if (inst
.operands
[2].addr
.writeback
)
442 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
445 else if ((inst
.opcode
->iclass
== ldst_imm9
/* Signed immediate. */
446 || (inst
.opcode
->iclass
== ldst_pos
/* Unsigned immediate. */
447 && (inst
.opcode
->op
== OP_STR_POS
448 || inst
.opcode
->op
== OP_STRF_POS
)))
449 && inst
.operands
[1].addr
.base_regno
== AARCH64_SP_REGNUM
450 && strcmp ("str", inst
.opcode
->name
) == 0)
452 /* STR (immediate) */
453 unsigned int rt
= inst
.operands
[0].reg
.regno
;
454 int32_t imm
= inst
.operands
[1].addr
.offset
.imm
;
455 unsigned int rn
= inst
.operands
[1].addr
.base_regno
;
457 = (aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
) == 8);
458 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
459 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
461 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
463 /* Only bottom 64-bit of each V register (D register) need
465 gdb_assert (inst
.operands
[0].qualifier
== AARCH64_OPND_QLF_S_D
);
466 rt
+= AARCH64_X_REGISTER_COUNT
;
469 stack
.store (pv_add_constant (regs
[rn
], imm
),
470 is64
? 8 : 4, regs
[rt
]);
471 if (inst
.operands
[1].addr
.writeback
)
472 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
474 else if (inst
.opcode
->iclass
== testbranch
)
476 /* Stop analysis on branch. */
479 else if (inst
.opcode
->iclass
== ic_system
)
481 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
482 int ra_state_val
= 0;
484 if (insn
== 0xd503233f /* paciasp. */
485 || insn
== 0xd503237f /* pacibsp. */)
487 /* Return addresses are mangled. */
490 else if (insn
== 0xd50323bf /* autiasp. */
491 || insn
== 0xd50323ff /* autibsp. */)
493 /* Return addresses are not mangled. */
499 debug_printf ("aarch64: prologue analysis gave up addr=%s"
500 " opcode=0x%x (iclass)\n",
501 core_addr_to_string_nz (start
), insn
);
505 if (tdep
->has_pauth () && cache
!= nullptr)
506 trad_frame_set_value (cache
->saved_regs
,
507 tdep
->pauth_ra_state_regnum
,
514 debug_printf ("aarch64: prologue analysis gave up addr=%s"
516 core_addr_to_string_nz (start
), insn
);
525 if (pv_is_register (regs
[AARCH64_FP_REGNUM
], AARCH64_SP_REGNUM
))
527 /* Frame pointer is fp. Frame size is constant. */
528 cache
->framereg
= AARCH64_FP_REGNUM
;
529 cache
->framesize
= -regs
[AARCH64_FP_REGNUM
].k
;
531 else if (pv_is_register (regs
[AARCH64_SP_REGNUM
], AARCH64_SP_REGNUM
))
533 /* Try the stack pointer. */
534 cache
->framesize
= -regs
[AARCH64_SP_REGNUM
].k
;
535 cache
->framereg
= AARCH64_SP_REGNUM
;
539 /* We're just out of luck. We don't know where the frame is. */
540 cache
->framereg
= -1;
541 cache
->framesize
= 0;
544 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
548 if (stack
.find_reg (gdbarch
, i
, &offset
))
549 cache
->saved_regs
[i
].addr
= offset
;
552 for (i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
554 int regnum
= gdbarch_num_regs (gdbarch
);
557 if (stack
.find_reg (gdbarch
, i
+ AARCH64_X_REGISTER_COUNT
,
559 cache
->saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
= offset
;
566 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
567 CORE_ADDR start
, CORE_ADDR limit
,
568 struct aarch64_prologue_cache
*cache
)
570 instruction_reader reader
;
572 return aarch64_analyze_prologue (gdbarch
, start
, limit
, cache
,
578 namespace selftests
{
580 /* Instruction reader from manually cooked instruction sequences. */
582 class instruction_reader_test
: public abstract_instruction_reader
585 template<size_t SIZE
>
586 explicit instruction_reader_test (const uint32_t (&insns
)[SIZE
])
587 : m_insns (insns
), m_insns_size (SIZE
)
590 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
593 SELF_CHECK (len
== 4);
594 SELF_CHECK (memaddr
% 4 == 0);
595 SELF_CHECK (memaddr
/ 4 < m_insns_size
);
597 return m_insns
[memaddr
/ 4];
601 const uint32_t *m_insns
;
606 aarch64_analyze_prologue_test (void)
608 struct gdbarch_info info
;
610 gdbarch_info_init (&info
);
611 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
613 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
614 SELF_CHECK (gdbarch
!= NULL
);
616 struct aarch64_prologue_cache cache
;
617 cache
.saved_regs
= trad_frame_alloc_saved_regs (gdbarch
);
619 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
621 /* Test the simple prologue in which frame pointer is used. */
623 static const uint32_t insns
[] = {
624 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
625 0x910003fd, /* mov x29, sp */
626 0x97ffffe6, /* bl 0x400580 */
628 instruction_reader_test
reader (insns
);
630 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
631 SELF_CHECK (end
== 4 * 2);
633 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
634 SELF_CHECK (cache
.framesize
== 272);
636 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
638 if (i
== AARCH64_FP_REGNUM
)
639 SELF_CHECK (cache
.saved_regs
[i
].addr
== -272);
640 else if (i
== AARCH64_LR_REGNUM
)
641 SELF_CHECK (cache
.saved_regs
[i
].addr
== -264);
643 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
646 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
648 int regnum
= gdbarch_num_regs (gdbarch
);
650 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
655 /* Test a prologue in which STR is used and frame pointer is not
658 static const uint32_t insns
[] = {
659 0xf81d0ff3, /* str x19, [sp, #-48]! */
660 0xb9002fe0, /* str w0, [sp, #44] */
661 0xf90013e1, /* str x1, [sp, #32]*/
662 0xfd000fe0, /* str d0, [sp, #24] */
663 0xaa0203f3, /* mov x19, x2 */
664 0xf94013e0, /* ldr x0, [sp, #32] */
666 instruction_reader_test
reader (insns
);
668 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
669 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
671 SELF_CHECK (end
== 4 * 5);
673 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
674 SELF_CHECK (cache
.framesize
== 48);
676 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
679 SELF_CHECK (cache
.saved_regs
[i
].addr
== -16);
681 SELF_CHECK (cache
.saved_regs
[i
].addr
== -48);
683 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
686 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
688 int regnum
= gdbarch_num_regs (gdbarch
);
691 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
694 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
699 /* Test a prologue in which there is a return address signing instruction. */
700 if (tdep
->has_pauth ())
702 static const uint32_t insns
[] = {
703 0xd503233f, /* paciasp */
704 0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */
705 0x910003fd, /* mov x29, sp */
706 0xf801c3f3, /* str x19, [sp, #28] */
707 0xb9401fa0, /* ldr x19, [x29, #28] */
709 instruction_reader_test
reader (insns
);
711 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
712 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
,
715 SELF_CHECK (end
== 4 * 4);
716 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
717 SELF_CHECK (cache
.framesize
== 48);
719 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
722 SELF_CHECK (cache
.saved_regs
[i
].addr
== -20);
723 else if (i
== AARCH64_FP_REGNUM
)
724 SELF_CHECK (cache
.saved_regs
[i
].addr
== -48);
725 else if (i
== AARCH64_LR_REGNUM
)
726 SELF_CHECK (cache
.saved_regs
[i
].addr
== -40);
728 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
731 if (tdep
->has_pauth ())
733 SELF_CHECK (trad_frame_value_p (cache
.saved_regs
,
734 tdep
->pauth_ra_state_regnum
));
735 SELF_CHECK (cache
.saved_regs
[tdep
->pauth_ra_state_regnum
].addr
== 1);
739 } // namespace selftests
740 #endif /* GDB_SELF_TEST */
742 /* Implement the "skip_prologue" gdbarch method. */
745 aarch64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
747 CORE_ADDR func_addr
, limit_pc
;
749 /* See if we can determine the end of the prologue via the symbol
750 table. If so, then return either PC, or the PC after the
751 prologue, whichever is greater. */
752 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
754 CORE_ADDR post_prologue_pc
755 = skip_prologue_using_sal (gdbarch
, func_addr
);
757 if (post_prologue_pc
!= 0)
758 return std::max (pc
, post_prologue_pc
);
761 /* Can't determine prologue from the symbol table, need to examine
764 /* Find an upper limit on the function prologue using the debug
765 information. If the debug information could not be used to
766 provide that bound, then use an arbitrary large number as the
768 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
770 limit_pc
= pc
+ 128; /* Magic. */
772 /* Try disassembling prologue. */
773 return aarch64_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
776 /* Scan the function prologue for THIS_FRAME and populate the prologue
780 aarch64_scan_prologue (struct frame_info
*this_frame
,
781 struct aarch64_prologue_cache
*cache
)
783 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
784 CORE_ADDR prologue_start
;
785 CORE_ADDR prologue_end
;
786 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
787 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
789 cache
->prev_pc
= prev_pc
;
791 /* Assume we do not find a frame. */
792 cache
->framereg
= -1;
793 cache
->framesize
= 0;
795 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
798 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
802 /* No line info so use the current PC. */
803 prologue_end
= prev_pc
;
805 else if (sal
.end
< prologue_end
)
807 /* The next line begins after the function end. */
808 prologue_end
= sal
.end
;
811 prologue_end
= std::min (prologue_end
, prev_pc
);
812 aarch64_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
818 frame_loc
= get_frame_register_unsigned (this_frame
, AARCH64_FP_REGNUM
);
822 cache
->framereg
= AARCH64_FP_REGNUM
;
823 cache
->framesize
= 16;
824 cache
->saved_regs
[29].addr
= 0;
825 cache
->saved_regs
[30].addr
= 8;
829 /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
830 function may throw an exception if the inferior's registers or memory is
834 aarch64_make_prologue_cache_1 (struct frame_info
*this_frame
,
835 struct aarch64_prologue_cache
*cache
)
837 CORE_ADDR unwound_fp
;
840 aarch64_scan_prologue (this_frame
, cache
);
842 if (cache
->framereg
== -1)
845 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
849 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
851 /* Calculate actual addresses of saved registers using offsets
852 determined by aarch64_analyze_prologue. */
853 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
854 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
855 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
857 cache
->func
= get_frame_func (this_frame
);
859 cache
->available_p
= 1;
862 /* Allocate and fill in *THIS_CACHE with information about the prologue of
863 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
864 Return a pointer to the current aarch64_prologue_cache in
867 static struct aarch64_prologue_cache
*
868 aarch64_make_prologue_cache (struct frame_info
*this_frame
, void **this_cache
)
870 struct aarch64_prologue_cache
*cache
;
872 if (*this_cache
!= NULL
)
873 return (struct aarch64_prologue_cache
*) *this_cache
;
875 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
876 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
881 aarch64_make_prologue_cache_1 (this_frame
, cache
);
883 catch (const gdb_exception_error
&ex
)
885 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
892 /* Implement the "stop_reason" frame_unwind method. */
894 static enum unwind_stop_reason
895 aarch64_prologue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
898 struct aarch64_prologue_cache
*cache
899 = aarch64_make_prologue_cache (this_frame
, this_cache
);
901 if (!cache
->available_p
)
902 return UNWIND_UNAVAILABLE
;
904 /* Halt the backtrace at "_start". */
905 if (cache
->prev_pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
906 return UNWIND_OUTERMOST
;
908 /* We've hit a wall, stop. */
909 if (cache
->prev_sp
== 0)
910 return UNWIND_OUTERMOST
;
912 return UNWIND_NO_REASON
;
915 /* Our frame ID for a normal frame is the current function's starting
916 PC and the caller's SP when we were called. */
919 aarch64_prologue_this_id (struct frame_info
*this_frame
,
920 void **this_cache
, struct frame_id
*this_id
)
922 struct aarch64_prologue_cache
*cache
923 = aarch64_make_prologue_cache (this_frame
, this_cache
);
925 if (!cache
->available_p
)
926 *this_id
= frame_id_build_unavailable_stack (cache
->func
);
928 *this_id
= frame_id_build (cache
->prev_sp
, cache
->func
);
931 /* Implement the "prev_register" frame_unwind method. */
933 static struct value
*
934 aarch64_prologue_prev_register (struct frame_info
*this_frame
,
935 void **this_cache
, int prev_regnum
)
937 struct aarch64_prologue_cache
*cache
938 = aarch64_make_prologue_cache (this_frame
, this_cache
);
940 /* If we are asked to unwind the PC, then we need to return the LR
941 instead. The prologue may save PC, but it will point into this
942 frame's prologue, not the next frame's resume location. */
943 if (prev_regnum
== AARCH64_PC_REGNUM
)
946 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
947 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
949 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
951 if (tdep
->has_pauth ()
952 && trad_frame_value_p (cache
->saved_regs
,
953 tdep
->pauth_ra_state_regnum
))
954 lr
= aarch64_frame_unmask_address (tdep
, this_frame
, lr
);
956 return frame_unwind_got_constant (this_frame
, prev_regnum
, lr
);
959 /* SP is generally not saved to the stack, but this frame is
960 identified by the next frame's stack pointer at the time of the
961 call. The value was already reconstructed into PREV_SP. */
974 if (prev_regnum
== AARCH64_SP_REGNUM
)
975 return frame_unwind_got_constant (this_frame
, prev_regnum
,
978 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
982 /* AArch64 prologue unwinder. */
983 struct frame_unwind aarch64_prologue_unwind
=
986 aarch64_prologue_frame_unwind_stop_reason
,
987 aarch64_prologue_this_id
,
988 aarch64_prologue_prev_register
,
990 default_frame_sniffer
993 /* Allocate and fill in *THIS_CACHE with information about the prologue of
994 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
995 Return a pointer to the current aarch64_prologue_cache in
998 static struct aarch64_prologue_cache
*
999 aarch64_make_stub_cache (struct frame_info
*this_frame
, void **this_cache
)
1001 struct aarch64_prologue_cache
*cache
;
1003 if (*this_cache
!= NULL
)
1004 return (struct aarch64_prologue_cache
*) *this_cache
;
1006 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
1007 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1008 *this_cache
= cache
;
1012 cache
->prev_sp
= get_frame_register_unsigned (this_frame
,
1014 cache
->prev_pc
= get_frame_pc (this_frame
);
1015 cache
->available_p
= 1;
1017 catch (const gdb_exception_error
&ex
)
1019 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
1026 /* Implement the "stop_reason" frame_unwind method. */
1028 static enum unwind_stop_reason
1029 aarch64_stub_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1032 struct aarch64_prologue_cache
*cache
1033 = aarch64_make_stub_cache (this_frame
, this_cache
);
1035 if (!cache
->available_p
)
1036 return UNWIND_UNAVAILABLE
;
1038 return UNWIND_NO_REASON
;
1041 /* Our frame ID for a stub frame is the current SP and LR. */
1044 aarch64_stub_this_id (struct frame_info
*this_frame
,
1045 void **this_cache
, struct frame_id
*this_id
)
1047 struct aarch64_prologue_cache
*cache
1048 = aarch64_make_stub_cache (this_frame
, this_cache
);
1050 if (cache
->available_p
)
1051 *this_id
= frame_id_build (cache
->prev_sp
, cache
->prev_pc
);
1053 *this_id
= frame_id_build_unavailable_stack (cache
->prev_pc
);
1056 /* Implement the "sniffer" frame_unwind method. */
1059 aarch64_stub_unwind_sniffer (const struct frame_unwind
*self
,
1060 struct frame_info
*this_frame
,
1061 void **this_prologue_cache
)
1063 CORE_ADDR addr_in_block
;
1066 addr_in_block
= get_frame_address_in_block (this_frame
);
1067 if (in_plt_section (addr_in_block
)
1068 /* We also use the stub winder if the target memory is unreadable
1069 to avoid having the prologue unwinder trying to read it. */
1070 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1076 /* AArch64 stub unwinder. */
1077 struct frame_unwind aarch64_stub_unwind
=
1080 aarch64_stub_frame_unwind_stop_reason
,
1081 aarch64_stub_this_id
,
1082 aarch64_prologue_prev_register
,
1084 aarch64_stub_unwind_sniffer
1087 /* Return the frame base address of *THIS_FRAME. */
1090 aarch64_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1092 struct aarch64_prologue_cache
*cache
1093 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1095 return cache
->prev_sp
- cache
->framesize
;
1098 /* AArch64 default frame base information. */
1099 struct frame_base aarch64_normal_base
=
1101 &aarch64_prologue_unwind
,
1102 aarch64_normal_frame_base
,
1103 aarch64_normal_frame_base
,
1104 aarch64_normal_frame_base
1107 /* Return the value of the REGNUM register in the previous frame of
1110 static struct value
*
1111 aarch64_dwarf2_prev_register (struct frame_info
*this_frame
,
1112 void **this_cache
, int regnum
)
1114 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1119 case AARCH64_PC_REGNUM
:
1120 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
1121 lr
= aarch64_frame_unmask_address (tdep
, this_frame
, lr
);
1122 return frame_unwind_got_constant (this_frame
, regnum
, lr
);
1125 internal_error (__FILE__
, __LINE__
,
1126 _("Unexpected register %d"), regnum
);
1130 static const unsigned char op_lit0
= DW_OP_lit0
;
1131 static const unsigned char op_lit1
= DW_OP_lit1
;
1133 /* Implement the "init_reg" dwarf2_frame_ops method. */
1136 aarch64_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1137 struct dwarf2_frame_state_reg
*reg
,
1138 struct frame_info
*this_frame
)
1140 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1144 case AARCH64_PC_REGNUM
:
1145 reg
->how
= DWARF2_FRAME_REG_FN
;
1146 reg
->loc
.fn
= aarch64_dwarf2_prev_register
;
1149 case AARCH64_SP_REGNUM
:
1150 reg
->how
= DWARF2_FRAME_REG_CFA
;
1154 /* Init pauth registers. */
1155 if (tdep
->has_pauth ())
1157 if (regnum
== tdep
->pauth_ra_state_regnum
)
1159 /* Initialize RA_STATE to zero. */
1160 reg
->how
= DWARF2_FRAME_REG_SAVED_VAL_EXP
;
1161 reg
->loc
.exp
.start
= &op_lit0
;
1162 reg
->loc
.exp
.len
= 1;
1165 else if (regnum
== AARCH64_PAUTH_DMASK_REGNUM (tdep
->pauth_reg_base
)
1166 || regnum
== AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
))
1168 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1174 /* Implement the execute_dwarf_cfa_vendor_op method. */
1177 aarch64_execute_dwarf_cfa_vendor_op (struct gdbarch
*gdbarch
, gdb_byte op
,
1178 struct dwarf2_frame_state
*fs
)
1180 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1181 struct dwarf2_frame_state_reg
*ra_state
;
1183 if (tdep
->has_pauth () && op
== DW_CFA_AARCH64_negate_ra_state
)
1185 /* Allocate RA_STATE column if it's not allocated yet. */
1186 fs
->regs
.alloc_regs (AARCH64_DWARF_PAUTH_RA_STATE
+ 1);
1188 /* Toggle the status of RA_STATE between 0 and 1. */
1189 ra_state
= &(fs
->regs
.reg
[AARCH64_DWARF_PAUTH_RA_STATE
]);
1190 ra_state
->how
= DWARF2_FRAME_REG_SAVED_VAL_EXP
;
1192 if (ra_state
->loc
.exp
.start
== nullptr
1193 || ra_state
->loc
.exp
.start
== &op_lit0
)
1194 ra_state
->loc
.exp
.start
= &op_lit1
;
1196 ra_state
->loc
.exp
.start
= &op_lit0
;
1198 ra_state
->loc
.exp
.len
= 1;
1206 /* When arguments must be pushed onto the stack, they go on in reverse
1207 order. The code below implements a FILO (stack) to do this. */
1211 /* Value to pass on stack. It can be NULL if this item is for stack
1213 const gdb_byte
*data
;
1215 /* Size in bytes of value to pass on stack. */
1219 DEF_VEC_O (stack_item_t
);
1221 /* Return the alignment (in bytes) of the given type. */
1224 aarch64_type_align (struct type
*t
)
1230 t
= check_typedef (t
);
1231 switch (TYPE_CODE (t
))
1234 /* Should never happen. */
1235 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1239 case TYPE_CODE_ENUM
:
1243 case TYPE_CODE_RANGE
:
1244 case TYPE_CODE_BITSTRING
:
1246 case TYPE_CODE_RVALUE_REF
:
1247 case TYPE_CODE_CHAR
:
1248 case TYPE_CODE_BOOL
:
1249 return TYPE_LENGTH (t
);
1251 case TYPE_CODE_ARRAY
:
1252 if (TYPE_VECTOR (t
))
1254 /* Use the natural alignment for vector types (the same for
1255 scalar type), but the maximum alignment is 128-bit. */
1256 if (TYPE_LENGTH (t
) > 16)
1259 return TYPE_LENGTH (t
);
1262 return aarch64_type_align (TYPE_TARGET_TYPE (t
));
1263 case TYPE_CODE_COMPLEX
:
1264 return aarch64_type_align (TYPE_TARGET_TYPE (t
));
1266 case TYPE_CODE_STRUCT
:
1267 case TYPE_CODE_UNION
:
1269 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1271 falign
= aarch64_type_align (TYPE_FIELD_TYPE (t
, n
));
1279 /* Worker function for aapcs_is_vfp_call_or_return_candidate.
1281 Return the number of register required, or -1 on failure.
1283 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1284 to the element, else fail if the type of this element does not match the
1288 aapcs_is_vfp_call_or_return_candidate_1 (struct type
*type
,
1289 struct type
**fundamental_type
)
1291 if (type
== nullptr)
1294 switch (TYPE_CODE (type
))
1297 if (TYPE_LENGTH (type
) > 16)
1300 if (*fundamental_type
== nullptr)
1301 *fundamental_type
= type
;
1302 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1303 || TYPE_CODE (type
) != TYPE_CODE (*fundamental_type
))
1308 case TYPE_CODE_COMPLEX
:
1310 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (type
));
1311 if (TYPE_LENGTH (target_type
) > 16)
1314 if (*fundamental_type
== nullptr)
1315 *fundamental_type
= target_type
;
1316 else if (TYPE_LENGTH (target_type
) != TYPE_LENGTH (*fundamental_type
)
1317 || TYPE_CODE (target_type
) != TYPE_CODE (*fundamental_type
))
1323 case TYPE_CODE_ARRAY
:
1325 if (TYPE_VECTOR (type
))
1327 if (TYPE_LENGTH (type
) != 8 && TYPE_LENGTH (type
) != 16)
1330 if (*fundamental_type
== nullptr)
1331 *fundamental_type
= type
;
1332 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1333 || TYPE_CODE (type
) != TYPE_CODE (*fundamental_type
))
1340 struct type
*target_type
= TYPE_TARGET_TYPE (type
);
1341 int count
= aapcs_is_vfp_call_or_return_candidate_1
1342 (target_type
, fundamental_type
);
1347 count
*= (TYPE_LENGTH (type
) / TYPE_LENGTH (target_type
));
1352 case TYPE_CODE_STRUCT
:
1353 case TYPE_CODE_UNION
:
1357 for (int i
= 0; i
< TYPE_NFIELDS (type
); i
++)
1359 /* Ignore any static fields. */
1360 if (field_is_static (&TYPE_FIELD (type
, i
)))
1363 struct type
*member
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
1365 int sub_count
= aapcs_is_vfp_call_or_return_candidate_1
1366 (member
, fundamental_type
);
1367 if (sub_count
== -1)
1372 /* Ensure there is no padding between the fields (allowing for empty
1373 zero length structs) */
1374 int ftype_length
= (*fundamental_type
== nullptr)
1375 ? 0 : TYPE_LENGTH (*fundamental_type
);
1376 if (count
* ftype_length
!= TYPE_LENGTH (type
))
1389 /* Return true if an argument, whose type is described by TYPE, can be passed or
1390 returned in simd/fp registers, providing enough parameter passing registers
1391 are available. This is as described in the AAPCS64.
1393 Upon successful return, *COUNT returns the number of needed registers,
1394 *FUNDAMENTAL_TYPE contains the type of those registers.
1396 Candidate as per the AAPCS64 5.4.2.C is either a:
1399 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1400 all the members are floats and has at most 4 members.
1401 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1402 all the members are short vectors and has at most 4 members.
1405 Note that HFAs and HVAs can include nested structures and arrays. */
1408 aapcs_is_vfp_call_or_return_candidate (struct type
*type
, int *count
,
1409 struct type
**fundamental_type
)
1411 if (type
== nullptr)
1414 *fundamental_type
= nullptr;
1416 int ag_count
= aapcs_is_vfp_call_or_return_candidate_1 (type
,
1419 if (ag_count
> 0 && ag_count
<= HA_MAX_NUM_FLDS
)
1428 /* AArch64 function call information structure. */
1429 struct aarch64_call_info
1431 /* the current argument number. */
1434 /* The next general purpose register number, equivalent to NGRN as
1435 described in the AArch64 Procedure Call Standard. */
1438 /* The next SIMD and floating point register number, equivalent to
1439 NSRN as described in the AArch64 Procedure Call Standard. */
1442 /* The next stacked argument address, equivalent to NSAA as
1443 described in the AArch64 Procedure Call Standard. */
1446 /* Stack item vector. */
1447 VEC(stack_item_t
) *si
;
1450 /* Pass a value in a sequence of consecutive X registers. The caller
1451 is responsbile for ensuring sufficient registers are available. */
1454 pass_in_x (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1455 struct aarch64_call_info
*info
, struct type
*type
,
1458 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1459 int len
= TYPE_LENGTH (type
);
1460 enum type_code typecode
= TYPE_CODE (type
);
1461 int regnum
= AARCH64_X0_REGNUM
+ info
->ngrn
;
1462 const bfd_byte
*buf
= value_contents (arg
);
1468 int partial_len
= len
< X_REGISTER_SIZE
? len
: X_REGISTER_SIZE
;
1469 CORE_ADDR regval
= extract_unsigned_integer (buf
, partial_len
,
1473 /* Adjust sub-word struct/union args when big-endian. */
1474 if (byte_order
== BFD_ENDIAN_BIG
1475 && partial_len
< X_REGISTER_SIZE
1476 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1477 regval
<<= ((X_REGISTER_SIZE
- partial_len
) * TARGET_CHAR_BIT
);
1481 debug_printf ("arg %d in %s = 0x%s\n", info
->argnum
,
1482 gdbarch_register_name (gdbarch
, regnum
),
1483 phex (regval
, X_REGISTER_SIZE
));
1485 regcache_cooked_write_unsigned (regcache
, regnum
, regval
);
1492 /* Attempt to marshall a value in a V register. Return 1 if
1493 successful, or 0 if insufficient registers are available. This
1494 function, unlike the equivalent pass_in_x() function does not
1495 handle arguments spread across multiple registers. */
1498 pass_in_v (struct gdbarch
*gdbarch
,
1499 struct regcache
*regcache
,
1500 struct aarch64_call_info
*info
,
1501 int len
, const bfd_byte
*buf
)
1505 int regnum
= AARCH64_V0_REGNUM
+ info
->nsrn
;
1506 /* Enough space for a full vector register. */
1507 gdb_byte reg
[register_size (gdbarch
, regnum
)];
1508 gdb_assert (len
<= sizeof (reg
));
1513 memset (reg
, 0, sizeof (reg
));
1514 /* PCS C.1, the argument is allocated to the least significant
1515 bits of V register. */
1516 memcpy (reg
, buf
, len
);
1517 regcache
->cooked_write (regnum
, reg
);
1521 debug_printf ("arg %d in %s\n", info
->argnum
,
1522 gdbarch_register_name (gdbarch
, regnum
));
1530 /* Marshall an argument onto the stack. */
1533 pass_on_stack (struct aarch64_call_info
*info
, struct type
*type
,
1536 const bfd_byte
*buf
= value_contents (arg
);
1537 int len
= TYPE_LENGTH (type
);
1543 align
= aarch64_type_align (type
);
1545 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1546 Natural alignment of the argument's type. */
1547 align
= align_up (align
, 8);
1549 /* The AArch64 PCS requires at most doubleword alignment. */
1555 debug_printf ("arg %d len=%d @ sp + %d\n", info
->argnum
, len
,
1561 VEC_safe_push (stack_item_t
, info
->si
, &item
);
1564 if (info
->nsaa
& (align
- 1))
1566 /* Push stack alignment padding. */
1567 int pad
= align
- (info
->nsaa
& (align
- 1));
1572 VEC_safe_push (stack_item_t
, info
->si
, &item
);
1577 /* Marshall an argument into a sequence of one or more consecutive X
1578 registers or, if insufficient X registers are available then onto
1582 pass_in_x_or_stack (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1583 struct aarch64_call_info
*info
, struct type
*type
,
1586 int len
= TYPE_LENGTH (type
);
1587 int nregs
= (len
+ X_REGISTER_SIZE
- 1) / X_REGISTER_SIZE
;
1589 /* PCS C.13 - Pass in registers if we have enough spare */
1590 if (info
->ngrn
+ nregs
<= 8)
1592 pass_in_x (gdbarch
, regcache
, info
, type
, arg
);
1593 info
->ngrn
+= nregs
;
1598 pass_on_stack (info
, type
, arg
);
1602 /* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1603 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1604 registers. A return value of false is an error state as the value will have
1605 been partially passed to the stack. */
1607 pass_in_v_vfp_candidate (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1608 struct aarch64_call_info
*info
, struct type
*arg_type
,
1611 switch (TYPE_CODE (arg_type
))
1614 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1615 value_contents (arg
));
1618 case TYPE_CODE_COMPLEX
:
1620 const bfd_byte
*buf
= value_contents (arg
);
1621 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (arg_type
));
1623 if (!pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1627 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1628 buf
+ TYPE_LENGTH (target_type
));
1631 case TYPE_CODE_ARRAY
:
1632 if (TYPE_VECTOR (arg_type
))
1633 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1634 value_contents (arg
));
1637 case TYPE_CODE_STRUCT
:
1638 case TYPE_CODE_UNION
:
1639 for (int i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
1641 /* Don't include static fields. */
1642 if (field_is_static (&TYPE_FIELD (arg_type
, i
)))
1645 struct value
*field
= value_primitive_field (arg
, 0, i
, arg_type
);
1646 struct type
*field_type
= check_typedef (value_type (field
));
1648 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, info
, field_type
,
1659 /* Implement the "push_dummy_call" gdbarch method. */
1662 aarch64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1663 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1665 struct value
**args
, CORE_ADDR sp
,
1666 function_call_return_method return_method
,
1667 CORE_ADDR struct_addr
)
1670 struct aarch64_call_info info
;
1672 memset (&info
, 0, sizeof (info
));
1674 /* We need to know what the type of the called function is in order
1675 to determine the number of named/anonymous arguments for the
1676 actual argument placement, and the return type in order to handle
1677 return value correctly.
1679 The generic code above us views the decision of return in memory
1680 or return in registers as a two stage processes. The language
1681 handler is consulted first and may decide to return in memory (eg
1682 class with copy constructor returned by value), this will cause
1683 the generic code to allocate space AND insert an initial leading
1686 If the language code does not decide to pass in memory then the
1687 target code is consulted.
1689 If the language code decides to pass in memory we want to move
1690 the pointer inserted as the initial argument from the argument
1691 list and into X8, the conventional AArch64 struct return pointer
1694 /* Set the return address. For the AArch64, the return breakpoint
1695 is always at BP_ADDR. */
1696 regcache_cooked_write_unsigned (regcache
, AARCH64_LR_REGNUM
, bp_addr
);
1698 /* If we were given an initial argument for the return slot, lose it. */
1699 if (return_method
== return_method_hidden_param
)
1705 /* The struct_return pointer occupies X8. */
1706 if (return_method
!= return_method_normal
)
1710 debug_printf ("struct return in %s = 0x%s\n",
1711 gdbarch_register_name (gdbarch
,
1712 AARCH64_STRUCT_RETURN_REGNUM
),
1713 paddress (gdbarch
, struct_addr
));
1715 regcache_cooked_write_unsigned (regcache
, AARCH64_STRUCT_RETURN_REGNUM
,
1719 for (argnum
= 0; argnum
< nargs
; argnum
++)
1721 struct value
*arg
= args
[argnum
];
1722 struct type
*arg_type
, *fundamental_type
;
1725 arg_type
= check_typedef (value_type (arg
));
1726 len
= TYPE_LENGTH (arg_type
);
1728 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1729 if there are enough spare registers. */
1730 if (aapcs_is_vfp_call_or_return_candidate (arg_type
, &elements
,
1733 if (info
.nsrn
+ elements
<= 8)
1735 /* We know that we have sufficient registers available therefore
1736 this will never need to fallback to the stack. */
1737 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, &info
, arg_type
,
1739 gdb_assert_not_reached ("Failed to push args");
1744 pass_on_stack (&info
, arg_type
, arg
);
1749 switch (TYPE_CODE (arg_type
))
1752 case TYPE_CODE_BOOL
:
1753 case TYPE_CODE_CHAR
:
1754 case TYPE_CODE_RANGE
:
1755 case TYPE_CODE_ENUM
:
1758 /* Promote to 32 bit integer. */
1759 if (TYPE_UNSIGNED (arg_type
))
1760 arg_type
= builtin_type (gdbarch
)->builtin_uint32
;
1762 arg_type
= builtin_type (gdbarch
)->builtin_int32
;
1763 arg
= value_cast (arg_type
, arg
);
1765 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1768 case TYPE_CODE_STRUCT
:
1769 case TYPE_CODE_ARRAY
:
1770 case TYPE_CODE_UNION
:
1773 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1774 invisible reference. */
1776 /* Allocate aligned storage. */
1777 sp
= align_down (sp
- len
, 16);
1779 /* Write the real data into the stack. */
1780 write_memory (sp
, value_contents (arg
), len
);
1782 /* Construct the indirection. */
1783 arg_type
= lookup_pointer_type (arg_type
);
1784 arg
= value_from_pointer (arg_type
, sp
);
1785 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1788 /* PCS C.15 / C.18 multiple values pass. */
1789 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1793 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1798 /* Make sure stack retains 16 byte alignment. */
1800 sp
-= 16 - (info
.nsaa
& 15);
1802 while (!VEC_empty (stack_item_t
, info
.si
))
1804 stack_item_t
*si
= VEC_last (stack_item_t
, info
.si
);
1807 if (si
->data
!= NULL
)
1808 write_memory (sp
, si
->data
, si
->len
);
1809 VEC_pop (stack_item_t
, info
.si
);
1812 VEC_free (stack_item_t
, info
.si
);
1814 /* Finally, update the SP register. */
1815 regcache_cooked_write_unsigned (regcache
, AARCH64_SP_REGNUM
, sp
);
1820 /* Implement the "frame_align" gdbarch method. */
1823 aarch64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1825 /* Align the stack to sixteen bytes. */
1826 return sp
& ~(CORE_ADDR
) 15;
1829 /* Return the type for an AdvSISD Q register. */
1831 static struct type
*
1832 aarch64_vnq_type (struct gdbarch
*gdbarch
)
1834 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1836 if (tdep
->vnq_type
== NULL
)
1841 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
1844 elem
= builtin_type (gdbarch
)->builtin_uint128
;
1845 append_composite_type_field (t
, "u", elem
);
1847 elem
= builtin_type (gdbarch
)->builtin_int128
;
1848 append_composite_type_field (t
, "s", elem
);
1853 return tdep
->vnq_type
;
1856 /* Return the type for an AdvSISD D register. */
1858 static struct type
*
1859 aarch64_vnd_type (struct gdbarch
*gdbarch
)
1861 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1863 if (tdep
->vnd_type
== NULL
)
1868 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
1871 elem
= builtin_type (gdbarch
)->builtin_double
;
1872 append_composite_type_field (t
, "f", elem
);
1874 elem
= builtin_type (gdbarch
)->builtin_uint64
;
1875 append_composite_type_field (t
, "u", elem
);
1877 elem
= builtin_type (gdbarch
)->builtin_int64
;
1878 append_composite_type_field (t
, "s", elem
);
1883 return tdep
->vnd_type
;
1886 /* Return the type for an AdvSISD S register. */
1888 static struct type
*
1889 aarch64_vns_type (struct gdbarch
*gdbarch
)
1891 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1893 if (tdep
->vns_type
== NULL
)
1898 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
1901 elem
= builtin_type (gdbarch
)->builtin_float
;
1902 append_composite_type_field (t
, "f", elem
);
1904 elem
= builtin_type (gdbarch
)->builtin_uint32
;
1905 append_composite_type_field (t
, "u", elem
);
1907 elem
= builtin_type (gdbarch
)->builtin_int32
;
1908 append_composite_type_field (t
, "s", elem
);
1913 return tdep
->vns_type
;
1916 /* Return the type for an AdvSISD H register. */
1918 static struct type
*
1919 aarch64_vnh_type (struct gdbarch
*gdbarch
)
1921 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1923 if (tdep
->vnh_type
== NULL
)
1928 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
1931 elem
= builtin_type (gdbarch
)->builtin_uint16
;
1932 append_composite_type_field (t
, "u", elem
);
1934 elem
= builtin_type (gdbarch
)->builtin_int16
;
1935 append_composite_type_field (t
, "s", elem
);
1940 return tdep
->vnh_type
;
1943 /* Return the type for an AdvSISD B register. */
1945 static struct type
*
1946 aarch64_vnb_type (struct gdbarch
*gdbarch
)
1948 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1950 if (tdep
->vnb_type
== NULL
)
1955 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
1958 elem
= builtin_type (gdbarch
)->builtin_uint8
;
1959 append_composite_type_field (t
, "u", elem
);
1961 elem
= builtin_type (gdbarch
)->builtin_int8
;
1962 append_composite_type_field (t
, "s", elem
);
1967 return tdep
->vnb_type
;
1970 /* Return the type for an AdvSISD V register. */
1972 static struct type
*
1973 aarch64_vnv_type (struct gdbarch
*gdbarch
)
1975 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1977 if (tdep
->vnv_type
== NULL
)
1979 /* The other AArch64 psuedo registers (Q,D,H,S,B) refer to a single value
1980 slice from the non-pseudo vector registers. However NEON V registers
1981 are always vector registers, and need constructing as such. */
1982 const struct builtin_type
*bt
= builtin_type (gdbarch
);
1984 struct type
*t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnv",
1987 struct type
*sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
1989 append_composite_type_field (sub
, "f",
1990 init_vector_type (bt
->builtin_double
, 2));
1991 append_composite_type_field (sub
, "u",
1992 init_vector_type (bt
->builtin_uint64
, 2));
1993 append_composite_type_field (sub
, "s",
1994 init_vector_type (bt
->builtin_int64
, 2));
1995 append_composite_type_field (t
, "d", sub
);
1997 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
1999 append_composite_type_field (sub
, "f",
2000 init_vector_type (bt
->builtin_float
, 4));
2001 append_composite_type_field (sub
, "u",
2002 init_vector_type (bt
->builtin_uint32
, 4));
2003 append_composite_type_field (sub
, "s",
2004 init_vector_type (bt
->builtin_int32
, 4));
2005 append_composite_type_field (t
, "s", sub
);
2007 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
2009 append_composite_type_field (sub
, "u",
2010 init_vector_type (bt
->builtin_uint16
, 8));
2011 append_composite_type_field (sub
, "s",
2012 init_vector_type (bt
->builtin_int16
, 8));
2013 append_composite_type_field (t
, "h", sub
);
2015 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
2017 append_composite_type_field (sub
, "u",
2018 init_vector_type (bt
->builtin_uint8
, 16));
2019 append_composite_type_field (sub
, "s",
2020 init_vector_type (bt
->builtin_int8
, 16));
2021 append_composite_type_field (t
, "b", sub
);
2023 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
2025 append_composite_type_field (sub
, "u",
2026 init_vector_type (bt
->builtin_uint128
, 1));
2027 append_composite_type_field (sub
, "s",
2028 init_vector_type (bt
->builtin_int128
, 1));
2029 append_composite_type_field (t
, "q", sub
);
2034 return tdep
->vnv_type
;
2037 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
2040 aarch64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
2042 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2044 if (reg
>= AARCH64_DWARF_X0
&& reg
<= AARCH64_DWARF_X0
+ 30)
2045 return AARCH64_X0_REGNUM
+ reg
- AARCH64_DWARF_X0
;
2047 if (reg
== AARCH64_DWARF_SP
)
2048 return AARCH64_SP_REGNUM
;
2050 if (reg
>= AARCH64_DWARF_V0
&& reg
<= AARCH64_DWARF_V0
+ 31)
2051 return AARCH64_V0_REGNUM
+ reg
- AARCH64_DWARF_V0
;
2053 if (reg
== AARCH64_DWARF_SVE_VG
)
2054 return AARCH64_SVE_VG_REGNUM
;
2056 if (reg
== AARCH64_DWARF_SVE_FFR
)
2057 return AARCH64_SVE_FFR_REGNUM
;
2059 if (reg
>= AARCH64_DWARF_SVE_P0
&& reg
<= AARCH64_DWARF_SVE_P0
+ 15)
2060 return AARCH64_SVE_P0_REGNUM
+ reg
- AARCH64_DWARF_SVE_P0
;
2062 if (reg
>= AARCH64_DWARF_SVE_Z0
&& reg
<= AARCH64_DWARF_SVE_Z0
+ 15)
2063 return AARCH64_SVE_Z0_REGNUM
+ reg
- AARCH64_DWARF_SVE_Z0
;
2065 if (tdep
->has_pauth ())
2067 if (reg
>= AARCH64_DWARF_PAUTH_DMASK
&& reg
<= AARCH64_DWARF_PAUTH_CMASK
)
2068 return tdep
->pauth_reg_base
+ reg
- AARCH64_DWARF_PAUTH_DMASK
;
2070 if (reg
== AARCH64_DWARF_PAUTH_RA_STATE
)
2071 return tdep
->pauth_ra_state_regnum
;
2077 /* Implement the "print_insn" gdbarch method. */
2080 aarch64_gdb_print_insn (bfd_vma memaddr
, disassemble_info
*info
)
2082 info
->symbols
= NULL
;
2083 return default_print_insn (memaddr
, info
);
2086 /* AArch64 BRK software debug mode instruction.
2087 Note that AArch64 code is always little-endian.
2088 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
2089 constexpr gdb_byte aarch64_default_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
2091 typedef BP_MANIPULATION (aarch64_default_breakpoint
) aarch64_breakpoint
;
2093 /* Extract from an array REGS containing the (raw) register state a
2094 function return value of type TYPE, and copy that, in virtual
2095 format, into VALBUF. */
2098 aarch64_extract_return_value (struct type
*type
, struct regcache
*regs
,
2101 struct gdbarch
*gdbarch
= regs
->arch ();
2102 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2104 struct type
*fundamental_type
;
2106 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2109 int len
= TYPE_LENGTH (fundamental_type
);
2111 for (int i
= 0; i
< elements
; i
++)
2113 int regno
= AARCH64_V0_REGNUM
+ i
;
2114 /* Enough space for a full vector register. */
2115 gdb_byte buf
[register_size (gdbarch
, regno
)];
2116 gdb_assert (len
<= sizeof (buf
));
2120 debug_printf ("read HFA or HVA return value element %d from %s\n",
2122 gdbarch_register_name (gdbarch
, regno
));
2124 regs
->cooked_read (regno
, buf
);
2126 memcpy (valbuf
, buf
, len
);
2130 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2131 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2132 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2133 || TYPE_CODE (type
) == TYPE_CODE_PTR
2134 || TYPE_IS_REFERENCE (type
)
2135 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2137 /* If the type is a plain integer, then the access is
2138 straight-forward. Otherwise we have to play around a bit
2140 int len
= TYPE_LENGTH (type
);
2141 int regno
= AARCH64_X0_REGNUM
;
2146 /* By using store_unsigned_integer we avoid having to do
2147 anything special for small big-endian values. */
2148 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2149 store_unsigned_integer (valbuf
,
2150 (len
> X_REGISTER_SIZE
2151 ? X_REGISTER_SIZE
: len
), byte_order
, tmp
);
2152 len
-= X_REGISTER_SIZE
;
2153 valbuf
+= X_REGISTER_SIZE
;
2158 /* For a structure or union the behaviour is as if the value had
2159 been stored to word-aligned memory and then loaded into
2160 registers with 64-bit load instruction(s). */
2161 int len
= TYPE_LENGTH (type
);
2162 int regno
= AARCH64_X0_REGNUM
;
2163 bfd_byte buf
[X_REGISTER_SIZE
];
2167 regs
->cooked_read (regno
++, buf
);
2168 memcpy (valbuf
, buf
, len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2169 len
-= X_REGISTER_SIZE
;
2170 valbuf
+= X_REGISTER_SIZE
;
2176 /* Will a function return an aggregate type in memory or in a
2177 register? Return 0 if an aggregate type can be returned in a
2178 register, 1 if it must be returned in memory. */
2181 aarch64_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2183 type
= check_typedef (type
);
2185 struct type
*fundamental_type
;
2187 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2190 /* v0-v7 are used to return values and one register is allocated
2191 for one member. However, HFA or HVA has at most four members. */
2195 if (TYPE_LENGTH (type
) > 16)
2197 /* PCS B.6 Aggregates larger than 16 bytes are passed by
2198 invisible reference. */
2206 /* Write into appropriate registers a function return value of type
2207 TYPE, given in virtual format. */
2210 aarch64_store_return_value (struct type
*type
, struct regcache
*regs
,
2211 const gdb_byte
*valbuf
)
2213 struct gdbarch
*gdbarch
= regs
->arch ();
2214 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2216 struct type
*fundamental_type
;
2218 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2221 int len
= TYPE_LENGTH (fundamental_type
);
2223 for (int i
= 0; i
< elements
; i
++)
2225 int regno
= AARCH64_V0_REGNUM
+ i
;
2226 /* Enough space for a full vector register. */
2227 gdb_byte tmpbuf
[register_size (gdbarch
, regno
)];
2228 gdb_assert (len
<= sizeof (tmpbuf
));
2232 debug_printf ("write HFA or HVA return value element %d to %s\n",
2234 gdbarch_register_name (gdbarch
, regno
));
2237 memcpy (tmpbuf
, valbuf
,
2238 len
> V_REGISTER_SIZE
? V_REGISTER_SIZE
: len
);
2239 regs
->cooked_write (regno
, tmpbuf
);
2243 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2244 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2245 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2246 || TYPE_CODE (type
) == TYPE_CODE_PTR
2247 || TYPE_IS_REFERENCE (type
)
2248 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2250 if (TYPE_LENGTH (type
) <= X_REGISTER_SIZE
)
2252 /* Values of one word or less are zero/sign-extended and
2254 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2255 LONGEST val
= unpack_long (type
, valbuf
);
2257 store_signed_integer (tmpbuf
, X_REGISTER_SIZE
, byte_order
, val
);
2258 regs
->cooked_write (AARCH64_X0_REGNUM
, tmpbuf
);
2262 /* Integral values greater than one word are stored in
2263 consecutive registers starting with r0. This will always
2264 be a multiple of the regiser size. */
2265 int len
= TYPE_LENGTH (type
);
2266 int regno
= AARCH64_X0_REGNUM
;
2270 regs
->cooked_write (regno
++, valbuf
);
2271 len
-= X_REGISTER_SIZE
;
2272 valbuf
+= X_REGISTER_SIZE
;
2278 /* For a structure or union the behaviour is as if the value had
2279 been stored to word-aligned memory and then loaded into
2280 registers with 64-bit load instruction(s). */
2281 int len
= TYPE_LENGTH (type
);
2282 int regno
= AARCH64_X0_REGNUM
;
2283 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2287 memcpy (tmpbuf
, valbuf
,
2288 len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2289 regs
->cooked_write (regno
++, tmpbuf
);
2290 len
-= X_REGISTER_SIZE
;
2291 valbuf
+= X_REGISTER_SIZE
;
2296 /* Implement the "return_value" gdbarch method. */
2298 static enum return_value_convention
2299 aarch64_return_value (struct gdbarch
*gdbarch
, struct value
*func_value
,
2300 struct type
*valtype
, struct regcache
*regcache
,
2301 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2304 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2305 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2306 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2308 if (aarch64_return_in_memory (gdbarch
, valtype
))
2311 debug_printf ("return value in memory\n");
2312 return RETURN_VALUE_STRUCT_CONVENTION
;
2317 aarch64_store_return_value (valtype
, regcache
, writebuf
);
2320 aarch64_extract_return_value (valtype
, regcache
, readbuf
);
2323 debug_printf ("return value in registers\n");
2325 return RETURN_VALUE_REGISTER_CONVENTION
;
2328 /* Implement the "get_longjmp_target" gdbarch method. */
2331 aarch64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2334 gdb_byte buf
[X_REGISTER_SIZE
];
2335 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2336 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2337 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2339 jb_addr
= get_frame_register_unsigned (frame
, AARCH64_X0_REGNUM
);
2341 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2345 *pc
= extract_unsigned_integer (buf
, X_REGISTER_SIZE
, byte_order
);
2349 /* Implement the "gen_return_address" gdbarch method. */
2352 aarch64_gen_return_address (struct gdbarch
*gdbarch
,
2353 struct agent_expr
*ax
, struct axs_value
*value
,
2356 value
->type
= register_type (gdbarch
, AARCH64_LR_REGNUM
);
2357 value
->kind
= axs_lvalue_register
;
2358 value
->u
.reg
= AARCH64_LR_REGNUM
;
2362 /* Return the pseudo register name corresponding to register regnum. */
2365 aarch64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
2367 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2369 static const char *const q_name
[] =
2371 "q0", "q1", "q2", "q3",
2372 "q4", "q5", "q6", "q7",
2373 "q8", "q9", "q10", "q11",
2374 "q12", "q13", "q14", "q15",
2375 "q16", "q17", "q18", "q19",
2376 "q20", "q21", "q22", "q23",
2377 "q24", "q25", "q26", "q27",
2378 "q28", "q29", "q30", "q31",
2381 static const char *const d_name
[] =
2383 "d0", "d1", "d2", "d3",
2384 "d4", "d5", "d6", "d7",
2385 "d8", "d9", "d10", "d11",
2386 "d12", "d13", "d14", "d15",
2387 "d16", "d17", "d18", "d19",
2388 "d20", "d21", "d22", "d23",
2389 "d24", "d25", "d26", "d27",
2390 "d28", "d29", "d30", "d31",
2393 static const char *const s_name
[] =
2395 "s0", "s1", "s2", "s3",
2396 "s4", "s5", "s6", "s7",
2397 "s8", "s9", "s10", "s11",
2398 "s12", "s13", "s14", "s15",
2399 "s16", "s17", "s18", "s19",
2400 "s20", "s21", "s22", "s23",
2401 "s24", "s25", "s26", "s27",
2402 "s28", "s29", "s30", "s31",
2405 static const char *const h_name
[] =
2407 "h0", "h1", "h2", "h3",
2408 "h4", "h5", "h6", "h7",
2409 "h8", "h9", "h10", "h11",
2410 "h12", "h13", "h14", "h15",
2411 "h16", "h17", "h18", "h19",
2412 "h20", "h21", "h22", "h23",
2413 "h24", "h25", "h26", "h27",
2414 "h28", "h29", "h30", "h31",
2417 static const char *const b_name
[] =
2419 "b0", "b1", "b2", "b3",
2420 "b4", "b5", "b6", "b7",
2421 "b8", "b9", "b10", "b11",
2422 "b12", "b13", "b14", "b15",
2423 "b16", "b17", "b18", "b19",
2424 "b20", "b21", "b22", "b23",
2425 "b24", "b25", "b26", "b27",
2426 "b28", "b29", "b30", "b31",
2429 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2431 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2432 return q_name
[p_regnum
- AARCH64_Q0_REGNUM
];
2434 if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2435 return d_name
[p_regnum
- AARCH64_D0_REGNUM
];
2437 if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2438 return s_name
[p_regnum
- AARCH64_S0_REGNUM
];
2440 if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2441 return h_name
[p_regnum
- AARCH64_H0_REGNUM
];
2443 if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2444 return b_name
[p_regnum
- AARCH64_B0_REGNUM
];
2446 if (tdep
->has_sve ())
2448 static const char *const sve_v_name
[] =
2450 "v0", "v1", "v2", "v3",
2451 "v4", "v5", "v6", "v7",
2452 "v8", "v9", "v10", "v11",
2453 "v12", "v13", "v14", "v15",
2454 "v16", "v17", "v18", "v19",
2455 "v20", "v21", "v22", "v23",
2456 "v24", "v25", "v26", "v27",
2457 "v28", "v29", "v30", "v31",
2460 if (p_regnum
>= AARCH64_SVE_V0_REGNUM
2461 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2462 return sve_v_name
[p_regnum
- AARCH64_SVE_V0_REGNUM
];
2465 /* RA_STATE is used for unwinding only. Do not assign it a name - this
2466 prevents it from being read by methods such as
2467 mi_cmd_trace_frame_collected. */
2468 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2471 internal_error (__FILE__
, __LINE__
,
2472 _("aarch64_pseudo_register_name: bad register number %d"),
2476 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
2478 static struct type
*
2479 aarch64_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2481 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2483 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2485 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2486 return aarch64_vnq_type (gdbarch
);
2488 if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2489 return aarch64_vnd_type (gdbarch
);
2491 if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2492 return aarch64_vns_type (gdbarch
);
2494 if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2495 return aarch64_vnh_type (gdbarch
);
2497 if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2498 return aarch64_vnb_type (gdbarch
);
2500 if (tdep
->has_sve () && p_regnum
>= AARCH64_SVE_V0_REGNUM
2501 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2502 return aarch64_vnv_type (gdbarch
);
2504 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2505 return builtin_type (gdbarch
)->builtin_uint64
;
2507 internal_error (__FILE__
, __LINE__
,
2508 _("aarch64_pseudo_register_type: bad register number %d"),
2512 /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2515 aarch64_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2516 struct reggroup
*group
)
2518 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2520 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2522 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2523 return group
== all_reggroup
|| group
== vector_reggroup
;
2524 else if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2525 return (group
== all_reggroup
|| group
== vector_reggroup
2526 || group
== float_reggroup
);
2527 else if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2528 return (group
== all_reggroup
|| group
== vector_reggroup
2529 || group
== float_reggroup
);
2530 else if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2531 return group
== all_reggroup
|| group
== vector_reggroup
;
2532 else if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2533 return group
== all_reggroup
|| group
== vector_reggroup
;
2534 else if (tdep
->has_sve () && p_regnum
>= AARCH64_SVE_V0_REGNUM
2535 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2536 return group
== all_reggroup
|| group
== vector_reggroup
;
2537 /* RA_STATE is used for unwinding only. Do not assign it to any groups. */
2538 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2541 return group
== all_reggroup
;
2544 /* Helper for aarch64_pseudo_read_value. */
2546 static struct value
*
2547 aarch64_pseudo_read_value_1 (struct gdbarch
*gdbarch
,
2548 readable_regcache
*regcache
, int regnum_offset
,
2549 int regsize
, struct value
*result_value
)
2551 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2553 /* Enough space for a full vector register. */
2554 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2555 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2557 if (regcache
->raw_read (v_regnum
, reg_buf
) != REG_VALID
)
2558 mark_value_bytes_unavailable (result_value
, 0,
2559 TYPE_LENGTH (value_type (result_value
)));
2561 memcpy (value_contents_raw (result_value
), reg_buf
, regsize
);
2563 return result_value
;
2566 /* Implement the "pseudo_register_read_value" gdbarch method. */
2568 static struct value
*
2569 aarch64_pseudo_read_value (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2572 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2573 struct value
*result_value
= allocate_value (register_type (gdbarch
, regnum
));
2575 VALUE_LVAL (result_value
) = lval_register
;
2576 VALUE_REGNUM (result_value
) = regnum
;
2578 regnum
-= gdbarch_num_regs (gdbarch
);
2580 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2581 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2582 regnum
- AARCH64_Q0_REGNUM
,
2583 Q_REGISTER_SIZE
, result_value
);
2585 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2586 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2587 regnum
- AARCH64_D0_REGNUM
,
2588 D_REGISTER_SIZE
, result_value
);
2590 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2591 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2592 regnum
- AARCH64_S0_REGNUM
,
2593 S_REGISTER_SIZE
, result_value
);
2595 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2596 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2597 regnum
- AARCH64_H0_REGNUM
,
2598 H_REGISTER_SIZE
, result_value
);
2600 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2601 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2602 regnum
- AARCH64_B0_REGNUM
,
2603 B_REGISTER_SIZE
, result_value
);
2605 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2606 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2607 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2608 regnum
- AARCH64_SVE_V0_REGNUM
,
2609 V_REGISTER_SIZE
, result_value
);
2611 gdb_assert_not_reached ("regnum out of bound");
2614 /* Helper for aarch64_pseudo_write. */
2617 aarch64_pseudo_write_1 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2618 int regnum_offset
, int regsize
, const gdb_byte
*buf
)
2620 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2622 /* Enough space for a full vector register. */
2623 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2624 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2626 /* Ensure the register buffer is zero, we want gdb writes of the
2627 various 'scalar' pseudo registers to behavior like architectural
2628 writes, register width bytes are written the remainder are set to
2630 memset (reg_buf
, 0, register_size (gdbarch
, AARCH64_V0_REGNUM
));
2632 memcpy (reg_buf
, buf
, regsize
);
2633 regcache
->raw_write (v_regnum
, reg_buf
);
2636 /* Implement the "pseudo_register_write" gdbarch method. */
2639 aarch64_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2640 int regnum
, const gdb_byte
*buf
)
2642 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2643 regnum
-= gdbarch_num_regs (gdbarch
);
2645 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2646 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2647 regnum
- AARCH64_Q0_REGNUM
, Q_REGISTER_SIZE
,
2650 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2651 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2652 regnum
- AARCH64_D0_REGNUM
, D_REGISTER_SIZE
,
2655 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2656 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2657 regnum
- AARCH64_S0_REGNUM
, S_REGISTER_SIZE
,
2660 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2661 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2662 regnum
- AARCH64_H0_REGNUM
, H_REGISTER_SIZE
,
2665 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2666 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2667 regnum
- AARCH64_B0_REGNUM
, B_REGISTER_SIZE
,
2670 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2671 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2672 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2673 regnum
- AARCH64_SVE_V0_REGNUM
,
2674 V_REGISTER_SIZE
, buf
);
2676 gdb_assert_not_reached ("regnum out of bound");
2679 /* Callback function for user_reg_add. */
2681 static struct value
*
2682 value_of_aarch64_user_reg (struct frame_info
*frame
, const void *baton
)
2684 const int *reg_p
= (const int *) baton
;
2686 return value_of_register (*reg_p
, frame
);
2690 /* Implement the "software_single_step" gdbarch method, needed to
2691 single step through atomic sequences on AArch64. */
2693 static std::vector
<CORE_ADDR
>
2694 aarch64_software_single_step (struct regcache
*regcache
)
2696 struct gdbarch
*gdbarch
= regcache
->arch ();
2697 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2698 const int insn_size
= 4;
2699 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2700 CORE_ADDR pc
= regcache_read_pc (regcache
);
2701 CORE_ADDR breaks
[2] = { CORE_ADDR_MAX
, CORE_ADDR_MAX
};
2703 CORE_ADDR closing_insn
= 0;
2704 uint32_t insn
= read_memory_unsigned_integer (loc
, insn_size
,
2705 byte_order_for_code
);
2708 int bc_insn_count
= 0; /* Conditional branch instruction count. */
2709 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2712 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2715 /* Look for a Load Exclusive instruction which begins the sequence. */
2716 if (inst
.opcode
->iclass
!= ldstexcl
|| bit (insn
, 22) == 0)
2719 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2722 insn
= read_memory_unsigned_integer (loc
, insn_size
,
2723 byte_order_for_code
);
2725 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2727 /* Check if the instruction is a conditional branch. */
2728 if (inst
.opcode
->iclass
== condbranch
)
2730 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_ADDR_PCREL19
);
2732 if (bc_insn_count
>= 1)
2735 /* It is, so we'll try to set a breakpoint at the destination. */
2736 breaks
[1] = loc
+ inst
.operands
[0].imm
.value
;
2742 /* Look for the Store Exclusive which closes the atomic sequence. */
2743 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22) == 0)
2750 /* We didn't find a closing Store Exclusive instruction, fall back. */
2754 /* Insert breakpoint after the end of the atomic sequence. */
2755 breaks
[0] = loc
+ insn_size
;
2757 /* Check for duplicated breakpoints, and also check that the second
2758 breakpoint is not within the atomic sequence. */
2760 && (breaks
[1] == breaks
[0]
2761 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
2762 last_breakpoint
= 0;
2764 std::vector
<CORE_ADDR
> next_pcs
;
2766 /* Insert the breakpoint at the end of the sequence, and one at the
2767 destination of the conditional branch, if it exists. */
2768 for (index
= 0; index
<= last_breakpoint
; index
++)
2769 next_pcs
.push_back (breaks
[index
]);
2774 struct aarch64_displaced_step_closure
: public displaced_step_closure
2776 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2777 is being displaced stepping. */
2780 /* PC adjustment offset after displaced stepping. */
2781 int32_t pc_adjust
= 0;
2784 /* Data when visiting instructions for displaced stepping. */
2786 struct aarch64_displaced_step_data
2788 struct aarch64_insn_data base
;
2790 /* The address where the instruction will be executed at. */
2792 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2793 uint32_t insn_buf
[DISPLACED_MODIFIED_INSNS
];
2794 /* Number of instructions in INSN_BUF. */
2795 unsigned insn_count
;
2796 /* Registers when doing displaced stepping. */
2797 struct regcache
*regs
;
2799 aarch64_displaced_step_closure
*dsc
;
2802 /* Implementation of aarch64_insn_visitor method "b". */
2805 aarch64_displaced_step_b (const int is_bl
, const int32_t offset
,
2806 struct aarch64_insn_data
*data
)
2808 struct aarch64_displaced_step_data
*dsd
2809 = (struct aarch64_displaced_step_data
*) data
;
2810 int64_t new_offset
= data
->insn_addr
- dsd
->new_addr
+ offset
;
2812 if (can_encode_int32 (new_offset
, 28))
2814 /* Emit B rather than BL, because executing BL on a new address
2815 will get the wrong address into LR. In order to avoid this,
2816 we emit B, and update LR if the instruction is BL. */
2817 emit_b (dsd
->insn_buf
, 0, new_offset
);
2823 emit_nop (dsd
->insn_buf
);
2825 dsd
->dsc
->pc_adjust
= offset
;
2831 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_LR_REGNUM
,
2832 data
->insn_addr
+ 4);
2836 /* Implementation of aarch64_insn_visitor method "b_cond". */
2839 aarch64_displaced_step_b_cond (const unsigned cond
, const int32_t offset
,
2840 struct aarch64_insn_data
*data
)
2842 struct aarch64_displaced_step_data
*dsd
2843 = (struct aarch64_displaced_step_data
*) data
;
2845 /* GDB has to fix up PC after displaced step this instruction
2846 differently according to the condition is true or false. Instead
2847 of checking COND against conditional flags, we can use
2848 the following instructions, and GDB can tell how to fix up PC
2849 according to the PC value.
2851 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2857 emit_bcond (dsd
->insn_buf
, cond
, 8);
2859 dsd
->dsc
->pc_adjust
= offset
;
2860 dsd
->insn_count
= 1;
2863 /* Dynamically allocate a new register. If we know the register
2864 statically, we should make it a global as above instead of using this
2867 static struct aarch64_register
2868 aarch64_register (unsigned num
, int is64
)
2870 return (struct aarch64_register
) { num
, is64
};
2873 /* Implementation of aarch64_insn_visitor method "cb". */
2876 aarch64_displaced_step_cb (const int32_t offset
, const int is_cbnz
,
2877 const unsigned rn
, int is64
,
2878 struct aarch64_insn_data
*data
)
2880 struct aarch64_displaced_step_data
*dsd
2881 = (struct aarch64_displaced_step_data
*) data
;
2883 /* The offset is out of range for a compare and branch
2884 instruction. We can use the following instructions instead:
2886 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2891 emit_cb (dsd
->insn_buf
, is_cbnz
, aarch64_register (rn
, is64
), 8);
2892 dsd
->insn_count
= 1;
2894 dsd
->dsc
->pc_adjust
= offset
;
2897 /* Implementation of aarch64_insn_visitor method "tb". */
2900 aarch64_displaced_step_tb (const int32_t offset
, int is_tbnz
,
2901 const unsigned rt
, unsigned bit
,
2902 struct aarch64_insn_data
*data
)
2904 struct aarch64_displaced_step_data
*dsd
2905 = (struct aarch64_displaced_step_data
*) data
;
2907 /* The offset is out of range for a test bit and branch
2908 instruction We can use the following instructions instead:
2910 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2916 emit_tb (dsd
->insn_buf
, is_tbnz
, bit
, aarch64_register (rt
, 1), 8);
2917 dsd
->insn_count
= 1;
2919 dsd
->dsc
->pc_adjust
= offset
;
2922 /* Implementation of aarch64_insn_visitor method "adr". */
2925 aarch64_displaced_step_adr (const int32_t offset
, const unsigned rd
,
2926 const int is_adrp
, struct aarch64_insn_data
*data
)
2928 struct aarch64_displaced_step_data
*dsd
2929 = (struct aarch64_displaced_step_data
*) data
;
2930 /* We know exactly the address the ADR{P,} instruction will compute.
2931 We can just write it to the destination register. */
2932 CORE_ADDR address
= data
->insn_addr
+ offset
;
2936 /* Clear the lower 12 bits of the offset to get the 4K page. */
2937 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
2941 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
2944 dsd
->dsc
->pc_adjust
= 4;
2945 emit_nop (dsd
->insn_buf
);
2946 dsd
->insn_count
= 1;
2949 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
2952 aarch64_displaced_step_ldr_literal (const int32_t offset
, const int is_sw
,
2953 const unsigned rt
, const int is64
,
2954 struct aarch64_insn_data
*data
)
2956 struct aarch64_displaced_step_data
*dsd
2957 = (struct aarch64_displaced_step_data
*) data
;
2958 CORE_ADDR address
= data
->insn_addr
+ offset
;
2959 struct aarch64_memory_operand zero
= { MEMORY_OPERAND_OFFSET
, 0 };
2961 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rt
,
2965 dsd
->insn_count
= emit_ldrsw (dsd
->insn_buf
, aarch64_register (rt
, 1),
2966 aarch64_register (rt
, 1), zero
);
2968 dsd
->insn_count
= emit_ldr (dsd
->insn_buf
, aarch64_register (rt
, is64
),
2969 aarch64_register (rt
, 1), zero
);
2971 dsd
->dsc
->pc_adjust
= 4;
2974 /* Implementation of aarch64_insn_visitor method "others". */
2977 aarch64_displaced_step_others (const uint32_t insn
,
2978 struct aarch64_insn_data
*data
)
2980 struct aarch64_displaced_step_data
*dsd
2981 = (struct aarch64_displaced_step_data
*) data
;
2983 aarch64_emit_insn (dsd
->insn_buf
, insn
);
2984 dsd
->insn_count
= 1;
2986 if ((insn
& 0xfffffc1f) == 0xd65f0000)
2989 dsd
->dsc
->pc_adjust
= 0;
2992 dsd
->dsc
->pc_adjust
= 4;
2995 static const struct aarch64_insn_visitor visitor
=
2997 aarch64_displaced_step_b
,
2998 aarch64_displaced_step_b_cond
,
2999 aarch64_displaced_step_cb
,
3000 aarch64_displaced_step_tb
,
3001 aarch64_displaced_step_adr
,
3002 aarch64_displaced_step_ldr_literal
,
3003 aarch64_displaced_step_others
,
3006 /* Implement the "displaced_step_copy_insn" gdbarch method. */
3008 struct displaced_step_closure
*
3009 aarch64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
3010 CORE_ADDR from
, CORE_ADDR to
,
3011 struct regcache
*regs
)
3013 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3014 uint32_t insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
3015 struct aarch64_displaced_step_data dsd
;
3018 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
3021 /* Look for a Load Exclusive instruction which begins the sequence. */
3022 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22))
3024 /* We can't displaced step atomic sequences. */
3028 std::unique_ptr
<aarch64_displaced_step_closure
> dsc
3029 (new aarch64_displaced_step_closure
);
3030 dsd
.base
.insn_addr
= from
;
3033 dsd
.dsc
= dsc
.get ();
3035 aarch64_relocate_instruction (insn
, &visitor
,
3036 (struct aarch64_insn_data
*) &dsd
);
3037 gdb_assert (dsd
.insn_count
<= DISPLACED_MODIFIED_INSNS
);
3039 if (dsd
.insn_count
!= 0)
3043 /* Instruction can be relocated to scratch pad. Copy
3044 relocated instruction(s) there. */
3045 for (i
= 0; i
< dsd
.insn_count
; i
++)
3047 if (debug_displaced
)
3049 debug_printf ("displaced: writing insn ");
3050 debug_printf ("%.8x", dsd
.insn_buf
[i
]);
3051 debug_printf (" at %s\n", paddress (gdbarch
, to
+ i
* 4));
3053 write_memory_unsigned_integer (to
+ i
* 4, 4, byte_order_for_code
,
3054 (ULONGEST
) dsd
.insn_buf
[i
]);
3062 return dsc
.release ();
3065 /* Implement the "displaced_step_fixup" gdbarch method. */
3068 aarch64_displaced_step_fixup (struct gdbarch
*gdbarch
,
3069 struct displaced_step_closure
*dsc_
,
3070 CORE_ADDR from
, CORE_ADDR to
,
3071 struct regcache
*regs
)
3073 aarch64_displaced_step_closure
*dsc
= (aarch64_displaced_step_closure
*) dsc_
;
3079 regcache_cooked_read_unsigned (regs
, AARCH64_PC_REGNUM
, &pc
);
3082 /* Condition is true. */
3084 else if (pc
- to
== 4)
3086 /* Condition is false. */
3090 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
3093 if (dsc
->pc_adjust
!= 0)
3095 if (debug_displaced
)
3097 debug_printf ("displaced: fixup: set PC to %s:%d\n",
3098 paddress (gdbarch
, from
), dsc
->pc_adjust
);
3100 regcache_cooked_write_unsigned (regs
, AARCH64_PC_REGNUM
,
3101 from
+ dsc
->pc_adjust
);
3105 /* Implement the "displaced_step_hw_singlestep" gdbarch method. */
3108 aarch64_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
3109 struct displaced_step_closure
*closure
)
3114 /* Get the correct target description for the given VQ value.
3115 If VQ is zero then it is assumed SVE is not supported.
3116 (It is not possible to set VQ to zero on an SVE system). */
3119 aarch64_read_description (uint64_t vq
, bool pauth_p
)
3121 if (vq
> AARCH64_MAX_SVE_VQ
)
3122 error (_("VQ is %" PRIu64
", maximum supported value is %d"), vq
,
3123 AARCH64_MAX_SVE_VQ
);
3125 struct target_desc
*tdesc
= tdesc_aarch64_list
[vq
][pauth_p
];
3129 tdesc
= aarch64_create_target_description (vq
, pauth_p
);
3130 tdesc_aarch64_list
[vq
][pauth_p
] = tdesc
;
3136 /* Return the VQ used when creating the target description TDESC. */
3139 aarch64_get_tdesc_vq (const struct target_desc
*tdesc
)
3141 const struct tdesc_feature
*feature_sve
;
3143 if (!tdesc_has_registers (tdesc
))
3146 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3148 if (feature_sve
== nullptr)
3151 uint64_t vl
= tdesc_register_bitsize (feature_sve
,
3152 aarch64_sve_register_names
[0]) / 8;
3153 return sve_vq_from_vl (vl
);
3156 /* Add all the expected register sets into GDBARCH. */
3159 aarch64_add_reggroups (struct gdbarch
*gdbarch
)
3161 reggroup_add (gdbarch
, general_reggroup
);
3162 reggroup_add (gdbarch
, float_reggroup
);
3163 reggroup_add (gdbarch
, system_reggroup
);
3164 reggroup_add (gdbarch
, vector_reggroup
);
3165 reggroup_add (gdbarch
, all_reggroup
);
3166 reggroup_add (gdbarch
, save_reggroup
);
3167 reggroup_add (gdbarch
, restore_reggroup
);
3170 /* Implement the "cannot_store_register" gdbarch method. */
3173 aarch64_cannot_store_register (struct gdbarch
*gdbarch
, int regnum
)
3175 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3177 if (!tdep
->has_pauth ())
3180 /* Pointer authentication registers are read-only. */
3181 return (regnum
== AARCH64_PAUTH_DMASK_REGNUM (tdep
->pauth_reg_base
)
3182 || regnum
== AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
));
3185 /* Initialize the current architecture based on INFO. If possible,
3186 re-use an architecture from ARCHES, which is a list of
3187 architectures already created during this debugging session.
3189 Called e.g. at program startup, when reading a core file, and when
3190 reading a binary file. */
3192 static struct gdbarch
*
3193 aarch64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3195 const struct tdesc_feature
*feature_core
, *feature_fpu
, *feature_sve
;
3196 const struct tdesc_feature
*feature_pauth
;
3197 bool valid_p
= true;
3198 int i
, num_regs
= 0, num_pseudo_regs
= 0;
3199 int first_pauth_regnum
= -1, pauth_ra_state_offset
= -1;
3201 /* If there is already a candidate, use it. */
3202 for (gdbarch_list
*best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
3203 best_arch
!= nullptr;
3204 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
3206 struct gdbarch_tdep
*tdep
= gdbarch_tdep (best_arch
->gdbarch
);
3208 return best_arch
->gdbarch
;
3211 /* Ensure we always have a target description. */
3212 const struct target_desc
*tdesc
= info
.target_desc
;
3213 if (!tdesc_has_registers (tdesc
))
3214 tdesc
= aarch64_read_description (0, false);
3217 feature_core
= tdesc_find_feature (tdesc
,"org.gnu.gdb.aarch64.core");
3218 feature_fpu
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.fpu");
3219 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3220 feature_pauth
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.pauth");
3222 if (feature_core
== nullptr)
3225 struct tdesc_arch_data
*tdesc_data
= tdesc_data_alloc ();
3227 /* Validate the description provides the mandatory core R registers
3228 and allocate their numbers. */
3229 for (i
= 0; i
< ARRAY_SIZE (aarch64_r_register_names
); i
++)
3230 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
,
3231 AARCH64_X0_REGNUM
+ i
,
3232 aarch64_r_register_names
[i
]);
3234 num_regs
= AARCH64_X0_REGNUM
+ i
;
3236 /* Add the V registers. */
3237 if (feature_fpu
!= nullptr)
3239 if (feature_sve
!= nullptr)
3240 error (_("Program contains both fpu and SVE features."));
3242 /* Validate the description provides the mandatory V registers
3243 and allocate their numbers. */
3244 for (i
= 0; i
< ARRAY_SIZE (aarch64_v_register_names
); i
++)
3245 valid_p
&= tdesc_numbered_register (feature_fpu
, tdesc_data
,
3246 AARCH64_V0_REGNUM
+ i
,
3247 aarch64_v_register_names
[i
]);
3249 num_regs
= AARCH64_V0_REGNUM
+ i
;
3252 /* Add the SVE registers. */
3253 if (feature_sve
!= nullptr)
3255 /* Validate the description provides the mandatory SVE registers
3256 and allocate their numbers. */
3257 for (i
= 0; i
< ARRAY_SIZE (aarch64_sve_register_names
); i
++)
3258 valid_p
&= tdesc_numbered_register (feature_sve
, tdesc_data
,
3259 AARCH64_SVE_Z0_REGNUM
+ i
,
3260 aarch64_sve_register_names
[i
]);
3262 num_regs
= AARCH64_SVE_Z0_REGNUM
+ i
;
3263 num_pseudo_regs
+= 32; /* add the Vn register pseudos. */
3266 if (feature_fpu
!= nullptr || feature_sve
!= nullptr)
3268 num_pseudo_regs
+= 32; /* add the Qn scalar register pseudos */
3269 num_pseudo_regs
+= 32; /* add the Dn scalar register pseudos */
3270 num_pseudo_regs
+= 32; /* add the Sn scalar register pseudos */
3271 num_pseudo_regs
+= 32; /* add the Hn scalar register pseudos */
3272 num_pseudo_regs
+= 32; /* add the Bn scalar register pseudos */
3275 /* Add the pauth registers. */
3276 if (feature_pauth
!= NULL
)
3278 first_pauth_regnum
= num_regs
;
3279 pauth_ra_state_offset
= num_pseudo_regs
;
3280 /* Validate the descriptor provides the mandatory PAUTH registers and
3281 allocate their numbers. */
3282 for (i
= 0; i
< ARRAY_SIZE (aarch64_pauth_register_names
); i
++)
3283 valid_p
&= tdesc_numbered_register (feature_pauth
, tdesc_data
,
3284 first_pauth_regnum
+ i
,
3285 aarch64_pauth_register_names
[i
]);
3288 num_pseudo_regs
+= 1; /* Count RA_STATE pseudo register. */
3293 tdesc_data_cleanup (tdesc_data
);
3297 /* AArch64 code is always little-endian. */
3298 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
3300 struct gdbarch_tdep
*tdep
= XCNEW (struct gdbarch_tdep
);
3301 struct gdbarch
*gdbarch
= gdbarch_alloc (&info
, tdep
);
3303 /* This should be low enough for everything. */
3304 tdep
->lowest_pc
= 0x20;
3305 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
3306 tdep
->jb_elt_size
= 8;
3307 tdep
->vq
= aarch64_get_tdesc_vq (tdesc
);
3308 tdep
->pauth_reg_base
= first_pauth_regnum
;
3309 tdep
->pauth_ra_state_regnum
= (feature_pauth
== NULL
) ? -1
3310 : pauth_ra_state_offset
+ num_regs
;
3312 set_gdbarch_push_dummy_call (gdbarch
, aarch64_push_dummy_call
);
3313 set_gdbarch_frame_align (gdbarch
, aarch64_frame_align
);
3315 /* Advance PC across function entry code. */
3316 set_gdbarch_skip_prologue (gdbarch
, aarch64_skip_prologue
);
3318 /* The stack grows downward. */
3319 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3321 /* Breakpoint manipulation. */
3322 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
3323 aarch64_breakpoint::kind_from_pc
);
3324 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
3325 aarch64_breakpoint::bp_from_kind
);
3326 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3327 set_gdbarch_software_single_step (gdbarch
, aarch64_software_single_step
);
3329 /* Information about registers, etc. */
3330 set_gdbarch_sp_regnum (gdbarch
, AARCH64_SP_REGNUM
);
3331 set_gdbarch_pc_regnum (gdbarch
, AARCH64_PC_REGNUM
);
3332 set_gdbarch_num_regs (gdbarch
, num_regs
);
3334 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudo_regs
);
3335 set_gdbarch_pseudo_register_read_value (gdbarch
, aarch64_pseudo_read_value
);
3336 set_gdbarch_pseudo_register_write (gdbarch
, aarch64_pseudo_write
);
3337 set_tdesc_pseudo_register_name (gdbarch
, aarch64_pseudo_register_name
);
3338 set_tdesc_pseudo_register_type (gdbarch
, aarch64_pseudo_register_type
);
3339 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3340 aarch64_pseudo_register_reggroup_p
);
3341 set_gdbarch_cannot_store_register (gdbarch
, aarch64_cannot_store_register
);
3344 set_gdbarch_short_bit (gdbarch
, 16);
3345 set_gdbarch_int_bit (gdbarch
, 32);
3346 set_gdbarch_float_bit (gdbarch
, 32);
3347 set_gdbarch_double_bit (gdbarch
, 64);
3348 set_gdbarch_long_double_bit (gdbarch
, 128);
3349 set_gdbarch_long_bit (gdbarch
, 64);
3350 set_gdbarch_long_long_bit (gdbarch
, 64);
3351 set_gdbarch_ptr_bit (gdbarch
, 64);
3352 set_gdbarch_char_signed (gdbarch
, 0);
3353 set_gdbarch_wchar_signed (gdbarch
, 0);
3354 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3355 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3356 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
3358 /* Internal <-> external register number maps. */
3359 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, aarch64_dwarf_reg_to_regnum
);
3361 /* Returning results. */
3362 set_gdbarch_return_value (gdbarch
, aarch64_return_value
);
3365 set_gdbarch_print_insn (gdbarch
, aarch64_gdb_print_insn
);
3367 /* Virtual tables. */
3368 set_gdbarch_vbit_in_delta (gdbarch
, 1);
3370 /* Register architecture. */
3371 aarch64_add_reggroups (gdbarch
);
3373 /* Hook in the ABI-specific overrides, if they have been registered. */
3374 info
.target_desc
= tdesc
;
3375 info
.tdesc_data
= tdesc_data
;
3376 gdbarch_init_osabi (info
, gdbarch
);
3378 dwarf2_frame_set_init_reg (gdbarch
, aarch64_dwarf2_frame_init_reg
);
3379 /* Register DWARF CFA vendor handler. */
3380 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch
,
3381 aarch64_execute_dwarf_cfa_vendor_op
);
3383 /* Add some default predicates. */
3384 frame_unwind_append_unwinder (gdbarch
, &aarch64_stub_unwind
);
3385 dwarf2_append_unwinders (gdbarch
);
3386 frame_unwind_append_unwinder (gdbarch
, &aarch64_prologue_unwind
);
3388 frame_base_set_default (gdbarch
, &aarch64_normal_base
);
3390 /* Now we have tuned the configuration, set a few final things,
3391 based on what the OS ABI has told us. */
3393 if (tdep
->jb_pc
>= 0)
3394 set_gdbarch_get_longjmp_target (gdbarch
, aarch64_get_longjmp_target
);
3396 set_gdbarch_gen_return_address (gdbarch
, aarch64_gen_return_address
);
3398 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
3400 /* Add standard register aliases. */
3401 for (i
= 0; i
< ARRAY_SIZE (aarch64_register_aliases
); i
++)
3402 user_reg_add (gdbarch
, aarch64_register_aliases
[i
].name
,
3403 value_of_aarch64_user_reg
,
3404 &aarch64_register_aliases
[i
].regnum
);
3406 register_aarch64_ravenscar_ops (gdbarch
);
3412 aarch64_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3414 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3419 fprintf_unfiltered (file
, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3420 paddress (gdbarch
, tdep
->lowest_pc
));
3426 static void aarch64_process_record_test (void);
3431 _initialize_aarch64_tdep (void)
3433 gdbarch_register (bfd_arch_aarch64
, aarch64_gdbarch_init
,
3436 /* Debug this file's internals. */
3437 add_setshow_boolean_cmd ("aarch64", class_maintenance
, &aarch64_debug
, _("\
3438 Set AArch64 debugging."), _("\
3439 Show AArch64 debugging."), _("\
3440 When on, AArch64 specific debugging is enabled."),
3443 &setdebuglist
, &showdebuglist
);
3446 selftests::register_test ("aarch64-analyze-prologue",
3447 selftests::aarch64_analyze_prologue_test
);
3448 selftests::register_test ("aarch64-process-record",
3449 selftests::aarch64_process_record_test
);
3450 selftests::record_xml_tdesc ("aarch64.xml",
3451 aarch64_create_target_description (0, false));
3455 /* AArch64 process record-replay related structures, defines etc. */
3457 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3460 unsigned int reg_len = LENGTH; \
3463 REGS = XNEWVEC (uint32_t, reg_len); \
3464 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3469 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3472 unsigned int mem_len = LENGTH; \
3475 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3476 memcpy(&MEMS->len, &RECORD_BUF[0], \
3477 sizeof(struct aarch64_mem_r) * LENGTH); \
3482 /* AArch64 record/replay structures and enumerations. */
3484 struct aarch64_mem_r
3486 uint64_t len
; /* Record length. */
3487 uint64_t addr
; /* Memory address. */
3490 enum aarch64_record_result
3492 AARCH64_RECORD_SUCCESS
,
3493 AARCH64_RECORD_UNSUPPORTED
,
3494 AARCH64_RECORD_UNKNOWN
3497 typedef struct insn_decode_record_t
3499 struct gdbarch
*gdbarch
;
3500 struct regcache
*regcache
;
3501 CORE_ADDR this_addr
; /* Address of insn to be recorded. */
3502 uint32_t aarch64_insn
; /* Insn to be recorded. */
3503 uint32_t mem_rec_count
; /* Count of memory records. */
3504 uint32_t reg_rec_count
; /* Count of register records. */
3505 uint32_t *aarch64_regs
; /* Registers to be recorded. */
3506 struct aarch64_mem_r
*aarch64_mems
; /* Memory locations to be recorded. */
3507 } insn_decode_record
;
3509 /* Record handler for data processing - register instructions. */
3512 aarch64_record_data_proc_reg (insn_decode_record
*aarch64_insn_r
)
3514 uint8_t reg_rd
, insn_bits24_27
, insn_bits21_23
;
3515 uint32_t record_buf
[4];
3517 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3518 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3519 insn_bits21_23
= bits (aarch64_insn_r
->aarch64_insn
, 21, 23);
3521 if (!bit (aarch64_insn_r
->aarch64_insn
, 28))
3525 /* Logical (shifted register). */
3526 if (insn_bits24_27
== 0x0a)
3527 setflags
= (bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03);
3529 else if (insn_bits24_27
== 0x0b)
3530 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3532 return AARCH64_RECORD_UNKNOWN
;
3534 record_buf
[0] = reg_rd
;
3535 aarch64_insn_r
->reg_rec_count
= 1;
3537 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3541 if (insn_bits24_27
== 0x0b)
3543 /* Data-processing (3 source). */
3544 record_buf
[0] = reg_rd
;
3545 aarch64_insn_r
->reg_rec_count
= 1;
3547 else if (insn_bits24_27
== 0x0a)
3549 if (insn_bits21_23
== 0x00)
3551 /* Add/subtract (with carry). */
3552 record_buf
[0] = reg_rd
;
3553 aarch64_insn_r
->reg_rec_count
= 1;
3554 if (bit (aarch64_insn_r
->aarch64_insn
, 29))
3556 record_buf
[1] = AARCH64_CPSR_REGNUM
;
3557 aarch64_insn_r
->reg_rec_count
= 2;
3560 else if (insn_bits21_23
== 0x02)
3562 /* Conditional compare (register) and conditional compare
3563 (immediate) instructions. */
3564 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3565 aarch64_insn_r
->reg_rec_count
= 1;
3567 else if (insn_bits21_23
== 0x04 || insn_bits21_23
== 0x06)
3569 /* CConditional select. */
3570 /* Data-processing (2 source). */
3571 /* Data-processing (1 source). */
3572 record_buf
[0] = reg_rd
;
3573 aarch64_insn_r
->reg_rec_count
= 1;
3576 return AARCH64_RECORD_UNKNOWN
;
3580 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3582 return AARCH64_RECORD_SUCCESS
;
3585 /* Record handler for data processing - immediate instructions. */
3588 aarch64_record_data_proc_imm (insn_decode_record
*aarch64_insn_r
)
3590 uint8_t reg_rd
, insn_bit23
, insn_bits24_27
, setflags
;
3591 uint32_t record_buf
[4];
3593 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3594 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3595 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3597 if (insn_bits24_27
== 0x00 /* PC rel addressing. */
3598 || insn_bits24_27
== 0x03 /* Bitfield and Extract. */
3599 || (insn_bits24_27
== 0x02 && insn_bit23
)) /* Move wide (immediate). */
3601 record_buf
[0] = reg_rd
;
3602 aarch64_insn_r
->reg_rec_count
= 1;
3604 else if (insn_bits24_27
== 0x01)
3606 /* Add/Subtract (immediate). */
3607 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3608 record_buf
[0] = reg_rd
;
3609 aarch64_insn_r
->reg_rec_count
= 1;
3611 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3613 else if (insn_bits24_27
== 0x02 && !insn_bit23
)
3615 /* Logical (immediate). */
3616 setflags
= bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03;
3617 record_buf
[0] = reg_rd
;
3618 aarch64_insn_r
->reg_rec_count
= 1;
3620 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3623 return AARCH64_RECORD_UNKNOWN
;
3625 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3627 return AARCH64_RECORD_SUCCESS
;
3630 /* Record handler for branch, exception generation and system instructions. */
3633 aarch64_record_branch_except_sys (insn_decode_record
*aarch64_insn_r
)
3635 struct gdbarch_tdep
*tdep
= gdbarch_tdep (aarch64_insn_r
->gdbarch
);
3636 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits22_23
;
3637 uint32_t record_buf
[4];
3639 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3640 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
3641 insn_bits22_23
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3643 if (insn_bits28_31
== 0x0d)
3645 /* Exception generation instructions. */
3646 if (insn_bits24_27
== 0x04)
3648 if (!bits (aarch64_insn_r
->aarch64_insn
, 2, 4)
3649 && !bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
3650 && bits (aarch64_insn_r
->aarch64_insn
, 0, 1) == 0x01)
3652 ULONGEST svc_number
;
3654 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, 8,
3656 return tdep
->aarch64_syscall_record (aarch64_insn_r
->regcache
,
3660 return AARCH64_RECORD_UNSUPPORTED
;
3662 /* System instructions. */
3663 else if (insn_bits24_27
== 0x05 && insn_bits22_23
== 0x00)
3665 uint32_t reg_rt
, reg_crn
;
3667 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3668 reg_crn
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3670 /* Record rt in case of sysl and mrs instructions. */
3671 if (bit (aarch64_insn_r
->aarch64_insn
, 21))
3673 record_buf
[0] = reg_rt
;
3674 aarch64_insn_r
->reg_rec_count
= 1;
3676 /* Record cpsr for hint and msr(immediate) instructions. */
3677 else if (reg_crn
== 0x02 || reg_crn
== 0x04)
3679 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3680 aarch64_insn_r
->reg_rec_count
= 1;
3683 /* Unconditional branch (register). */
3684 else if((insn_bits24_27
& 0x0e) == 0x06)
3686 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3687 if (bits (aarch64_insn_r
->aarch64_insn
, 21, 22) == 0x01)
3688 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3691 return AARCH64_RECORD_UNKNOWN
;
3693 /* Unconditional branch (immediate). */
3694 else if ((insn_bits28_31
& 0x07) == 0x01 && (insn_bits24_27
& 0x0c) == 0x04)
3696 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3697 if (bit (aarch64_insn_r
->aarch64_insn
, 31))
3698 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3701 /* Compare & branch (immediate), Test & branch (immediate) and
3702 Conditional branch (immediate). */
3703 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3705 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3707 return AARCH64_RECORD_SUCCESS
;
3710 /* Record handler for advanced SIMD load and store instructions. */
3713 aarch64_record_asimd_load_store (insn_decode_record
*aarch64_insn_r
)
3716 uint64_t addr_offset
= 0;
3717 uint32_t record_buf
[24];
3718 uint64_t record_buf_mem
[24];
3719 uint32_t reg_rn
, reg_rt
;
3720 uint32_t reg_index
= 0, mem_index
= 0;
3721 uint8_t opcode_bits
, size_bits
;
3723 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3724 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3725 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3726 opcode_bits
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3727 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
, &address
);
3730 debug_printf ("Process record: Advanced SIMD load/store\n");
3732 /* Load/store single structure. */
3733 if (bit (aarch64_insn_r
->aarch64_insn
, 24))
3735 uint8_t sindex
, scale
, selem
, esize
, replicate
= 0;
3736 scale
= opcode_bits
>> 2;
3737 selem
= ((opcode_bits
& 0x02) |
3738 bit (aarch64_insn_r
->aarch64_insn
, 21)) + 1;
3742 if (size_bits
& 0x01)
3743 return AARCH64_RECORD_UNKNOWN
;
3746 if ((size_bits
>> 1) & 0x01)
3747 return AARCH64_RECORD_UNKNOWN
;
3748 if (size_bits
& 0x01)
3750 if (!((opcode_bits
>> 1) & 0x01))
3753 return AARCH64_RECORD_UNKNOWN
;
3757 if (bit (aarch64_insn_r
->aarch64_insn
, 22) && !(opcode_bits
& 0x01))
3764 return AARCH64_RECORD_UNKNOWN
;
3770 for (sindex
= 0; sindex
< selem
; sindex
++)
3772 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3773 reg_rt
= (reg_rt
+ 1) % 32;
3777 for (sindex
= 0; sindex
< selem
; sindex
++)
3779 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3780 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3783 record_buf_mem
[mem_index
++] = esize
/ 8;
3784 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3786 addr_offset
= addr_offset
+ (esize
/ 8);
3787 reg_rt
= (reg_rt
+ 1) % 32;
3791 /* Load/store multiple structure. */
3794 uint8_t selem
, esize
, rpt
, elements
;
3795 uint8_t eindex
, rindex
;
3797 esize
= 8 << size_bits
;
3798 if (bit (aarch64_insn_r
->aarch64_insn
, 30))
3799 elements
= 128 / esize
;
3801 elements
= 64 / esize
;
3803 switch (opcode_bits
)
3805 /*LD/ST4 (4 Registers). */
3810 /*LD/ST1 (4 Registers). */
3815 /*LD/ST3 (3 Registers). */
3820 /*LD/ST1 (3 Registers). */
3825 /*LD/ST1 (1 Register). */
3830 /*LD/ST2 (2 Registers). */
3835 /*LD/ST1 (2 Registers). */
3841 return AARCH64_RECORD_UNSUPPORTED
;
3844 for (rindex
= 0; rindex
< rpt
; rindex
++)
3845 for (eindex
= 0; eindex
< elements
; eindex
++)
3847 uint8_t reg_tt
, sindex
;
3848 reg_tt
= (reg_rt
+ rindex
) % 32;
3849 for (sindex
= 0; sindex
< selem
; sindex
++)
3851 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3852 record_buf
[reg_index
++] = reg_tt
+ AARCH64_V0_REGNUM
;
3855 record_buf_mem
[mem_index
++] = esize
/ 8;
3856 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3858 addr_offset
= addr_offset
+ (esize
/ 8);
3859 reg_tt
= (reg_tt
+ 1) % 32;
3864 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
3865 record_buf
[reg_index
++] = reg_rn
;
3867 aarch64_insn_r
->reg_rec_count
= reg_index
;
3868 aarch64_insn_r
->mem_rec_count
= mem_index
/ 2;
3869 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
3871 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3873 return AARCH64_RECORD_SUCCESS
;
3876 /* Record handler for load and store instructions. */
3879 aarch64_record_load_store (insn_decode_record
*aarch64_insn_r
)
3881 uint8_t insn_bits24_27
, insn_bits28_29
, insn_bits10_11
;
3882 uint8_t insn_bit23
, insn_bit21
;
3883 uint8_t opc
, size_bits
, ld_flag
, vector_flag
;
3884 uint32_t reg_rn
, reg_rt
, reg_rt2
;
3885 uint64_t datasize
, offset
;
3886 uint32_t record_buf
[8];
3887 uint64_t record_buf_mem
[8];
3890 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3891 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3892 insn_bits28_29
= bits (aarch64_insn_r
->aarch64_insn
, 28, 29);
3893 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
3894 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3895 ld_flag
= bit (aarch64_insn_r
->aarch64_insn
, 22);
3896 vector_flag
= bit (aarch64_insn_r
->aarch64_insn
, 26);
3897 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3898 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3899 reg_rt2
= bits (aarch64_insn_r
->aarch64_insn
, 10, 14);
3900 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 30, 31);
3902 /* Load/store exclusive. */
3903 if (insn_bits24_27
== 0x08 && insn_bits28_29
== 0x00)
3906 debug_printf ("Process record: load/store exclusive\n");
3910 record_buf
[0] = reg_rt
;
3911 aarch64_insn_r
->reg_rec_count
= 1;
3914 record_buf
[1] = reg_rt2
;
3915 aarch64_insn_r
->reg_rec_count
= 2;
3921 datasize
= (8 << size_bits
) * 2;
3923 datasize
= (8 << size_bits
);
3924 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3926 record_buf_mem
[0] = datasize
/ 8;
3927 record_buf_mem
[1] = address
;
3928 aarch64_insn_r
->mem_rec_count
= 1;
3931 /* Save register rs. */
3932 record_buf
[0] = bits (aarch64_insn_r
->aarch64_insn
, 16, 20);
3933 aarch64_insn_r
->reg_rec_count
= 1;
3937 /* Load register (literal) instructions decoding. */
3938 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x01)
3941 debug_printf ("Process record: load register (literal)\n");
3943 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3945 record_buf
[0] = reg_rt
;
3946 aarch64_insn_r
->reg_rec_count
= 1;
3948 /* All types of load/store pair instructions decoding. */
3949 else if ((insn_bits24_27
& 0x0a) == 0x08 && insn_bits28_29
== 0x02)
3952 debug_printf ("Process record: load/store pair\n");
3958 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3959 record_buf
[1] = reg_rt2
+ AARCH64_V0_REGNUM
;
3963 record_buf
[0] = reg_rt
;
3964 record_buf
[1] = reg_rt2
;
3966 aarch64_insn_r
->reg_rec_count
= 2;
3971 imm7_off
= bits (aarch64_insn_r
->aarch64_insn
, 15, 21);
3973 size_bits
= size_bits
>> 1;
3974 datasize
= 8 << (2 + size_bits
);
3975 offset
= (imm7_off
& 0x40) ? (~imm7_off
& 0x007f) + 1 : imm7_off
;
3976 offset
= offset
<< (2 + size_bits
);
3977 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3979 if (!((insn_bits24_27
& 0x0b) == 0x08 && insn_bit23
))
3981 if (imm7_off
& 0x40)
3982 address
= address
- offset
;
3984 address
= address
+ offset
;
3987 record_buf_mem
[0] = datasize
/ 8;
3988 record_buf_mem
[1] = address
;
3989 record_buf_mem
[2] = datasize
/ 8;
3990 record_buf_mem
[3] = address
+ (datasize
/ 8);
3991 aarch64_insn_r
->mem_rec_count
= 2;
3993 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
3994 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
3996 /* Load/store register (unsigned immediate) instructions. */
3997 else if ((insn_bits24_27
& 0x0b) == 0x09 && insn_bits28_29
== 0x03)
3999 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4009 if (size_bits
== 0x3 && vector_flag
== 0x0 && opc
== 0x2)
4011 /* PRFM (immediate) */
4012 return AARCH64_RECORD_SUCCESS
;
4014 else if (size_bits
== 0x2 && vector_flag
== 0x0 && opc
== 0x2)
4016 /* LDRSW (immediate) */
4030 debug_printf ("Process record: load/store (unsigned immediate):"
4031 " size %x V %d opc %x\n", size_bits
, vector_flag
,
4037 offset
= bits (aarch64_insn_r
->aarch64_insn
, 10, 21);
4038 datasize
= 8 << size_bits
;
4039 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4041 offset
= offset
<< size_bits
;
4042 address
= address
+ offset
;
4044 record_buf_mem
[0] = datasize
>> 3;
4045 record_buf_mem
[1] = address
;
4046 aarch64_insn_r
->mem_rec_count
= 1;
4051 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4053 record_buf
[0] = reg_rt
;
4054 aarch64_insn_r
->reg_rec_count
= 1;
4057 /* Load/store register (register offset) instructions. */
4058 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
4059 && insn_bits10_11
== 0x02 && insn_bit21
)
4062 debug_printf ("Process record: load/store (register offset)\n");
4063 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4070 if (size_bits
!= 0x03)
4073 return AARCH64_RECORD_UNKNOWN
;
4077 ULONGEST reg_rm_val
;
4079 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
,
4080 bits (aarch64_insn_r
->aarch64_insn
, 16, 20), ®_rm_val
);
4081 if (bit (aarch64_insn_r
->aarch64_insn
, 12))
4082 offset
= reg_rm_val
<< size_bits
;
4084 offset
= reg_rm_val
;
4085 datasize
= 8 << size_bits
;
4086 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4088 address
= address
+ offset
;
4089 record_buf_mem
[0] = datasize
>> 3;
4090 record_buf_mem
[1] = address
;
4091 aarch64_insn_r
->mem_rec_count
= 1;
4096 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4098 record_buf
[0] = reg_rt
;
4099 aarch64_insn_r
->reg_rec_count
= 1;
4102 /* Load/store register (immediate and unprivileged) instructions. */
4103 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
4108 debug_printf ("Process record: load/store "
4109 "(immediate and unprivileged)\n");
4111 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4118 if (size_bits
!= 0x03)
4121 return AARCH64_RECORD_UNKNOWN
;
4126 imm9_off
= bits (aarch64_insn_r
->aarch64_insn
, 12, 20);
4127 offset
= (imm9_off
& 0x0100) ? (((~imm9_off
) & 0x01ff) + 1) : imm9_off
;
4128 datasize
= 8 << size_bits
;
4129 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4131 if (insn_bits10_11
!= 0x01)
4133 if (imm9_off
& 0x0100)
4134 address
= address
- offset
;
4136 address
= address
+ offset
;
4138 record_buf_mem
[0] = datasize
>> 3;
4139 record_buf_mem
[1] = address
;
4140 aarch64_insn_r
->mem_rec_count
= 1;
4145 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4147 record_buf
[0] = reg_rt
;
4148 aarch64_insn_r
->reg_rec_count
= 1;
4150 if (insn_bits10_11
== 0x01 || insn_bits10_11
== 0x03)
4151 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
4153 /* Advanced SIMD load/store instructions. */
4155 return aarch64_record_asimd_load_store (aarch64_insn_r
);
4157 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
4159 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4161 return AARCH64_RECORD_SUCCESS
;
4164 /* Record handler for data processing SIMD and floating point instructions. */
4167 aarch64_record_data_proc_simd_fp (insn_decode_record
*aarch64_insn_r
)
4169 uint8_t insn_bit21
, opcode
, rmode
, reg_rd
;
4170 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits10_11
, insn_bits12_15
;
4171 uint8_t insn_bits11_14
;
4172 uint32_t record_buf
[2];
4174 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
4175 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
4176 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
4177 insn_bits12_15
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
4178 insn_bits11_14
= bits (aarch64_insn_r
->aarch64_insn
, 11, 14);
4179 opcode
= bits (aarch64_insn_r
->aarch64_insn
, 16, 18);
4180 rmode
= bits (aarch64_insn_r
->aarch64_insn
, 19, 20);
4181 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
4182 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
4185 debug_printf ("Process record: data processing SIMD/FP: ");
4187 if ((insn_bits28_31
& 0x05) == 0x01 && insn_bits24_27
== 0x0e)
4189 /* Floating point - fixed point conversion instructions. */
4193 debug_printf ("FP - fixed point conversion");
4195 if ((opcode
>> 1) == 0x0 && rmode
== 0x03)
4196 record_buf
[0] = reg_rd
;
4198 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4200 /* Floating point - conditional compare instructions. */
4201 else if (insn_bits10_11
== 0x01)
4204 debug_printf ("FP - conditional compare");
4206 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4208 /* Floating point - data processing (2-source) and
4209 conditional select instructions. */
4210 else if (insn_bits10_11
== 0x02 || insn_bits10_11
== 0x03)
4213 debug_printf ("FP - DP (2-source)");
4215 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4217 else if (insn_bits10_11
== 0x00)
4219 /* Floating point - immediate instructions. */
4220 if ((insn_bits12_15
& 0x01) == 0x01
4221 || (insn_bits12_15
& 0x07) == 0x04)
4224 debug_printf ("FP - immediate");
4225 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4227 /* Floating point - compare instructions. */
4228 else if ((insn_bits12_15
& 0x03) == 0x02)
4231 debug_printf ("FP - immediate");
4232 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4234 /* Floating point - integer conversions instructions. */
4235 else if (insn_bits12_15
== 0x00)
4237 /* Convert float to integer instruction. */
4238 if (!(opcode
>> 1) || ((opcode
>> 1) == 0x02 && !rmode
))
4241 debug_printf ("float to int conversion");
4243 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4245 /* Convert integer to float instruction. */
4246 else if ((opcode
>> 1) == 0x01 && !rmode
)
4249 debug_printf ("int to float conversion");
4251 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4253 /* Move float to integer instruction. */
4254 else if ((opcode
>> 1) == 0x03)
4257 debug_printf ("move float to int");
4259 if (!(opcode
& 0x01))
4260 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4262 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4265 return AARCH64_RECORD_UNKNOWN
;
4268 return AARCH64_RECORD_UNKNOWN
;
4271 return AARCH64_RECORD_UNKNOWN
;
4273 else if ((insn_bits28_31
& 0x09) == 0x00 && insn_bits24_27
== 0x0e)
4276 debug_printf ("SIMD copy");
4278 /* Advanced SIMD copy instructions. */
4279 if (!bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
4280 && !bit (aarch64_insn_r
->aarch64_insn
, 15)
4281 && bit (aarch64_insn_r
->aarch64_insn
, 10))
4283 if (insn_bits11_14
== 0x05 || insn_bits11_14
== 0x07)
4284 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4286 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4289 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4291 /* All remaining floating point or advanced SIMD instructions. */
4295 debug_printf ("all remain");
4297 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4301 debug_printf ("\n");
4303 aarch64_insn_r
->reg_rec_count
++;
4304 gdb_assert (aarch64_insn_r
->reg_rec_count
== 1);
4305 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4307 return AARCH64_RECORD_SUCCESS
;
4310 /* Decodes insns type and invokes its record handler. */
4313 aarch64_record_decode_insn_handler (insn_decode_record
*aarch64_insn_r
)
4315 uint32_t ins_bit25
, ins_bit26
, ins_bit27
, ins_bit28
;
4317 ins_bit25
= bit (aarch64_insn_r
->aarch64_insn
, 25);
4318 ins_bit26
= bit (aarch64_insn_r
->aarch64_insn
, 26);
4319 ins_bit27
= bit (aarch64_insn_r
->aarch64_insn
, 27);
4320 ins_bit28
= bit (aarch64_insn_r
->aarch64_insn
, 28);
4322 /* Data processing - immediate instructions. */
4323 if (!ins_bit26
&& !ins_bit27
&& ins_bit28
)
4324 return aarch64_record_data_proc_imm (aarch64_insn_r
);
4326 /* Branch, exception generation and system instructions. */
4327 if (ins_bit26
&& !ins_bit27
&& ins_bit28
)
4328 return aarch64_record_branch_except_sys (aarch64_insn_r
);
4330 /* Load and store instructions. */
4331 if (!ins_bit25
&& ins_bit27
)
4332 return aarch64_record_load_store (aarch64_insn_r
);
4334 /* Data processing - register instructions. */
4335 if (ins_bit25
&& !ins_bit26
&& ins_bit27
)
4336 return aarch64_record_data_proc_reg (aarch64_insn_r
);
4338 /* Data processing - SIMD and floating point instructions. */
4339 if (ins_bit25
&& ins_bit26
&& ins_bit27
)
4340 return aarch64_record_data_proc_simd_fp (aarch64_insn_r
);
4342 return AARCH64_RECORD_UNSUPPORTED
;
4345 /* Cleans up local record registers and memory allocations. */
4348 deallocate_reg_mem (insn_decode_record
*record
)
4350 xfree (record
->aarch64_regs
);
4351 xfree (record
->aarch64_mems
);
4355 namespace selftests
{
4358 aarch64_process_record_test (void)
4360 struct gdbarch_info info
;
4363 gdbarch_info_init (&info
);
4364 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
4366 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
4367 SELF_CHECK (gdbarch
!= NULL
);
4369 insn_decode_record aarch64_record
;
4371 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4372 aarch64_record
.regcache
= NULL
;
4373 aarch64_record
.this_addr
= 0;
4374 aarch64_record
.gdbarch
= gdbarch
;
4376 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4377 aarch64_record
.aarch64_insn
= 0xf9800020;
4378 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4379 SELF_CHECK (ret
== AARCH64_RECORD_SUCCESS
);
4380 SELF_CHECK (aarch64_record
.reg_rec_count
== 0);
4381 SELF_CHECK (aarch64_record
.mem_rec_count
== 0);
4383 deallocate_reg_mem (&aarch64_record
);
4386 } // namespace selftests
4387 #endif /* GDB_SELF_TEST */
4389 /* Parse the current instruction and record the values of the registers and
4390 memory that will be changed in current instruction to record_arch_list
4391 return -1 if something is wrong. */
4394 aarch64_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4395 CORE_ADDR insn_addr
)
4397 uint32_t rec_no
= 0;
4398 uint8_t insn_size
= 4;
4400 gdb_byte buf
[insn_size
];
4401 insn_decode_record aarch64_record
;
4403 memset (&buf
[0], 0, insn_size
);
4404 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4405 target_read_memory (insn_addr
, &buf
[0], insn_size
);
4406 aarch64_record
.aarch64_insn
4407 = (uint32_t) extract_unsigned_integer (&buf
[0],
4409 gdbarch_byte_order (gdbarch
));
4410 aarch64_record
.regcache
= regcache
;
4411 aarch64_record
.this_addr
= insn_addr
;
4412 aarch64_record
.gdbarch
= gdbarch
;
4414 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4415 if (ret
== AARCH64_RECORD_UNSUPPORTED
)
4417 printf_unfiltered (_("Process record does not support instruction "
4418 "0x%0x at address %s.\n"),
4419 aarch64_record
.aarch64_insn
,
4420 paddress (gdbarch
, insn_addr
));
4426 /* Record registers. */
4427 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4429 /* Always record register CPSR. */
4430 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4431 AARCH64_CPSR_REGNUM
);
4432 if (aarch64_record
.aarch64_regs
)
4433 for (rec_no
= 0; rec_no
< aarch64_record
.reg_rec_count
; rec_no
++)
4434 if (record_full_arch_list_add_reg (aarch64_record
.regcache
,
4435 aarch64_record
.aarch64_regs
[rec_no
]))
4438 /* Record memories. */
4439 if (aarch64_record
.aarch64_mems
)
4440 for (rec_no
= 0; rec_no
< aarch64_record
.mem_rec_count
; rec_no
++)
4441 if (record_full_arch_list_add_mem
4442 ((CORE_ADDR
)aarch64_record
.aarch64_mems
[rec_no
].addr
,
4443 aarch64_record
.aarch64_mems
[rec_no
].len
))
4446 if (record_full_arch_list_add_end ())
4450 deallocate_reg_mem (&aarch64_record
);