1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2020 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
28 #include "reggroups.h"
30 #include "arch-utils.h"
32 #include "frame-unwind.h"
33 #include "frame-base.h"
34 #include "trad-frame.h"
37 #include "dwarf2-frame.h"
39 #include "prologue-value.h"
40 #include "target-descriptions.h"
41 #include "user-regs.h"
43 #include "gdbsupport/selftest.h"
45 #include "aarch64-tdep.h"
46 #include "aarch64-ravenscar-thread.h"
49 #include "record-full.h"
50 #include "arch/aarch64-insn.h"
53 #include "opcode/aarch64.h"
56 #define submask(x) ((1L << ((x) + 1)) - 1)
57 #define bit(obj,st) (((obj) >> (st)) & 1)
58 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
60 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
62 #define HA_MAX_NUM_FLDS 4
64 /* All possible aarch64 target descriptors. */
65 struct target_desc
*tdesc_aarch64_list
[AARCH64_MAX_SVE_VQ
+ 1][2/*pauth*/];
67 /* The standard register names, and all the valid aliases for them. */
70 const char *const name
;
72 } aarch64_register_aliases
[] =
74 /* 64-bit register names. */
75 {"fp", AARCH64_FP_REGNUM
},
76 {"lr", AARCH64_LR_REGNUM
},
77 {"sp", AARCH64_SP_REGNUM
},
79 /* 32-bit register names. */
80 {"w0", AARCH64_X0_REGNUM
+ 0},
81 {"w1", AARCH64_X0_REGNUM
+ 1},
82 {"w2", AARCH64_X0_REGNUM
+ 2},
83 {"w3", AARCH64_X0_REGNUM
+ 3},
84 {"w4", AARCH64_X0_REGNUM
+ 4},
85 {"w5", AARCH64_X0_REGNUM
+ 5},
86 {"w6", AARCH64_X0_REGNUM
+ 6},
87 {"w7", AARCH64_X0_REGNUM
+ 7},
88 {"w8", AARCH64_X0_REGNUM
+ 8},
89 {"w9", AARCH64_X0_REGNUM
+ 9},
90 {"w10", AARCH64_X0_REGNUM
+ 10},
91 {"w11", AARCH64_X0_REGNUM
+ 11},
92 {"w12", AARCH64_X0_REGNUM
+ 12},
93 {"w13", AARCH64_X0_REGNUM
+ 13},
94 {"w14", AARCH64_X0_REGNUM
+ 14},
95 {"w15", AARCH64_X0_REGNUM
+ 15},
96 {"w16", AARCH64_X0_REGNUM
+ 16},
97 {"w17", AARCH64_X0_REGNUM
+ 17},
98 {"w18", AARCH64_X0_REGNUM
+ 18},
99 {"w19", AARCH64_X0_REGNUM
+ 19},
100 {"w20", AARCH64_X0_REGNUM
+ 20},
101 {"w21", AARCH64_X0_REGNUM
+ 21},
102 {"w22", AARCH64_X0_REGNUM
+ 22},
103 {"w23", AARCH64_X0_REGNUM
+ 23},
104 {"w24", AARCH64_X0_REGNUM
+ 24},
105 {"w25", AARCH64_X0_REGNUM
+ 25},
106 {"w26", AARCH64_X0_REGNUM
+ 26},
107 {"w27", AARCH64_X0_REGNUM
+ 27},
108 {"w28", AARCH64_X0_REGNUM
+ 28},
109 {"w29", AARCH64_X0_REGNUM
+ 29},
110 {"w30", AARCH64_X0_REGNUM
+ 30},
113 {"ip0", AARCH64_X0_REGNUM
+ 16},
114 {"ip1", AARCH64_X0_REGNUM
+ 17}
117 /* The required core 'R' registers. */
118 static const char *const aarch64_r_register_names
[] =
120 /* These registers must appear in consecutive RAW register number
121 order and they must begin with AARCH64_X0_REGNUM! */
122 "x0", "x1", "x2", "x3",
123 "x4", "x5", "x6", "x7",
124 "x8", "x9", "x10", "x11",
125 "x12", "x13", "x14", "x15",
126 "x16", "x17", "x18", "x19",
127 "x20", "x21", "x22", "x23",
128 "x24", "x25", "x26", "x27",
129 "x28", "x29", "x30", "sp",
133 /* The FP/SIMD 'V' registers. */
134 static const char *const aarch64_v_register_names
[] =
136 /* These registers must appear in consecutive RAW register number
137 order and they must begin with AARCH64_V0_REGNUM! */
138 "v0", "v1", "v2", "v3",
139 "v4", "v5", "v6", "v7",
140 "v8", "v9", "v10", "v11",
141 "v12", "v13", "v14", "v15",
142 "v16", "v17", "v18", "v19",
143 "v20", "v21", "v22", "v23",
144 "v24", "v25", "v26", "v27",
145 "v28", "v29", "v30", "v31",
150 /* The SVE 'Z' and 'P' registers. */
151 static const char *const aarch64_sve_register_names
[] =
153 /* These registers must appear in consecutive RAW register number
154 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
155 "z0", "z1", "z2", "z3",
156 "z4", "z5", "z6", "z7",
157 "z8", "z9", "z10", "z11",
158 "z12", "z13", "z14", "z15",
159 "z16", "z17", "z18", "z19",
160 "z20", "z21", "z22", "z23",
161 "z24", "z25", "z26", "z27",
162 "z28", "z29", "z30", "z31",
164 "p0", "p1", "p2", "p3",
165 "p4", "p5", "p6", "p7",
166 "p8", "p9", "p10", "p11",
167 "p12", "p13", "p14", "p15",
171 static const char *const aarch64_pauth_register_names
[] =
173 /* Authentication mask for data pointer. */
175 /* Authentication mask for code pointer. */
179 /* AArch64 prologue cache structure. */
180 struct aarch64_prologue_cache
182 /* The program counter at the start of the function. It is used to
183 identify this frame as a prologue frame. */
186 /* The program counter at the time this frame was created; i.e. where
187 this function was called from. It is used to identify this frame as a
191 /* The stack pointer at the time this frame was created; i.e. the
192 caller's stack pointer when this function was called. It is used
193 to identify this frame. */
196 /* Is the target available to read from? */
199 /* The frame base for this frame is just prev_sp - frame size.
200 FRAMESIZE is the distance from the frame pointer to the
201 initial stack pointer. */
204 /* The register used to hold the frame pointer for this frame. */
207 /* Saved register offsets. */
208 struct trad_frame_saved_reg
*saved_regs
;
212 show_aarch64_debug (struct ui_file
*file
, int from_tty
,
213 struct cmd_list_element
*c
, const char *value
)
215 fprintf_filtered (file
, _("AArch64 debugging is %s.\n"), value
);
220 /* Abstract instruction reader. */
222 class abstract_instruction_reader
225 /* Read in one instruction. */
226 virtual ULONGEST
read (CORE_ADDR memaddr
, int len
,
227 enum bfd_endian byte_order
) = 0;
230 /* Instruction reader from real target. */
232 class instruction_reader
: public abstract_instruction_reader
235 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
238 return read_code_unsigned_integer (memaddr
, len
, byte_order
);
244 /* If address signing is enabled, mask off the signature bits from the link
245 register, which is passed by value in ADDR, using the register values in
249 aarch64_frame_unmask_lr (struct gdbarch_tdep
*tdep
,
250 struct frame_info
*this_frame
, CORE_ADDR addr
)
252 if (tdep
->has_pauth ()
253 && frame_unwind_register_unsigned (this_frame
,
254 tdep
->pauth_ra_state_regnum
))
256 int cmask_num
= AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
);
257 CORE_ADDR cmask
= frame_unwind_register_unsigned (this_frame
, cmask_num
);
258 addr
= addr
& ~cmask
;
260 /* Record in the frame that the link register required unmasking. */
261 set_frame_previous_pc_masked (this_frame
);
267 /* Implement the "get_pc_address_flags" gdbarch method. */
270 aarch64_get_pc_address_flags (frame_info
*frame
, CORE_ADDR pc
)
272 if (pc
!= 0 && get_frame_pc_masked (frame
))
278 /* Analyze a prologue, looking for a recognizable stack frame
279 and frame pointer. Scan until we encounter a store that could
280 clobber the stack frame unexpectedly, or an unknown instruction. */
283 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
284 CORE_ADDR start
, CORE_ADDR limit
,
285 struct aarch64_prologue_cache
*cache
,
286 abstract_instruction_reader
& reader
)
288 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
290 /* Track X registers and D registers in prologue. */
291 pv_t regs
[AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
];
293 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
; i
++)
294 regs
[i
] = pv_register (i
, 0);
295 pv_area
stack (AARCH64_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
297 for (; start
< limit
; start
+= 4)
302 insn
= reader
.read (start
, 4, byte_order_for_code
);
304 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
307 if (inst
.opcode
->iclass
== addsub_imm
308 && (inst
.opcode
->op
== OP_ADD
309 || strcmp ("sub", inst
.opcode
->name
) == 0))
311 unsigned rd
= inst
.operands
[0].reg
.regno
;
312 unsigned rn
= inst
.operands
[1].reg
.regno
;
314 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 3);
315 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd_SP
);
316 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn_SP
);
317 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_AIMM
);
319 if (inst
.opcode
->op
== OP_ADD
)
321 regs
[rd
] = pv_add_constant (regs
[rn
],
322 inst
.operands
[2].imm
.value
);
326 regs
[rd
] = pv_add_constant (regs
[rn
],
327 -inst
.operands
[2].imm
.value
);
330 else if (inst
.opcode
->iclass
== pcreladdr
331 && inst
.operands
[1].type
== AARCH64_OPND_ADDR_ADRP
)
333 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
334 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
336 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
338 else if (inst
.opcode
->iclass
== branch_imm
)
340 /* Stop analysis on branch. */
343 else if (inst
.opcode
->iclass
== condbranch
)
345 /* Stop analysis on branch. */
348 else if (inst
.opcode
->iclass
== branch_reg
)
350 /* Stop analysis on branch. */
353 else if (inst
.opcode
->iclass
== compbranch
)
355 /* Stop analysis on branch. */
358 else if (inst
.opcode
->op
== OP_MOVZ
)
360 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
361 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
363 else if (inst
.opcode
->iclass
== log_shift
364 && strcmp (inst
.opcode
->name
, "orr") == 0)
366 unsigned rd
= inst
.operands
[0].reg
.regno
;
367 unsigned rn
= inst
.operands
[1].reg
.regno
;
368 unsigned rm
= inst
.operands
[2].reg
.regno
;
370 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
371 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn
);
372 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_Rm_SFT
);
374 if (inst
.operands
[2].shifter
.amount
== 0
375 && rn
== AARCH64_SP_REGNUM
)
381 debug_printf ("aarch64: prologue analysis gave up "
382 "addr=%s opcode=0x%x (orr x register)\n",
383 core_addr_to_string_nz (start
), insn
);
388 else if (inst
.opcode
->op
== OP_STUR
)
390 unsigned rt
= inst
.operands
[0].reg
.regno
;
391 unsigned rn
= inst
.operands
[1].addr
.base_regno
;
392 int size
= aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
);
394 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
395 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
);
396 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_ADDR_SIMM9
);
397 gdb_assert (!inst
.operands
[1].addr
.offset
.is_reg
);
400 (pv_add_constant (regs
[rn
], inst
.operands
[1].addr
.offset
.imm
),
403 else if ((inst
.opcode
->iclass
== ldstpair_off
404 || (inst
.opcode
->iclass
== ldstpair_indexed
405 && inst
.operands
[2].addr
.preind
))
406 && strcmp ("stp", inst
.opcode
->name
) == 0)
408 /* STP with addressing mode Pre-indexed and Base register. */
411 unsigned rn
= inst
.operands
[2].addr
.base_regno
;
412 int32_t imm
= inst
.operands
[2].addr
.offset
.imm
;
413 int size
= aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
);
415 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
416 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
417 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rt2
418 || inst
.operands
[1].type
== AARCH64_OPND_Ft2
);
419 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_ADDR_SIMM7
);
420 gdb_assert (!inst
.operands
[2].addr
.offset
.is_reg
);
422 /* If recording this store would invalidate the store area
423 (perhaps because rn is not known) then we should abandon
424 further prologue analysis. */
425 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
)))
428 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
+ 8)))
431 rt1
= inst
.operands
[0].reg
.regno
;
432 rt2
= inst
.operands
[1].reg
.regno
;
433 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
435 rt1
+= AARCH64_X_REGISTER_COUNT
;
436 rt2
+= AARCH64_X_REGISTER_COUNT
;
439 stack
.store (pv_add_constant (regs
[rn
], imm
), size
, regs
[rt1
]);
440 stack
.store (pv_add_constant (regs
[rn
], imm
+ size
), size
, regs
[rt2
]);
442 if (inst
.operands
[2].addr
.writeback
)
443 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
446 else if ((inst
.opcode
->iclass
== ldst_imm9
/* Signed immediate. */
447 || (inst
.opcode
->iclass
== ldst_pos
/* Unsigned immediate. */
448 && (inst
.opcode
->op
== OP_STR_POS
449 || inst
.opcode
->op
== OP_STRF_POS
)))
450 && inst
.operands
[1].addr
.base_regno
== AARCH64_SP_REGNUM
451 && strcmp ("str", inst
.opcode
->name
) == 0)
453 /* STR (immediate) */
454 unsigned int rt
= inst
.operands
[0].reg
.regno
;
455 int32_t imm
= inst
.operands
[1].addr
.offset
.imm
;
456 unsigned int rn
= inst
.operands
[1].addr
.base_regno
;
457 int size
= aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
);
458 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
459 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
461 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
462 rt
+= AARCH64_X_REGISTER_COUNT
;
464 stack
.store (pv_add_constant (regs
[rn
], imm
), size
, regs
[rt
]);
465 if (inst
.operands
[1].addr
.writeback
)
466 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
468 else if (inst
.opcode
->iclass
== testbranch
)
470 /* Stop analysis on branch. */
473 else if (inst
.opcode
->iclass
== ic_system
)
475 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
476 int ra_state_val
= 0;
478 if (insn
== 0xd503233f /* paciasp. */
479 || insn
== 0xd503237f /* pacibsp. */)
481 /* Return addresses are mangled. */
484 else if (insn
== 0xd50323bf /* autiasp. */
485 || insn
== 0xd50323ff /* autibsp. */)
487 /* Return addresses are not mangled. */
493 debug_printf ("aarch64: prologue analysis gave up addr=%s"
494 " opcode=0x%x (iclass)\n",
495 core_addr_to_string_nz (start
), insn
);
499 if (tdep
->has_pauth () && cache
!= nullptr)
500 trad_frame_set_value (cache
->saved_regs
,
501 tdep
->pauth_ra_state_regnum
,
508 debug_printf ("aarch64: prologue analysis gave up addr=%s"
510 core_addr_to_string_nz (start
), insn
);
519 if (pv_is_register (regs
[AARCH64_FP_REGNUM
], AARCH64_SP_REGNUM
))
521 /* Frame pointer is fp. Frame size is constant. */
522 cache
->framereg
= AARCH64_FP_REGNUM
;
523 cache
->framesize
= -regs
[AARCH64_FP_REGNUM
].k
;
525 else if (pv_is_register (regs
[AARCH64_SP_REGNUM
], AARCH64_SP_REGNUM
))
527 /* Try the stack pointer. */
528 cache
->framesize
= -regs
[AARCH64_SP_REGNUM
].k
;
529 cache
->framereg
= AARCH64_SP_REGNUM
;
533 /* We're just out of luck. We don't know where the frame is. */
534 cache
->framereg
= -1;
535 cache
->framesize
= 0;
538 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
542 if (stack
.find_reg (gdbarch
, i
, &offset
))
543 cache
->saved_regs
[i
].addr
= offset
;
546 for (i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
548 int regnum
= gdbarch_num_regs (gdbarch
);
551 if (stack
.find_reg (gdbarch
, i
+ AARCH64_X_REGISTER_COUNT
,
553 cache
->saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
= offset
;
560 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
561 CORE_ADDR start
, CORE_ADDR limit
,
562 struct aarch64_prologue_cache
*cache
)
564 instruction_reader reader
;
566 return aarch64_analyze_prologue (gdbarch
, start
, limit
, cache
,
572 namespace selftests
{
574 /* Instruction reader from manually cooked instruction sequences. */
576 class instruction_reader_test
: public abstract_instruction_reader
579 template<size_t SIZE
>
580 explicit instruction_reader_test (const uint32_t (&insns
)[SIZE
])
581 : m_insns (insns
), m_insns_size (SIZE
)
584 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
587 SELF_CHECK (len
== 4);
588 SELF_CHECK (memaddr
% 4 == 0);
589 SELF_CHECK (memaddr
/ 4 < m_insns_size
);
591 return m_insns
[memaddr
/ 4];
595 const uint32_t *m_insns
;
600 aarch64_analyze_prologue_test (void)
602 struct gdbarch_info info
;
604 gdbarch_info_init (&info
);
605 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
607 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
608 SELF_CHECK (gdbarch
!= NULL
);
610 struct aarch64_prologue_cache cache
;
611 cache
.saved_regs
= trad_frame_alloc_saved_regs (gdbarch
);
613 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
615 /* Test the simple prologue in which frame pointer is used. */
617 static const uint32_t insns
[] = {
618 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
619 0x910003fd, /* mov x29, sp */
620 0x97ffffe6, /* bl 0x400580 */
622 instruction_reader_test
reader (insns
);
624 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
625 SELF_CHECK (end
== 4 * 2);
627 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
628 SELF_CHECK (cache
.framesize
== 272);
630 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
632 if (i
== AARCH64_FP_REGNUM
)
633 SELF_CHECK (cache
.saved_regs
[i
].addr
== -272);
634 else if (i
== AARCH64_LR_REGNUM
)
635 SELF_CHECK (cache
.saved_regs
[i
].addr
== -264);
637 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
640 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
642 int regnum
= gdbarch_num_regs (gdbarch
);
644 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
649 /* Test a prologue in which STR is used and frame pointer is not
652 static const uint32_t insns
[] = {
653 0xf81d0ff3, /* str x19, [sp, #-48]! */
654 0xb9002fe0, /* str w0, [sp, #44] */
655 0xf90013e1, /* str x1, [sp, #32]*/
656 0xfd000fe0, /* str d0, [sp, #24] */
657 0xaa0203f3, /* mov x19, x2 */
658 0xf94013e0, /* ldr x0, [sp, #32] */
660 instruction_reader_test
reader (insns
);
662 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
663 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
665 SELF_CHECK (end
== 4 * 5);
667 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
668 SELF_CHECK (cache
.framesize
== 48);
670 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
673 SELF_CHECK (cache
.saved_regs
[i
].addr
== -16);
675 SELF_CHECK (cache
.saved_regs
[i
].addr
== -48);
677 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
680 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
682 int regnum
= gdbarch_num_regs (gdbarch
);
685 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
688 SELF_CHECK (cache
.saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].addr
693 /* Test a prologue in which there is a return address signing instruction. */
694 if (tdep
->has_pauth ())
696 static const uint32_t insns
[] = {
697 0xd503233f, /* paciasp */
698 0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */
699 0x910003fd, /* mov x29, sp */
700 0xf801c3f3, /* str x19, [sp, #28] */
701 0xb9401fa0, /* ldr x19, [x29, #28] */
703 instruction_reader_test
reader (insns
);
705 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
706 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
,
709 SELF_CHECK (end
== 4 * 4);
710 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
711 SELF_CHECK (cache
.framesize
== 48);
713 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
716 SELF_CHECK (cache
.saved_regs
[i
].addr
== -20);
717 else if (i
== AARCH64_FP_REGNUM
)
718 SELF_CHECK (cache
.saved_regs
[i
].addr
== -48);
719 else if (i
== AARCH64_LR_REGNUM
)
720 SELF_CHECK (cache
.saved_regs
[i
].addr
== -40);
722 SELF_CHECK (cache
.saved_regs
[i
].addr
== -1);
725 if (tdep
->has_pauth ())
727 SELF_CHECK (trad_frame_value_p (cache
.saved_regs
,
728 tdep
->pauth_ra_state_regnum
));
729 SELF_CHECK (cache
.saved_regs
[tdep
->pauth_ra_state_regnum
].addr
== 1);
733 } // namespace selftests
734 #endif /* GDB_SELF_TEST */
736 /* Implement the "skip_prologue" gdbarch method. */
739 aarch64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
741 CORE_ADDR func_addr
, limit_pc
;
743 /* See if we can determine the end of the prologue via the symbol
744 table. If so, then return either PC, or the PC after the
745 prologue, whichever is greater. */
746 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
748 CORE_ADDR post_prologue_pc
749 = skip_prologue_using_sal (gdbarch
, func_addr
);
751 if (post_prologue_pc
!= 0)
752 return std::max (pc
, post_prologue_pc
);
755 /* Can't determine prologue from the symbol table, need to examine
758 /* Find an upper limit on the function prologue using the debug
759 information. If the debug information could not be used to
760 provide that bound, then use an arbitrary large number as the
762 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
764 limit_pc
= pc
+ 128; /* Magic. */
766 /* Try disassembling prologue. */
767 return aarch64_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
770 /* Scan the function prologue for THIS_FRAME and populate the prologue
774 aarch64_scan_prologue (struct frame_info
*this_frame
,
775 struct aarch64_prologue_cache
*cache
)
777 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
778 CORE_ADDR prologue_start
;
779 CORE_ADDR prologue_end
;
780 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
781 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
783 cache
->prev_pc
= prev_pc
;
785 /* Assume we do not find a frame. */
786 cache
->framereg
= -1;
787 cache
->framesize
= 0;
789 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
792 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
796 /* No line info so use the current PC. */
797 prologue_end
= prev_pc
;
799 else if (sal
.end
< prologue_end
)
801 /* The next line begins after the function end. */
802 prologue_end
= sal
.end
;
805 prologue_end
= std::min (prologue_end
, prev_pc
);
806 aarch64_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
812 frame_loc
= get_frame_register_unsigned (this_frame
, AARCH64_FP_REGNUM
);
816 cache
->framereg
= AARCH64_FP_REGNUM
;
817 cache
->framesize
= 16;
818 cache
->saved_regs
[29].addr
= 0;
819 cache
->saved_regs
[30].addr
= 8;
823 /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
824 function may throw an exception if the inferior's registers or memory is
828 aarch64_make_prologue_cache_1 (struct frame_info
*this_frame
,
829 struct aarch64_prologue_cache
*cache
)
831 CORE_ADDR unwound_fp
;
834 aarch64_scan_prologue (this_frame
, cache
);
836 if (cache
->framereg
== -1)
839 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
843 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
845 /* Calculate actual addresses of saved registers using offsets
846 determined by aarch64_analyze_prologue. */
847 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
848 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
849 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
851 cache
->func
= get_frame_func (this_frame
);
853 cache
->available_p
= 1;
856 /* Allocate and fill in *THIS_CACHE with information about the prologue of
857 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
858 Return a pointer to the current aarch64_prologue_cache in
861 static struct aarch64_prologue_cache
*
862 aarch64_make_prologue_cache (struct frame_info
*this_frame
, void **this_cache
)
864 struct aarch64_prologue_cache
*cache
;
866 if (*this_cache
!= NULL
)
867 return (struct aarch64_prologue_cache
*) *this_cache
;
869 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
870 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
875 aarch64_make_prologue_cache_1 (this_frame
, cache
);
877 catch (const gdb_exception_error
&ex
)
879 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
886 /* Implement the "stop_reason" frame_unwind method. */
888 static enum unwind_stop_reason
889 aarch64_prologue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
892 struct aarch64_prologue_cache
*cache
893 = aarch64_make_prologue_cache (this_frame
, this_cache
);
895 if (!cache
->available_p
)
896 return UNWIND_UNAVAILABLE
;
898 /* Halt the backtrace at "_start". */
899 if (cache
->prev_pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
900 return UNWIND_OUTERMOST
;
902 /* We've hit a wall, stop. */
903 if (cache
->prev_sp
== 0)
904 return UNWIND_OUTERMOST
;
906 return UNWIND_NO_REASON
;
909 /* Our frame ID for a normal frame is the current function's starting
910 PC and the caller's SP when we were called. */
913 aarch64_prologue_this_id (struct frame_info
*this_frame
,
914 void **this_cache
, struct frame_id
*this_id
)
916 struct aarch64_prologue_cache
*cache
917 = aarch64_make_prologue_cache (this_frame
, this_cache
);
919 if (!cache
->available_p
)
920 *this_id
= frame_id_build_unavailable_stack (cache
->func
);
922 *this_id
= frame_id_build (cache
->prev_sp
, cache
->func
);
925 /* Implement the "prev_register" frame_unwind method. */
927 static struct value
*
928 aarch64_prologue_prev_register (struct frame_info
*this_frame
,
929 void **this_cache
, int prev_regnum
)
931 struct aarch64_prologue_cache
*cache
932 = aarch64_make_prologue_cache (this_frame
, this_cache
);
934 /* If we are asked to unwind the PC, then we need to return the LR
935 instead. The prologue may save PC, but it will point into this
936 frame's prologue, not the next frame's resume location. */
937 if (prev_regnum
== AARCH64_PC_REGNUM
)
940 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
941 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
943 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
945 if (tdep
->has_pauth ()
946 && trad_frame_value_p (cache
->saved_regs
,
947 tdep
->pauth_ra_state_regnum
))
948 lr
= aarch64_frame_unmask_lr (tdep
, this_frame
, lr
);
950 return frame_unwind_got_constant (this_frame
, prev_regnum
, lr
);
953 /* SP is generally not saved to the stack, but this frame is
954 identified by the next frame's stack pointer at the time of the
955 call. The value was already reconstructed into PREV_SP. */
968 if (prev_regnum
== AARCH64_SP_REGNUM
)
969 return frame_unwind_got_constant (this_frame
, prev_regnum
,
972 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
976 /* AArch64 prologue unwinder. */
977 struct frame_unwind aarch64_prologue_unwind
=
980 aarch64_prologue_frame_unwind_stop_reason
,
981 aarch64_prologue_this_id
,
982 aarch64_prologue_prev_register
,
984 default_frame_sniffer
987 /* Allocate and fill in *THIS_CACHE with information about the prologue of
988 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
989 Return a pointer to the current aarch64_prologue_cache in
992 static struct aarch64_prologue_cache
*
993 aarch64_make_stub_cache (struct frame_info
*this_frame
, void **this_cache
)
995 struct aarch64_prologue_cache
*cache
;
997 if (*this_cache
!= NULL
)
998 return (struct aarch64_prologue_cache
*) *this_cache
;
1000 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
1001 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1002 *this_cache
= cache
;
1006 cache
->prev_sp
= get_frame_register_unsigned (this_frame
,
1008 cache
->prev_pc
= get_frame_pc (this_frame
);
1009 cache
->available_p
= 1;
1011 catch (const gdb_exception_error
&ex
)
1013 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
1020 /* Implement the "stop_reason" frame_unwind method. */
1022 static enum unwind_stop_reason
1023 aarch64_stub_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1026 struct aarch64_prologue_cache
*cache
1027 = aarch64_make_stub_cache (this_frame
, this_cache
);
1029 if (!cache
->available_p
)
1030 return UNWIND_UNAVAILABLE
;
1032 return UNWIND_NO_REASON
;
1035 /* Our frame ID for a stub frame is the current SP and LR. */
1038 aarch64_stub_this_id (struct frame_info
*this_frame
,
1039 void **this_cache
, struct frame_id
*this_id
)
1041 struct aarch64_prologue_cache
*cache
1042 = aarch64_make_stub_cache (this_frame
, this_cache
);
1044 if (cache
->available_p
)
1045 *this_id
= frame_id_build (cache
->prev_sp
, cache
->prev_pc
);
1047 *this_id
= frame_id_build_unavailable_stack (cache
->prev_pc
);
1050 /* Implement the "sniffer" frame_unwind method. */
1053 aarch64_stub_unwind_sniffer (const struct frame_unwind
*self
,
1054 struct frame_info
*this_frame
,
1055 void **this_prologue_cache
)
1057 CORE_ADDR addr_in_block
;
1060 addr_in_block
= get_frame_address_in_block (this_frame
);
1061 if (in_plt_section (addr_in_block
)
1062 /* We also use the stub winder if the target memory is unreadable
1063 to avoid having the prologue unwinder trying to read it. */
1064 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1070 /* AArch64 stub unwinder. */
1071 struct frame_unwind aarch64_stub_unwind
=
1074 aarch64_stub_frame_unwind_stop_reason
,
1075 aarch64_stub_this_id
,
1076 aarch64_prologue_prev_register
,
1078 aarch64_stub_unwind_sniffer
1081 /* Return the frame base address of *THIS_FRAME. */
1084 aarch64_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1086 struct aarch64_prologue_cache
*cache
1087 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1089 return cache
->prev_sp
- cache
->framesize
;
1092 /* AArch64 default frame base information. */
1093 struct frame_base aarch64_normal_base
=
1095 &aarch64_prologue_unwind
,
1096 aarch64_normal_frame_base
,
1097 aarch64_normal_frame_base
,
1098 aarch64_normal_frame_base
1101 /* Return the value of the REGNUM register in the previous frame of
1104 static struct value
*
1105 aarch64_dwarf2_prev_register (struct frame_info
*this_frame
,
1106 void **this_cache
, int regnum
)
1108 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1113 case AARCH64_PC_REGNUM
:
1114 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
1115 lr
= aarch64_frame_unmask_lr (tdep
, this_frame
, lr
);
1116 return frame_unwind_got_constant (this_frame
, regnum
, lr
);
1119 internal_error (__FILE__
, __LINE__
,
1120 _("Unexpected register %d"), regnum
);
1124 static const unsigned char op_lit0
= DW_OP_lit0
;
1125 static const unsigned char op_lit1
= DW_OP_lit1
;
1127 /* Implement the "init_reg" dwarf2_frame_ops method. */
1130 aarch64_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1131 struct dwarf2_frame_state_reg
*reg
,
1132 struct frame_info
*this_frame
)
1134 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1138 case AARCH64_PC_REGNUM
:
1139 reg
->how
= DWARF2_FRAME_REG_FN
;
1140 reg
->loc
.fn
= aarch64_dwarf2_prev_register
;
1143 case AARCH64_SP_REGNUM
:
1144 reg
->how
= DWARF2_FRAME_REG_CFA
;
1148 /* Init pauth registers. */
1149 if (tdep
->has_pauth ())
1151 if (regnum
== tdep
->pauth_ra_state_regnum
)
1153 /* Initialize RA_STATE to zero. */
1154 reg
->how
= DWARF2_FRAME_REG_SAVED_VAL_EXP
;
1155 reg
->loc
.exp
.start
= &op_lit0
;
1156 reg
->loc
.exp
.len
= 1;
1159 else if (regnum
== AARCH64_PAUTH_DMASK_REGNUM (tdep
->pauth_reg_base
)
1160 || regnum
== AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
))
1162 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1168 /* Implement the execute_dwarf_cfa_vendor_op method. */
1171 aarch64_execute_dwarf_cfa_vendor_op (struct gdbarch
*gdbarch
, gdb_byte op
,
1172 struct dwarf2_frame_state
*fs
)
1174 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1175 struct dwarf2_frame_state_reg
*ra_state
;
1177 if (op
== DW_CFA_AARCH64_negate_ra_state
)
1179 /* On systems without pauth, treat as a nop. */
1180 if (!tdep
->has_pauth ())
1183 /* Allocate RA_STATE column if it's not allocated yet. */
1184 fs
->regs
.alloc_regs (AARCH64_DWARF_PAUTH_RA_STATE
+ 1);
1186 /* Toggle the status of RA_STATE between 0 and 1. */
1187 ra_state
= &(fs
->regs
.reg
[AARCH64_DWARF_PAUTH_RA_STATE
]);
1188 ra_state
->how
= DWARF2_FRAME_REG_SAVED_VAL_EXP
;
1190 if (ra_state
->loc
.exp
.start
== nullptr
1191 || ra_state
->loc
.exp
.start
== &op_lit0
)
1192 ra_state
->loc
.exp
.start
= &op_lit1
;
1194 ra_state
->loc
.exp
.start
= &op_lit0
;
1196 ra_state
->loc
.exp
.len
= 1;
1204 /* Used for matching BRK instructions for AArch64. */
1205 static constexpr uint32_t BRK_INSN_MASK
= 0xffe0001f;
1206 static constexpr uint32_t BRK_INSN_BASE
= 0xd4200000;
1208 /* Implementation of gdbarch_program_breakpoint_here_p for aarch64. */
1211 aarch64_program_breakpoint_here_p (gdbarch
*gdbarch
, CORE_ADDR address
)
1213 const uint32_t insn_len
= 4;
1214 gdb_byte target_mem
[4];
1216 /* Enable the automatic memory restoration from breakpoints while
1217 we read the memory. Otherwise we may find temporary breakpoints, ones
1218 inserted by GDB, and flag them as permanent breakpoints. */
1219 scoped_restore restore_memory
1220 = make_scoped_restore_show_memory_breakpoints (0);
1222 if (target_read_memory (address
, target_mem
, insn_len
) == 0)
1225 (uint32_t) extract_unsigned_integer (target_mem
, insn_len
,
1226 gdbarch_byte_order_for_code (gdbarch
));
1228 /* Check if INSN is a BRK instruction pattern. There are multiple choices
1229 of such instructions with different immediate values. Different OS'
1230 may use a different variation, but they have the same outcome. */
1231 return ((insn
& BRK_INSN_MASK
) == BRK_INSN_BASE
);
1237 /* When arguments must be pushed onto the stack, they go on in reverse
1238 order. The code below implements a FILO (stack) to do this. */
1242 /* Value to pass on stack. It can be NULL if this item is for stack
1244 const gdb_byte
*data
;
1246 /* Size in bytes of value to pass on stack. */
1250 /* Implement the gdbarch type alignment method, overrides the generic
1251 alignment algorithm for anything that is aarch64 specific. */
1254 aarch64_type_align (gdbarch
*gdbarch
, struct type
*t
)
1256 t
= check_typedef (t
);
1257 if (TYPE_CODE (t
) == TYPE_CODE_ARRAY
&& TYPE_VECTOR (t
))
1259 /* Use the natural alignment for vector types (the same for
1260 scalar type), but the maximum alignment is 128-bit. */
1261 if (TYPE_LENGTH (t
) > 16)
1264 return TYPE_LENGTH (t
);
1267 /* Allow the common code to calculate the alignment. */
1271 /* Worker function for aapcs_is_vfp_call_or_return_candidate.
1273 Return the number of register required, or -1 on failure.
1275 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1276 to the element, else fail if the type of this element does not match the
1280 aapcs_is_vfp_call_or_return_candidate_1 (struct type
*type
,
1281 struct type
**fundamental_type
)
1283 if (type
== nullptr)
1286 switch (TYPE_CODE (type
))
1289 if (TYPE_LENGTH (type
) > 16)
1292 if (*fundamental_type
== nullptr)
1293 *fundamental_type
= type
;
1294 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1295 || TYPE_CODE (type
) != TYPE_CODE (*fundamental_type
))
1300 case TYPE_CODE_COMPLEX
:
1302 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (type
));
1303 if (TYPE_LENGTH (target_type
) > 16)
1306 if (*fundamental_type
== nullptr)
1307 *fundamental_type
= target_type
;
1308 else if (TYPE_LENGTH (target_type
) != TYPE_LENGTH (*fundamental_type
)
1309 || TYPE_CODE (target_type
) != TYPE_CODE (*fundamental_type
))
1315 case TYPE_CODE_ARRAY
:
1317 if (TYPE_VECTOR (type
))
1319 if (TYPE_LENGTH (type
) != 8 && TYPE_LENGTH (type
) != 16)
1322 if (*fundamental_type
== nullptr)
1323 *fundamental_type
= type
;
1324 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1325 || TYPE_CODE (type
) != TYPE_CODE (*fundamental_type
))
1332 struct type
*target_type
= TYPE_TARGET_TYPE (type
);
1333 int count
= aapcs_is_vfp_call_or_return_candidate_1
1334 (target_type
, fundamental_type
);
1339 count
*= (TYPE_LENGTH (type
) / TYPE_LENGTH (target_type
));
1344 case TYPE_CODE_STRUCT
:
1345 case TYPE_CODE_UNION
:
1349 for (int i
= 0; i
< TYPE_NFIELDS (type
); i
++)
1351 /* Ignore any static fields. */
1352 if (field_is_static (&TYPE_FIELD (type
, i
)))
1355 struct type
*member
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
1357 int sub_count
= aapcs_is_vfp_call_or_return_candidate_1
1358 (member
, fundamental_type
);
1359 if (sub_count
== -1)
1364 /* Ensure there is no padding between the fields (allowing for empty
1365 zero length structs) */
1366 int ftype_length
= (*fundamental_type
== nullptr)
1367 ? 0 : TYPE_LENGTH (*fundamental_type
);
1368 if (count
* ftype_length
!= TYPE_LENGTH (type
))
1381 /* Return true if an argument, whose type is described by TYPE, can be passed or
1382 returned in simd/fp registers, providing enough parameter passing registers
1383 are available. This is as described in the AAPCS64.
1385 Upon successful return, *COUNT returns the number of needed registers,
1386 *FUNDAMENTAL_TYPE contains the type of those registers.
1388 Candidate as per the AAPCS64 5.4.2.C is either a:
1391 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1392 all the members are floats and has at most 4 members.
1393 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1394 all the members are short vectors and has at most 4 members.
1397 Note that HFAs and HVAs can include nested structures and arrays. */
1400 aapcs_is_vfp_call_or_return_candidate (struct type
*type
, int *count
,
1401 struct type
**fundamental_type
)
1403 if (type
== nullptr)
1406 *fundamental_type
= nullptr;
1408 int ag_count
= aapcs_is_vfp_call_or_return_candidate_1 (type
,
1411 if (ag_count
> 0 && ag_count
<= HA_MAX_NUM_FLDS
)
1420 /* AArch64 function call information structure. */
1421 struct aarch64_call_info
1423 /* the current argument number. */
1424 unsigned argnum
= 0;
1426 /* The next general purpose register number, equivalent to NGRN as
1427 described in the AArch64 Procedure Call Standard. */
1430 /* The next SIMD and floating point register number, equivalent to
1431 NSRN as described in the AArch64 Procedure Call Standard. */
1434 /* The next stacked argument address, equivalent to NSAA as
1435 described in the AArch64 Procedure Call Standard. */
1438 /* Stack item vector. */
1439 std::vector
<stack_item_t
> si
;
1442 /* Pass a value in a sequence of consecutive X registers. The caller
1443 is responsible for ensuring sufficient registers are available. */
1446 pass_in_x (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1447 struct aarch64_call_info
*info
, struct type
*type
,
1450 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1451 int len
= TYPE_LENGTH (type
);
1452 enum type_code typecode
= TYPE_CODE (type
);
1453 int regnum
= AARCH64_X0_REGNUM
+ info
->ngrn
;
1454 const bfd_byte
*buf
= value_contents (arg
);
1460 int partial_len
= len
< X_REGISTER_SIZE
? len
: X_REGISTER_SIZE
;
1461 CORE_ADDR regval
= extract_unsigned_integer (buf
, partial_len
,
1465 /* Adjust sub-word struct/union args when big-endian. */
1466 if (byte_order
== BFD_ENDIAN_BIG
1467 && partial_len
< X_REGISTER_SIZE
1468 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1469 regval
<<= ((X_REGISTER_SIZE
- partial_len
) * TARGET_CHAR_BIT
);
1473 debug_printf ("arg %d in %s = 0x%s\n", info
->argnum
,
1474 gdbarch_register_name (gdbarch
, regnum
),
1475 phex (regval
, X_REGISTER_SIZE
));
1477 regcache_cooked_write_unsigned (regcache
, regnum
, regval
);
1484 /* Attempt to marshall a value in a V register. Return 1 if
1485 successful, or 0 if insufficient registers are available. This
1486 function, unlike the equivalent pass_in_x() function does not
1487 handle arguments spread across multiple registers. */
1490 pass_in_v (struct gdbarch
*gdbarch
,
1491 struct regcache
*regcache
,
1492 struct aarch64_call_info
*info
,
1493 int len
, const bfd_byte
*buf
)
1497 int regnum
= AARCH64_V0_REGNUM
+ info
->nsrn
;
1498 /* Enough space for a full vector register. */
1499 gdb_byte reg
[register_size (gdbarch
, regnum
)];
1500 gdb_assert (len
<= sizeof (reg
));
1505 memset (reg
, 0, sizeof (reg
));
1506 /* PCS C.1, the argument is allocated to the least significant
1507 bits of V register. */
1508 memcpy (reg
, buf
, len
);
1509 regcache
->cooked_write (regnum
, reg
);
1513 debug_printf ("arg %d in %s\n", info
->argnum
,
1514 gdbarch_register_name (gdbarch
, regnum
));
1522 /* Marshall an argument onto the stack. */
1525 pass_on_stack (struct aarch64_call_info
*info
, struct type
*type
,
1528 const bfd_byte
*buf
= value_contents (arg
);
1529 int len
= TYPE_LENGTH (type
);
1535 align
= type_align (type
);
1537 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1538 Natural alignment of the argument's type. */
1539 align
= align_up (align
, 8);
1541 /* The AArch64 PCS requires at most doubleword alignment. */
1547 debug_printf ("arg %d len=%d @ sp + %d\n", info
->argnum
, len
,
1553 info
->si
.push_back (item
);
1556 if (info
->nsaa
& (align
- 1))
1558 /* Push stack alignment padding. */
1559 int pad
= align
- (info
->nsaa
& (align
- 1));
1564 info
->si
.push_back (item
);
1569 /* Marshall an argument into a sequence of one or more consecutive X
1570 registers or, if insufficient X registers are available then onto
1574 pass_in_x_or_stack (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1575 struct aarch64_call_info
*info
, struct type
*type
,
1578 int len
= TYPE_LENGTH (type
);
1579 int nregs
= (len
+ X_REGISTER_SIZE
- 1) / X_REGISTER_SIZE
;
1581 /* PCS C.13 - Pass in registers if we have enough spare */
1582 if (info
->ngrn
+ nregs
<= 8)
1584 pass_in_x (gdbarch
, regcache
, info
, type
, arg
);
1585 info
->ngrn
+= nregs
;
1590 pass_on_stack (info
, type
, arg
);
1594 /* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1595 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1596 registers. A return value of false is an error state as the value will have
1597 been partially passed to the stack. */
1599 pass_in_v_vfp_candidate (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1600 struct aarch64_call_info
*info
, struct type
*arg_type
,
1603 switch (TYPE_CODE (arg_type
))
1606 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1607 value_contents (arg
));
1610 case TYPE_CODE_COMPLEX
:
1612 const bfd_byte
*buf
= value_contents (arg
);
1613 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (arg_type
));
1615 if (!pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1619 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1620 buf
+ TYPE_LENGTH (target_type
));
1623 case TYPE_CODE_ARRAY
:
1624 if (TYPE_VECTOR (arg_type
))
1625 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1626 value_contents (arg
));
1629 case TYPE_CODE_STRUCT
:
1630 case TYPE_CODE_UNION
:
1631 for (int i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
1633 /* Don't include static fields. */
1634 if (field_is_static (&TYPE_FIELD (arg_type
, i
)))
1637 struct value
*field
= value_primitive_field (arg
, 0, i
, arg_type
);
1638 struct type
*field_type
= check_typedef (value_type (field
));
1640 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, info
, field_type
,
1651 /* Implement the "push_dummy_call" gdbarch method. */
1654 aarch64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1655 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1657 struct value
**args
, CORE_ADDR sp
,
1658 function_call_return_method return_method
,
1659 CORE_ADDR struct_addr
)
1662 struct aarch64_call_info info
;
1664 /* We need to know what the type of the called function is in order
1665 to determine the number of named/anonymous arguments for the
1666 actual argument placement, and the return type in order to handle
1667 return value correctly.
1669 The generic code above us views the decision of return in memory
1670 or return in registers as a two stage processes. The language
1671 handler is consulted first and may decide to return in memory (eg
1672 class with copy constructor returned by value), this will cause
1673 the generic code to allocate space AND insert an initial leading
1676 If the language code does not decide to pass in memory then the
1677 target code is consulted.
1679 If the language code decides to pass in memory we want to move
1680 the pointer inserted as the initial argument from the argument
1681 list and into X8, the conventional AArch64 struct return pointer
1684 /* Set the return address. For the AArch64, the return breakpoint
1685 is always at BP_ADDR. */
1686 regcache_cooked_write_unsigned (regcache
, AARCH64_LR_REGNUM
, bp_addr
);
1688 /* If we were given an initial argument for the return slot, lose it. */
1689 if (return_method
== return_method_hidden_param
)
1695 /* The struct_return pointer occupies X8. */
1696 if (return_method
!= return_method_normal
)
1700 debug_printf ("struct return in %s = 0x%s\n",
1701 gdbarch_register_name (gdbarch
,
1702 AARCH64_STRUCT_RETURN_REGNUM
),
1703 paddress (gdbarch
, struct_addr
));
1705 regcache_cooked_write_unsigned (regcache
, AARCH64_STRUCT_RETURN_REGNUM
,
1709 for (argnum
= 0; argnum
< nargs
; argnum
++)
1711 struct value
*arg
= args
[argnum
];
1712 struct type
*arg_type
, *fundamental_type
;
1715 arg_type
= check_typedef (value_type (arg
));
1716 len
= TYPE_LENGTH (arg_type
);
1718 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1719 if there are enough spare registers. */
1720 if (aapcs_is_vfp_call_or_return_candidate (arg_type
, &elements
,
1723 if (info
.nsrn
+ elements
<= 8)
1725 /* We know that we have sufficient registers available therefore
1726 this will never need to fallback to the stack. */
1727 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, &info
, arg_type
,
1729 gdb_assert_not_reached ("Failed to push args");
1734 pass_on_stack (&info
, arg_type
, arg
);
1739 switch (TYPE_CODE (arg_type
))
1742 case TYPE_CODE_BOOL
:
1743 case TYPE_CODE_CHAR
:
1744 case TYPE_CODE_RANGE
:
1745 case TYPE_CODE_ENUM
:
1748 /* Promote to 32 bit integer. */
1749 if (TYPE_UNSIGNED (arg_type
))
1750 arg_type
= builtin_type (gdbarch
)->builtin_uint32
;
1752 arg_type
= builtin_type (gdbarch
)->builtin_int32
;
1753 arg
= value_cast (arg_type
, arg
);
1755 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1758 case TYPE_CODE_STRUCT
:
1759 case TYPE_CODE_ARRAY
:
1760 case TYPE_CODE_UNION
:
1763 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1764 invisible reference. */
1766 /* Allocate aligned storage. */
1767 sp
= align_down (sp
- len
, 16);
1769 /* Write the real data into the stack. */
1770 write_memory (sp
, value_contents (arg
), len
);
1772 /* Construct the indirection. */
1773 arg_type
= lookup_pointer_type (arg_type
);
1774 arg
= value_from_pointer (arg_type
, sp
);
1775 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1778 /* PCS C.15 / C.18 multiple values pass. */
1779 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1783 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1788 /* Make sure stack retains 16 byte alignment. */
1790 sp
-= 16 - (info
.nsaa
& 15);
1792 while (!info
.si
.empty ())
1794 const stack_item_t
&si
= info
.si
.back ();
1797 if (si
.data
!= NULL
)
1798 write_memory (sp
, si
.data
, si
.len
);
1799 info
.si
.pop_back ();
1802 /* Finally, update the SP register. */
1803 regcache_cooked_write_unsigned (regcache
, AARCH64_SP_REGNUM
, sp
);
1808 /* Implement the "frame_align" gdbarch method. */
1811 aarch64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1813 /* Align the stack to sixteen bytes. */
1814 return sp
& ~(CORE_ADDR
) 15;
1817 /* Return the type for an AdvSISD Q register. */
1819 static struct type
*
1820 aarch64_vnq_type (struct gdbarch
*gdbarch
)
1822 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1824 if (tdep
->vnq_type
== NULL
)
1829 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
1832 elem
= builtin_type (gdbarch
)->builtin_uint128
;
1833 append_composite_type_field (t
, "u", elem
);
1835 elem
= builtin_type (gdbarch
)->builtin_int128
;
1836 append_composite_type_field (t
, "s", elem
);
1841 return tdep
->vnq_type
;
1844 /* Return the type for an AdvSISD D register. */
1846 static struct type
*
1847 aarch64_vnd_type (struct gdbarch
*gdbarch
)
1849 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1851 if (tdep
->vnd_type
== NULL
)
1856 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
1859 elem
= builtin_type (gdbarch
)->builtin_double
;
1860 append_composite_type_field (t
, "f", elem
);
1862 elem
= builtin_type (gdbarch
)->builtin_uint64
;
1863 append_composite_type_field (t
, "u", elem
);
1865 elem
= builtin_type (gdbarch
)->builtin_int64
;
1866 append_composite_type_field (t
, "s", elem
);
1871 return tdep
->vnd_type
;
1874 /* Return the type for an AdvSISD S register. */
1876 static struct type
*
1877 aarch64_vns_type (struct gdbarch
*gdbarch
)
1879 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1881 if (tdep
->vns_type
== NULL
)
1886 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
1889 elem
= builtin_type (gdbarch
)->builtin_float
;
1890 append_composite_type_field (t
, "f", elem
);
1892 elem
= builtin_type (gdbarch
)->builtin_uint32
;
1893 append_composite_type_field (t
, "u", elem
);
1895 elem
= builtin_type (gdbarch
)->builtin_int32
;
1896 append_composite_type_field (t
, "s", elem
);
1901 return tdep
->vns_type
;
1904 /* Return the type for an AdvSISD H register. */
1906 static struct type
*
1907 aarch64_vnh_type (struct gdbarch
*gdbarch
)
1909 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1911 if (tdep
->vnh_type
== NULL
)
1916 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
1919 elem
= builtin_type (gdbarch
)->builtin_half
;
1920 append_composite_type_field (t
, "f", elem
);
1922 elem
= builtin_type (gdbarch
)->builtin_uint16
;
1923 append_composite_type_field (t
, "u", elem
);
1925 elem
= builtin_type (gdbarch
)->builtin_int16
;
1926 append_composite_type_field (t
, "s", elem
);
1931 return tdep
->vnh_type
;
1934 /* Return the type for an AdvSISD B register. */
1936 static struct type
*
1937 aarch64_vnb_type (struct gdbarch
*gdbarch
)
1939 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1941 if (tdep
->vnb_type
== NULL
)
1946 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
1949 elem
= builtin_type (gdbarch
)->builtin_uint8
;
1950 append_composite_type_field (t
, "u", elem
);
1952 elem
= builtin_type (gdbarch
)->builtin_int8
;
1953 append_composite_type_field (t
, "s", elem
);
1958 return tdep
->vnb_type
;
1961 /* Return the type for an AdvSISD V register. */
1963 static struct type
*
1964 aarch64_vnv_type (struct gdbarch
*gdbarch
)
1966 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1968 if (tdep
->vnv_type
== NULL
)
1970 /* The other AArch64 psuedo registers (Q,D,H,S,B) refer to a single value
1971 slice from the non-pseudo vector registers. However NEON V registers
1972 are always vector registers, and need constructing as such. */
1973 const struct builtin_type
*bt
= builtin_type (gdbarch
);
1975 struct type
*t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnv",
1978 struct type
*sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
1980 append_composite_type_field (sub
, "f",
1981 init_vector_type (bt
->builtin_double
, 2));
1982 append_composite_type_field (sub
, "u",
1983 init_vector_type (bt
->builtin_uint64
, 2));
1984 append_composite_type_field (sub
, "s",
1985 init_vector_type (bt
->builtin_int64
, 2));
1986 append_composite_type_field (t
, "d", sub
);
1988 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
1990 append_composite_type_field (sub
, "f",
1991 init_vector_type (bt
->builtin_float
, 4));
1992 append_composite_type_field (sub
, "u",
1993 init_vector_type (bt
->builtin_uint32
, 4));
1994 append_composite_type_field (sub
, "s",
1995 init_vector_type (bt
->builtin_int32
, 4));
1996 append_composite_type_field (t
, "s", sub
);
1998 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
2000 append_composite_type_field (sub
, "f",
2001 init_vector_type (bt
->builtin_half
, 8));
2002 append_composite_type_field (sub
, "u",
2003 init_vector_type (bt
->builtin_uint16
, 8));
2004 append_composite_type_field (sub
, "s",
2005 init_vector_type (bt
->builtin_int16
, 8));
2006 append_composite_type_field (t
, "h", sub
);
2008 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
2010 append_composite_type_field (sub
, "u",
2011 init_vector_type (bt
->builtin_uint8
, 16));
2012 append_composite_type_field (sub
, "s",
2013 init_vector_type (bt
->builtin_int8
, 16));
2014 append_composite_type_field (t
, "b", sub
);
2016 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
2018 append_composite_type_field (sub
, "u",
2019 init_vector_type (bt
->builtin_uint128
, 1));
2020 append_composite_type_field (sub
, "s",
2021 init_vector_type (bt
->builtin_int128
, 1));
2022 append_composite_type_field (t
, "q", sub
);
2027 return tdep
->vnv_type
;
2030 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
2033 aarch64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
2035 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2037 if (reg
>= AARCH64_DWARF_X0
&& reg
<= AARCH64_DWARF_X0
+ 30)
2038 return AARCH64_X0_REGNUM
+ reg
- AARCH64_DWARF_X0
;
2040 if (reg
== AARCH64_DWARF_SP
)
2041 return AARCH64_SP_REGNUM
;
2043 if (reg
>= AARCH64_DWARF_V0
&& reg
<= AARCH64_DWARF_V0
+ 31)
2044 return AARCH64_V0_REGNUM
+ reg
- AARCH64_DWARF_V0
;
2046 if (reg
== AARCH64_DWARF_SVE_VG
)
2047 return AARCH64_SVE_VG_REGNUM
;
2049 if (reg
== AARCH64_DWARF_SVE_FFR
)
2050 return AARCH64_SVE_FFR_REGNUM
;
2052 if (reg
>= AARCH64_DWARF_SVE_P0
&& reg
<= AARCH64_DWARF_SVE_P0
+ 15)
2053 return AARCH64_SVE_P0_REGNUM
+ reg
- AARCH64_DWARF_SVE_P0
;
2055 if (reg
>= AARCH64_DWARF_SVE_Z0
&& reg
<= AARCH64_DWARF_SVE_Z0
+ 15)
2056 return AARCH64_SVE_Z0_REGNUM
+ reg
- AARCH64_DWARF_SVE_Z0
;
2058 if (tdep
->has_pauth ())
2060 if (reg
>= AARCH64_DWARF_PAUTH_DMASK
&& reg
<= AARCH64_DWARF_PAUTH_CMASK
)
2061 return tdep
->pauth_reg_base
+ reg
- AARCH64_DWARF_PAUTH_DMASK
;
2063 if (reg
== AARCH64_DWARF_PAUTH_RA_STATE
)
2064 return tdep
->pauth_ra_state_regnum
;
2070 /* Implement the "print_insn" gdbarch method. */
2073 aarch64_gdb_print_insn (bfd_vma memaddr
, disassemble_info
*info
)
2075 info
->symbols
= NULL
;
2076 return default_print_insn (memaddr
, info
);
2079 /* AArch64 BRK software debug mode instruction.
2080 Note that AArch64 code is always little-endian.
2081 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
2082 constexpr gdb_byte aarch64_default_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
2084 typedef BP_MANIPULATION (aarch64_default_breakpoint
) aarch64_breakpoint
;
2086 /* Extract from an array REGS containing the (raw) register state a
2087 function return value of type TYPE, and copy that, in virtual
2088 format, into VALBUF. */
2091 aarch64_extract_return_value (struct type
*type
, struct regcache
*regs
,
2094 struct gdbarch
*gdbarch
= regs
->arch ();
2095 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2097 struct type
*fundamental_type
;
2099 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2102 int len
= TYPE_LENGTH (fundamental_type
);
2104 for (int i
= 0; i
< elements
; i
++)
2106 int regno
= AARCH64_V0_REGNUM
+ i
;
2107 /* Enough space for a full vector register. */
2108 gdb_byte buf
[register_size (gdbarch
, regno
)];
2109 gdb_assert (len
<= sizeof (buf
));
2113 debug_printf ("read HFA or HVA return value element %d from %s\n",
2115 gdbarch_register_name (gdbarch
, regno
));
2117 regs
->cooked_read (regno
, buf
);
2119 memcpy (valbuf
, buf
, len
);
2123 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2124 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2125 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2126 || TYPE_CODE (type
) == TYPE_CODE_PTR
2127 || TYPE_IS_REFERENCE (type
)
2128 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2130 /* If the type is a plain integer, then the access is
2131 straight-forward. Otherwise we have to play around a bit
2133 int len
= TYPE_LENGTH (type
);
2134 int regno
= AARCH64_X0_REGNUM
;
2139 /* By using store_unsigned_integer we avoid having to do
2140 anything special for small big-endian values. */
2141 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2142 store_unsigned_integer (valbuf
,
2143 (len
> X_REGISTER_SIZE
2144 ? X_REGISTER_SIZE
: len
), byte_order
, tmp
);
2145 len
-= X_REGISTER_SIZE
;
2146 valbuf
+= X_REGISTER_SIZE
;
2151 /* For a structure or union the behaviour is as if the value had
2152 been stored to word-aligned memory and then loaded into
2153 registers with 64-bit load instruction(s). */
2154 int len
= TYPE_LENGTH (type
);
2155 int regno
= AARCH64_X0_REGNUM
;
2156 bfd_byte buf
[X_REGISTER_SIZE
];
2160 regs
->cooked_read (regno
++, buf
);
2161 memcpy (valbuf
, buf
, len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2162 len
-= X_REGISTER_SIZE
;
2163 valbuf
+= X_REGISTER_SIZE
;
2169 /* Will a function return an aggregate type in memory or in a
2170 register? Return 0 if an aggregate type can be returned in a
2171 register, 1 if it must be returned in memory. */
2174 aarch64_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2176 type
= check_typedef (type
);
2178 struct type
*fundamental_type
;
2180 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2183 /* v0-v7 are used to return values and one register is allocated
2184 for one member. However, HFA or HVA has at most four members. */
2188 if (TYPE_LENGTH (type
) > 16)
2190 /* PCS B.6 Aggregates larger than 16 bytes are passed by
2191 invisible reference. */
2199 /* Write into appropriate registers a function return value of type
2200 TYPE, given in virtual format. */
2203 aarch64_store_return_value (struct type
*type
, struct regcache
*regs
,
2204 const gdb_byte
*valbuf
)
2206 struct gdbarch
*gdbarch
= regs
->arch ();
2207 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2209 struct type
*fundamental_type
;
2211 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2214 int len
= TYPE_LENGTH (fundamental_type
);
2216 for (int i
= 0; i
< elements
; i
++)
2218 int regno
= AARCH64_V0_REGNUM
+ i
;
2219 /* Enough space for a full vector register. */
2220 gdb_byte tmpbuf
[register_size (gdbarch
, regno
)];
2221 gdb_assert (len
<= sizeof (tmpbuf
));
2225 debug_printf ("write HFA or HVA return value element %d to %s\n",
2227 gdbarch_register_name (gdbarch
, regno
));
2230 memcpy (tmpbuf
, valbuf
,
2231 len
> V_REGISTER_SIZE
? V_REGISTER_SIZE
: len
);
2232 regs
->cooked_write (regno
, tmpbuf
);
2236 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2237 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2238 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2239 || TYPE_CODE (type
) == TYPE_CODE_PTR
2240 || TYPE_IS_REFERENCE (type
)
2241 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2243 if (TYPE_LENGTH (type
) <= X_REGISTER_SIZE
)
2245 /* Values of one word or less are zero/sign-extended and
2247 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2248 LONGEST val
= unpack_long (type
, valbuf
);
2250 store_signed_integer (tmpbuf
, X_REGISTER_SIZE
, byte_order
, val
);
2251 regs
->cooked_write (AARCH64_X0_REGNUM
, tmpbuf
);
2255 /* Integral values greater than one word are stored in
2256 consecutive registers starting with r0. This will always
2257 be a multiple of the regiser size. */
2258 int len
= TYPE_LENGTH (type
);
2259 int regno
= AARCH64_X0_REGNUM
;
2263 regs
->cooked_write (regno
++, valbuf
);
2264 len
-= X_REGISTER_SIZE
;
2265 valbuf
+= X_REGISTER_SIZE
;
2271 /* For a structure or union the behaviour is as if the value had
2272 been stored to word-aligned memory and then loaded into
2273 registers with 64-bit load instruction(s). */
2274 int len
= TYPE_LENGTH (type
);
2275 int regno
= AARCH64_X0_REGNUM
;
2276 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2280 memcpy (tmpbuf
, valbuf
,
2281 len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2282 regs
->cooked_write (regno
++, tmpbuf
);
2283 len
-= X_REGISTER_SIZE
;
2284 valbuf
+= X_REGISTER_SIZE
;
2289 /* Implement the "return_value" gdbarch method. */
2291 static enum return_value_convention
2292 aarch64_return_value (struct gdbarch
*gdbarch
, struct value
*func_value
,
2293 struct type
*valtype
, struct regcache
*regcache
,
2294 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2297 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2298 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2299 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2301 if (aarch64_return_in_memory (gdbarch
, valtype
))
2304 debug_printf ("return value in memory\n");
2305 return RETURN_VALUE_STRUCT_CONVENTION
;
2310 aarch64_store_return_value (valtype
, regcache
, writebuf
);
2313 aarch64_extract_return_value (valtype
, regcache
, readbuf
);
2316 debug_printf ("return value in registers\n");
2318 return RETURN_VALUE_REGISTER_CONVENTION
;
2321 /* Implement the "get_longjmp_target" gdbarch method. */
2324 aarch64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2327 gdb_byte buf
[X_REGISTER_SIZE
];
2328 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2329 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2330 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2332 jb_addr
= get_frame_register_unsigned (frame
, AARCH64_X0_REGNUM
);
2334 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2338 *pc
= extract_unsigned_integer (buf
, X_REGISTER_SIZE
, byte_order
);
2342 /* Implement the "gen_return_address" gdbarch method. */
2345 aarch64_gen_return_address (struct gdbarch
*gdbarch
,
2346 struct agent_expr
*ax
, struct axs_value
*value
,
2349 value
->type
= register_type (gdbarch
, AARCH64_LR_REGNUM
);
2350 value
->kind
= axs_lvalue_register
;
2351 value
->u
.reg
= AARCH64_LR_REGNUM
;
2355 /* Return the pseudo register name corresponding to register regnum. */
2358 aarch64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
2360 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2362 static const char *const q_name
[] =
2364 "q0", "q1", "q2", "q3",
2365 "q4", "q5", "q6", "q7",
2366 "q8", "q9", "q10", "q11",
2367 "q12", "q13", "q14", "q15",
2368 "q16", "q17", "q18", "q19",
2369 "q20", "q21", "q22", "q23",
2370 "q24", "q25", "q26", "q27",
2371 "q28", "q29", "q30", "q31",
2374 static const char *const d_name
[] =
2376 "d0", "d1", "d2", "d3",
2377 "d4", "d5", "d6", "d7",
2378 "d8", "d9", "d10", "d11",
2379 "d12", "d13", "d14", "d15",
2380 "d16", "d17", "d18", "d19",
2381 "d20", "d21", "d22", "d23",
2382 "d24", "d25", "d26", "d27",
2383 "d28", "d29", "d30", "d31",
2386 static const char *const s_name
[] =
2388 "s0", "s1", "s2", "s3",
2389 "s4", "s5", "s6", "s7",
2390 "s8", "s9", "s10", "s11",
2391 "s12", "s13", "s14", "s15",
2392 "s16", "s17", "s18", "s19",
2393 "s20", "s21", "s22", "s23",
2394 "s24", "s25", "s26", "s27",
2395 "s28", "s29", "s30", "s31",
2398 static const char *const h_name
[] =
2400 "h0", "h1", "h2", "h3",
2401 "h4", "h5", "h6", "h7",
2402 "h8", "h9", "h10", "h11",
2403 "h12", "h13", "h14", "h15",
2404 "h16", "h17", "h18", "h19",
2405 "h20", "h21", "h22", "h23",
2406 "h24", "h25", "h26", "h27",
2407 "h28", "h29", "h30", "h31",
2410 static const char *const b_name
[] =
2412 "b0", "b1", "b2", "b3",
2413 "b4", "b5", "b6", "b7",
2414 "b8", "b9", "b10", "b11",
2415 "b12", "b13", "b14", "b15",
2416 "b16", "b17", "b18", "b19",
2417 "b20", "b21", "b22", "b23",
2418 "b24", "b25", "b26", "b27",
2419 "b28", "b29", "b30", "b31",
2422 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2424 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2425 return q_name
[p_regnum
- AARCH64_Q0_REGNUM
];
2427 if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2428 return d_name
[p_regnum
- AARCH64_D0_REGNUM
];
2430 if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2431 return s_name
[p_regnum
- AARCH64_S0_REGNUM
];
2433 if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2434 return h_name
[p_regnum
- AARCH64_H0_REGNUM
];
2436 if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2437 return b_name
[p_regnum
- AARCH64_B0_REGNUM
];
2439 if (tdep
->has_sve ())
2441 static const char *const sve_v_name
[] =
2443 "v0", "v1", "v2", "v3",
2444 "v4", "v5", "v6", "v7",
2445 "v8", "v9", "v10", "v11",
2446 "v12", "v13", "v14", "v15",
2447 "v16", "v17", "v18", "v19",
2448 "v20", "v21", "v22", "v23",
2449 "v24", "v25", "v26", "v27",
2450 "v28", "v29", "v30", "v31",
2453 if (p_regnum
>= AARCH64_SVE_V0_REGNUM
2454 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2455 return sve_v_name
[p_regnum
- AARCH64_SVE_V0_REGNUM
];
2458 /* RA_STATE is used for unwinding only. Do not assign it a name - this
2459 prevents it from being read by methods such as
2460 mi_cmd_trace_frame_collected. */
2461 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2464 internal_error (__FILE__
, __LINE__
,
2465 _("aarch64_pseudo_register_name: bad register number %d"),
2469 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
2471 static struct type
*
2472 aarch64_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2474 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2476 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2478 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2479 return aarch64_vnq_type (gdbarch
);
2481 if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2482 return aarch64_vnd_type (gdbarch
);
2484 if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2485 return aarch64_vns_type (gdbarch
);
2487 if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2488 return aarch64_vnh_type (gdbarch
);
2490 if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2491 return aarch64_vnb_type (gdbarch
);
2493 if (tdep
->has_sve () && p_regnum
>= AARCH64_SVE_V0_REGNUM
2494 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2495 return aarch64_vnv_type (gdbarch
);
2497 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2498 return builtin_type (gdbarch
)->builtin_uint64
;
2500 internal_error (__FILE__
, __LINE__
,
2501 _("aarch64_pseudo_register_type: bad register number %d"),
2505 /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2508 aarch64_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2509 struct reggroup
*group
)
2511 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2513 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2515 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2516 return group
== all_reggroup
|| group
== vector_reggroup
;
2517 else if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2518 return (group
== all_reggroup
|| group
== vector_reggroup
2519 || group
== float_reggroup
);
2520 else if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2521 return (group
== all_reggroup
|| group
== vector_reggroup
2522 || group
== float_reggroup
);
2523 else if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2524 return group
== all_reggroup
|| group
== vector_reggroup
;
2525 else if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2526 return group
== all_reggroup
|| group
== vector_reggroup
;
2527 else if (tdep
->has_sve () && p_regnum
>= AARCH64_SVE_V0_REGNUM
2528 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2529 return group
== all_reggroup
|| group
== vector_reggroup
;
2530 /* RA_STATE is used for unwinding only. Do not assign it to any groups. */
2531 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2534 return group
== all_reggroup
;
2537 /* Helper for aarch64_pseudo_read_value. */
2539 static struct value
*
2540 aarch64_pseudo_read_value_1 (struct gdbarch
*gdbarch
,
2541 readable_regcache
*regcache
, int regnum_offset
,
2542 int regsize
, struct value
*result_value
)
2544 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2546 /* Enough space for a full vector register. */
2547 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2548 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2550 if (regcache
->raw_read (v_regnum
, reg_buf
) != REG_VALID
)
2551 mark_value_bytes_unavailable (result_value
, 0,
2552 TYPE_LENGTH (value_type (result_value
)));
2554 memcpy (value_contents_raw (result_value
), reg_buf
, regsize
);
2556 return result_value
;
2559 /* Implement the "pseudo_register_read_value" gdbarch method. */
2561 static struct value
*
2562 aarch64_pseudo_read_value (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2565 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2566 struct value
*result_value
= allocate_value (register_type (gdbarch
, regnum
));
2568 VALUE_LVAL (result_value
) = lval_register
;
2569 VALUE_REGNUM (result_value
) = regnum
;
2571 regnum
-= gdbarch_num_regs (gdbarch
);
2573 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2574 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2575 regnum
- AARCH64_Q0_REGNUM
,
2576 Q_REGISTER_SIZE
, result_value
);
2578 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2579 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2580 regnum
- AARCH64_D0_REGNUM
,
2581 D_REGISTER_SIZE
, result_value
);
2583 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2584 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2585 regnum
- AARCH64_S0_REGNUM
,
2586 S_REGISTER_SIZE
, result_value
);
2588 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2589 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2590 regnum
- AARCH64_H0_REGNUM
,
2591 H_REGISTER_SIZE
, result_value
);
2593 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2594 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2595 regnum
- AARCH64_B0_REGNUM
,
2596 B_REGISTER_SIZE
, result_value
);
2598 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2599 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2600 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2601 regnum
- AARCH64_SVE_V0_REGNUM
,
2602 V_REGISTER_SIZE
, result_value
);
2604 gdb_assert_not_reached ("regnum out of bound");
2607 /* Helper for aarch64_pseudo_write. */
2610 aarch64_pseudo_write_1 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2611 int regnum_offset
, int regsize
, const gdb_byte
*buf
)
2613 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2615 /* Enough space for a full vector register. */
2616 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2617 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2619 /* Ensure the register buffer is zero, we want gdb writes of the
2620 various 'scalar' pseudo registers to behavior like architectural
2621 writes, register width bytes are written the remainder are set to
2623 memset (reg_buf
, 0, register_size (gdbarch
, AARCH64_V0_REGNUM
));
2625 memcpy (reg_buf
, buf
, regsize
);
2626 regcache
->raw_write (v_regnum
, reg_buf
);
2629 /* Implement the "pseudo_register_write" gdbarch method. */
2632 aarch64_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2633 int regnum
, const gdb_byte
*buf
)
2635 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2636 regnum
-= gdbarch_num_regs (gdbarch
);
2638 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2639 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2640 regnum
- AARCH64_Q0_REGNUM
, Q_REGISTER_SIZE
,
2643 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2644 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2645 regnum
- AARCH64_D0_REGNUM
, D_REGISTER_SIZE
,
2648 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2649 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2650 regnum
- AARCH64_S0_REGNUM
, S_REGISTER_SIZE
,
2653 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2654 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2655 regnum
- AARCH64_H0_REGNUM
, H_REGISTER_SIZE
,
2658 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2659 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2660 regnum
- AARCH64_B0_REGNUM
, B_REGISTER_SIZE
,
2663 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2664 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2665 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2666 regnum
- AARCH64_SVE_V0_REGNUM
,
2667 V_REGISTER_SIZE
, buf
);
2669 gdb_assert_not_reached ("regnum out of bound");
2672 /* Callback function for user_reg_add. */
2674 static struct value
*
2675 value_of_aarch64_user_reg (struct frame_info
*frame
, const void *baton
)
2677 const int *reg_p
= (const int *) baton
;
2679 return value_of_register (*reg_p
, frame
);
2683 /* Implement the "software_single_step" gdbarch method, needed to
2684 single step through atomic sequences on AArch64. */
2686 static std::vector
<CORE_ADDR
>
2687 aarch64_software_single_step (struct regcache
*regcache
)
2689 struct gdbarch
*gdbarch
= regcache
->arch ();
2690 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2691 const int insn_size
= 4;
2692 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2693 CORE_ADDR pc
= regcache_read_pc (regcache
);
2694 CORE_ADDR breaks
[2] = { CORE_ADDR_MAX
, CORE_ADDR_MAX
};
2696 CORE_ADDR closing_insn
= 0;
2697 uint32_t insn
= read_memory_unsigned_integer (loc
, insn_size
,
2698 byte_order_for_code
);
2701 int bc_insn_count
= 0; /* Conditional branch instruction count. */
2702 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2705 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2708 /* Look for a Load Exclusive instruction which begins the sequence. */
2709 if (inst
.opcode
->iclass
!= ldstexcl
|| bit (insn
, 22) == 0)
2712 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2715 insn
= read_memory_unsigned_integer (loc
, insn_size
,
2716 byte_order_for_code
);
2718 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2720 /* Check if the instruction is a conditional branch. */
2721 if (inst
.opcode
->iclass
== condbranch
)
2723 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_ADDR_PCREL19
);
2725 if (bc_insn_count
>= 1)
2728 /* It is, so we'll try to set a breakpoint at the destination. */
2729 breaks
[1] = loc
+ inst
.operands
[0].imm
.value
;
2735 /* Look for the Store Exclusive which closes the atomic sequence. */
2736 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22) == 0)
2743 /* We didn't find a closing Store Exclusive instruction, fall back. */
2747 /* Insert breakpoint after the end of the atomic sequence. */
2748 breaks
[0] = loc
+ insn_size
;
2750 /* Check for duplicated breakpoints, and also check that the second
2751 breakpoint is not within the atomic sequence. */
2753 && (breaks
[1] == breaks
[0]
2754 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
2755 last_breakpoint
= 0;
2757 std::vector
<CORE_ADDR
> next_pcs
;
2759 /* Insert the breakpoint at the end of the sequence, and one at the
2760 destination of the conditional branch, if it exists. */
2761 for (index
= 0; index
<= last_breakpoint
; index
++)
2762 next_pcs
.push_back (breaks
[index
]);
2767 struct aarch64_displaced_step_closure
: public displaced_step_closure
2769 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2770 is being displaced stepping. */
2773 /* PC adjustment offset after displaced stepping. If 0, then we don't
2774 write the PC back, assuming the PC is already the right address. */
2775 int32_t pc_adjust
= 0;
2778 /* Data when visiting instructions for displaced stepping. */
2780 struct aarch64_displaced_step_data
2782 struct aarch64_insn_data base
;
2784 /* The address where the instruction will be executed at. */
2786 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2787 uint32_t insn_buf
[AARCH64_DISPLACED_MODIFIED_INSNS
];
2788 /* Number of instructions in INSN_BUF. */
2789 unsigned insn_count
;
2790 /* Registers when doing displaced stepping. */
2791 struct regcache
*regs
;
2793 aarch64_displaced_step_closure
*dsc
;
2796 /* Implementation of aarch64_insn_visitor method "b". */
2799 aarch64_displaced_step_b (const int is_bl
, const int32_t offset
,
2800 struct aarch64_insn_data
*data
)
2802 struct aarch64_displaced_step_data
*dsd
2803 = (struct aarch64_displaced_step_data
*) data
;
2804 int64_t new_offset
= data
->insn_addr
- dsd
->new_addr
+ offset
;
2806 if (can_encode_int32 (new_offset
, 28))
2808 /* Emit B rather than BL, because executing BL on a new address
2809 will get the wrong address into LR. In order to avoid this,
2810 we emit B, and update LR if the instruction is BL. */
2811 emit_b (dsd
->insn_buf
, 0, new_offset
);
2817 emit_nop (dsd
->insn_buf
);
2819 dsd
->dsc
->pc_adjust
= offset
;
2825 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_LR_REGNUM
,
2826 data
->insn_addr
+ 4);
2830 /* Implementation of aarch64_insn_visitor method "b_cond". */
2833 aarch64_displaced_step_b_cond (const unsigned cond
, const int32_t offset
,
2834 struct aarch64_insn_data
*data
)
2836 struct aarch64_displaced_step_data
*dsd
2837 = (struct aarch64_displaced_step_data
*) data
;
2839 /* GDB has to fix up PC after displaced step this instruction
2840 differently according to the condition is true or false. Instead
2841 of checking COND against conditional flags, we can use
2842 the following instructions, and GDB can tell how to fix up PC
2843 according to the PC value.
2845 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2851 emit_bcond (dsd
->insn_buf
, cond
, 8);
2852 dsd
->dsc
->cond
= true;
2853 dsd
->dsc
->pc_adjust
= offset
;
2854 dsd
->insn_count
= 1;
2857 /* Dynamically allocate a new register. If we know the register
2858 statically, we should make it a global as above instead of using this
2861 static struct aarch64_register
2862 aarch64_register (unsigned num
, int is64
)
2864 return (struct aarch64_register
) { num
, is64
};
2867 /* Implementation of aarch64_insn_visitor method "cb". */
2870 aarch64_displaced_step_cb (const int32_t offset
, const int is_cbnz
,
2871 const unsigned rn
, int is64
,
2872 struct aarch64_insn_data
*data
)
2874 struct aarch64_displaced_step_data
*dsd
2875 = (struct aarch64_displaced_step_data
*) data
;
2877 /* The offset is out of range for a compare and branch
2878 instruction. We can use the following instructions instead:
2880 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2885 emit_cb (dsd
->insn_buf
, is_cbnz
, aarch64_register (rn
, is64
), 8);
2886 dsd
->insn_count
= 1;
2887 dsd
->dsc
->cond
= true;
2888 dsd
->dsc
->pc_adjust
= offset
;
2891 /* Implementation of aarch64_insn_visitor method "tb". */
2894 aarch64_displaced_step_tb (const int32_t offset
, int is_tbnz
,
2895 const unsigned rt
, unsigned bit
,
2896 struct aarch64_insn_data
*data
)
2898 struct aarch64_displaced_step_data
*dsd
2899 = (struct aarch64_displaced_step_data
*) data
;
2901 /* The offset is out of range for a test bit and branch
2902 instruction We can use the following instructions instead:
2904 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2910 emit_tb (dsd
->insn_buf
, is_tbnz
, bit
, aarch64_register (rt
, 1), 8);
2911 dsd
->insn_count
= 1;
2912 dsd
->dsc
->cond
= true;
2913 dsd
->dsc
->pc_adjust
= offset
;
2916 /* Implementation of aarch64_insn_visitor method "adr". */
2919 aarch64_displaced_step_adr (const int32_t offset
, const unsigned rd
,
2920 const int is_adrp
, struct aarch64_insn_data
*data
)
2922 struct aarch64_displaced_step_data
*dsd
2923 = (struct aarch64_displaced_step_data
*) data
;
2924 /* We know exactly the address the ADR{P,} instruction will compute.
2925 We can just write it to the destination register. */
2926 CORE_ADDR address
= data
->insn_addr
+ offset
;
2930 /* Clear the lower 12 bits of the offset to get the 4K page. */
2931 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
2935 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
2938 dsd
->dsc
->pc_adjust
= 4;
2939 emit_nop (dsd
->insn_buf
);
2940 dsd
->insn_count
= 1;
2943 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
2946 aarch64_displaced_step_ldr_literal (const int32_t offset
, const int is_sw
,
2947 const unsigned rt
, const int is64
,
2948 struct aarch64_insn_data
*data
)
2950 struct aarch64_displaced_step_data
*dsd
2951 = (struct aarch64_displaced_step_data
*) data
;
2952 CORE_ADDR address
= data
->insn_addr
+ offset
;
2953 struct aarch64_memory_operand zero
= { MEMORY_OPERAND_OFFSET
, 0 };
2955 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rt
,
2959 dsd
->insn_count
= emit_ldrsw (dsd
->insn_buf
, aarch64_register (rt
, 1),
2960 aarch64_register (rt
, 1), zero
);
2962 dsd
->insn_count
= emit_ldr (dsd
->insn_buf
, aarch64_register (rt
, is64
),
2963 aarch64_register (rt
, 1), zero
);
2965 dsd
->dsc
->pc_adjust
= 4;
2968 /* Implementation of aarch64_insn_visitor method "others". */
2971 aarch64_displaced_step_others (const uint32_t insn
,
2972 struct aarch64_insn_data
*data
)
2974 struct aarch64_displaced_step_data
*dsd
2975 = (struct aarch64_displaced_step_data
*) data
;
2977 aarch64_emit_insn (dsd
->insn_buf
, insn
);
2978 dsd
->insn_count
= 1;
2980 if ((insn
& 0xfffffc1f) == 0xd65f0000)
2983 dsd
->dsc
->pc_adjust
= 0;
2986 dsd
->dsc
->pc_adjust
= 4;
2989 static const struct aarch64_insn_visitor visitor
=
2991 aarch64_displaced_step_b
,
2992 aarch64_displaced_step_b_cond
,
2993 aarch64_displaced_step_cb
,
2994 aarch64_displaced_step_tb
,
2995 aarch64_displaced_step_adr
,
2996 aarch64_displaced_step_ldr_literal
,
2997 aarch64_displaced_step_others
,
3000 /* Implement the "displaced_step_copy_insn" gdbarch method. */
3002 struct displaced_step_closure
*
3003 aarch64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
3004 CORE_ADDR from
, CORE_ADDR to
,
3005 struct regcache
*regs
)
3007 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3008 uint32_t insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
3009 struct aarch64_displaced_step_data dsd
;
3012 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
3015 /* Look for a Load Exclusive instruction which begins the sequence. */
3016 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22))
3018 /* We can't displaced step atomic sequences. */
3022 std::unique_ptr
<aarch64_displaced_step_closure
> dsc
3023 (new aarch64_displaced_step_closure
);
3024 dsd
.base
.insn_addr
= from
;
3027 dsd
.dsc
= dsc
.get ();
3029 aarch64_relocate_instruction (insn
, &visitor
,
3030 (struct aarch64_insn_data
*) &dsd
);
3031 gdb_assert (dsd
.insn_count
<= AARCH64_DISPLACED_MODIFIED_INSNS
);
3033 if (dsd
.insn_count
!= 0)
3037 /* Instruction can be relocated to scratch pad. Copy
3038 relocated instruction(s) there. */
3039 for (i
= 0; i
< dsd
.insn_count
; i
++)
3041 if (debug_displaced
)
3043 debug_printf ("displaced: writing insn ");
3044 debug_printf ("%.8x", dsd
.insn_buf
[i
]);
3045 debug_printf (" at %s\n", paddress (gdbarch
, to
+ i
* 4));
3047 write_memory_unsigned_integer (to
+ i
* 4, 4, byte_order_for_code
,
3048 (ULONGEST
) dsd
.insn_buf
[i
]);
3056 return dsc
.release ();
3059 /* Implement the "displaced_step_fixup" gdbarch method. */
3062 aarch64_displaced_step_fixup (struct gdbarch
*gdbarch
,
3063 struct displaced_step_closure
*dsc_
,
3064 CORE_ADDR from
, CORE_ADDR to
,
3065 struct regcache
*regs
)
3067 aarch64_displaced_step_closure
*dsc
= (aarch64_displaced_step_closure
*) dsc_
;
3071 regcache_cooked_read_unsigned (regs
, AARCH64_PC_REGNUM
, &pc
);
3073 if (debug_displaced
)
3074 debug_printf ("Displaced: PC after stepping: %s (was %s).\n",
3075 paddress (gdbarch
, pc
), paddress (gdbarch
, to
));
3079 if (debug_displaced
)
3080 debug_printf ("Displaced: [Conditional] pc_adjust before: %d\n",
3085 /* Condition is true. */
3087 else if (pc
- to
== 4)
3089 /* Condition is false. */
3093 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
3095 if (debug_displaced
)
3096 debug_printf ("Displaced: [Conditional] pc_adjust after: %d\n",
3100 if (debug_displaced
)
3101 debug_printf ("Displaced: %s PC by %d\n",
3102 dsc
->pc_adjust
? "adjusting" : "not adjusting",
3106 if (dsc
->pc_adjust
!= 0)
3108 /* Make sure the previous instruction was executed (that is, the PC
3109 has changed). If the PC didn't change, then discard the adjustment
3110 offset. Otherwise we may skip an instruction before its execution
3114 if (debug_displaced
)
3115 debug_printf ("Displaced: PC did not move. Discarding PC "
3120 if (debug_displaced
)
3122 debug_printf ("Displaced: fixup: set PC to %s:%d\n",
3123 paddress (gdbarch
, from
), dsc
->pc_adjust
);
3125 regcache_cooked_write_unsigned (regs
, AARCH64_PC_REGNUM
,
3126 from
+ dsc
->pc_adjust
);
3130 /* Implement the "displaced_step_hw_singlestep" gdbarch method. */
3133 aarch64_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
3134 struct displaced_step_closure
*closure
)
3139 /* Get the correct target description for the given VQ value.
3140 If VQ is zero then it is assumed SVE is not supported.
3141 (It is not possible to set VQ to zero on an SVE system). */
3144 aarch64_read_description (uint64_t vq
, bool pauth_p
)
3146 if (vq
> AARCH64_MAX_SVE_VQ
)
3147 error (_("VQ is %" PRIu64
", maximum supported value is %d"), vq
,
3148 AARCH64_MAX_SVE_VQ
);
3150 struct target_desc
*tdesc
= tdesc_aarch64_list
[vq
][pauth_p
];
3154 tdesc
= aarch64_create_target_description (vq
, pauth_p
);
3155 tdesc_aarch64_list
[vq
][pauth_p
] = tdesc
;
3161 /* Return the VQ used when creating the target description TDESC. */
3164 aarch64_get_tdesc_vq (const struct target_desc
*tdesc
)
3166 const struct tdesc_feature
*feature_sve
;
3168 if (!tdesc_has_registers (tdesc
))
3171 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3173 if (feature_sve
== nullptr)
3176 uint64_t vl
= tdesc_register_bitsize (feature_sve
,
3177 aarch64_sve_register_names
[0]) / 8;
3178 return sve_vq_from_vl (vl
);
3181 /* Add all the expected register sets into GDBARCH. */
3184 aarch64_add_reggroups (struct gdbarch
*gdbarch
)
3186 reggroup_add (gdbarch
, general_reggroup
);
3187 reggroup_add (gdbarch
, float_reggroup
);
3188 reggroup_add (gdbarch
, system_reggroup
);
3189 reggroup_add (gdbarch
, vector_reggroup
);
3190 reggroup_add (gdbarch
, all_reggroup
);
3191 reggroup_add (gdbarch
, save_reggroup
);
3192 reggroup_add (gdbarch
, restore_reggroup
);
3195 /* Implement the "cannot_store_register" gdbarch method. */
3198 aarch64_cannot_store_register (struct gdbarch
*gdbarch
, int regnum
)
3200 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3202 if (!tdep
->has_pauth ())
3205 /* Pointer authentication registers are read-only. */
3206 return (regnum
== AARCH64_PAUTH_DMASK_REGNUM (tdep
->pauth_reg_base
)
3207 || regnum
== AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
));
3210 /* Initialize the current architecture based on INFO. If possible,
3211 re-use an architecture from ARCHES, which is a list of
3212 architectures already created during this debugging session.
3214 Called e.g. at program startup, when reading a core file, and when
3215 reading a binary file. */
3217 static struct gdbarch
*
3218 aarch64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3220 const struct tdesc_feature
*feature_core
, *feature_fpu
, *feature_sve
;
3221 const struct tdesc_feature
*feature_pauth
;
3222 bool valid_p
= true;
3223 int i
, num_regs
= 0, num_pseudo_regs
= 0;
3224 int first_pauth_regnum
= -1, pauth_ra_state_offset
= -1;
3226 /* Use the vector length passed via the target info. Here -1 is used for no
3227 SVE, and 0 is unset. If unset then use the vector length from the existing
3230 if (info
.id
== (int *) -1)
3232 else if (info
.id
!= 0)
3233 vq
= (uint64_t) info
.id
;
3235 vq
= aarch64_get_tdesc_vq (info
.target_desc
);
3237 if (vq
> AARCH64_MAX_SVE_VQ
)
3238 internal_error (__FILE__
, __LINE__
, _("VQ out of bounds: %s (max %d)"),
3239 pulongest (vq
), AARCH64_MAX_SVE_VQ
);
3241 /* If there is already a candidate, use it. */
3242 for (gdbarch_list
*best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
3243 best_arch
!= nullptr;
3244 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
3246 struct gdbarch_tdep
*tdep
= gdbarch_tdep (best_arch
->gdbarch
);
3247 if (tdep
&& tdep
->vq
== vq
)
3248 return best_arch
->gdbarch
;
3251 /* Ensure we always have a target descriptor, and that it is for the given VQ
3253 const struct target_desc
*tdesc
= info
.target_desc
;
3254 if (!tdesc_has_registers (tdesc
) || vq
!= aarch64_get_tdesc_vq (tdesc
))
3255 tdesc
= aarch64_read_description (vq
, false);
3258 feature_core
= tdesc_find_feature (tdesc
,"org.gnu.gdb.aarch64.core");
3259 feature_fpu
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.fpu");
3260 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3261 feature_pauth
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.pauth");
3263 if (feature_core
== nullptr)
3266 struct tdesc_arch_data
*tdesc_data
= tdesc_data_alloc ();
3268 /* Validate the description provides the mandatory core R registers
3269 and allocate their numbers. */
3270 for (i
= 0; i
< ARRAY_SIZE (aarch64_r_register_names
); i
++)
3271 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
,
3272 AARCH64_X0_REGNUM
+ i
,
3273 aarch64_r_register_names
[i
]);
3275 num_regs
= AARCH64_X0_REGNUM
+ i
;
3277 /* Add the V registers. */
3278 if (feature_fpu
!= nullptr)
3280 if (feature_sve
!= nullptr)
3281 error (_("Program contains both fpu and SVE features."));
3283 /* Validate the description provides the mandatory V registers
3284 and allocate their numbers. */
3285 for (i
= 0; i
< ARRAY_SIZE (aarch64_v_register_names
); i
++)
3286 valid_p
&= tdesc_numbered_register (feature_fpu
, tdesc_data
,
3287 AARCH64_V0_REGNUM
+ i
,
3288 aarch64_v_register_names
[i
]);
3290 num_regs
= AARCH64_V0_REGNUM
+ i
;
3293 /* Add the SVE registers. */
3294 if (feature_sve
!= nullptr)
3296 /* Validate the description provides the mandatory SVE registers
3297 and allocate their numbers. */
3298 for (i
= 0; i
< ARRAY_SIZE (aarch64_sve_register_names
); i
++)
3299 valid_p
&= tdesc_numbered_register (feature_sve
, tdesc_data
,
3300 AARCH64_SVE_Z0_REGNUM
+ i
,
3301 aarch64_sve_register_names
[i
]);
3303 num_regs
= AARCH64_SVE_Z0_REGNUM
+ i
;
3304 num_pseudo_regs
+= 32; /* add the Vn register pseudos. */
3307 if (feature_fpu
!= nullptr || feature_sve
!= nullptr)
3309 num_pseudo_regs
+= 32; /* add the Qn scalar register pseudos */
3310 num_pseudo_regs
+= 32; /* add the Dn scalar register pseudos */
3311 num_pseudo_regs
+= 32; /* add the Sn scalar register pseudos */
3312 num_pseudo_regs
+= 32; /* add the Hn scalar register pseudos */
3313 num_pseudo_regs
+= 32; /* add the Bn scalar register pseudos */
3316 /* Add the pauth registers. */
3317 if (feature_pauth
!= NULL
)
3319 first_pauth_regnum
= num_regs
;
3320 pauth_ra_state_offset
= num_pseudo_regs
;
3321 /* Validate the descriptor provides the mandatory PAUTH registers and
3322 allocate their numbers. */
3323 for (i
= 0; i
< ARRAY_SIZE (aarch64_pauth_register_names
); i
++)
3324 valid_p
&= tdesc_numbered_register (feature_pauth
, tdesc_data
,
3325 first_pauth_regnum
+ i
,
3326 aarch64_pauth_register_names
[i
]);
3329 num_pseudo_regs
+= 1; /* Count RA_STATE pseudo register. */
3334 tdesc_data_cleanup (tdesc_data
);
3338 /* AArch64 code is always little-endian. */
3339 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
3341 struct gdbarch_tdep
*tdep
= XCNEW (struct gdbarch_tdep
);
3342 struct gdbarch
*gdbarch
= gdbarch_alloc (&info
, tdep
);
3344 /* This should be low enough for everything. */
3345 tdep
->lowest_pc
= 0x20;
3346 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
3347 tdep
->jb_elt_size
= 8;
3349 tdep
->pauth_reg_base
= first_pauth_regnum
;
3350 tdep
->pauth_ra_state_regnum
= (feature_pauth
== NULL
) ? -1
3351 : pauth_ra_state_offset
+ num_regs
;
3353 set_gdbarch_push_dummy_call (gdbarch
, aarch64_push_dummy_call
);
3354 set_gdbarch_frame_align (gdbarch
, aarch64_frame_align
);
3356 /* Advance PC across function entry code. */
3357 set_gdbarch_skip_prologue (gdbarch
, aarch64_skip_prologue
);
3359 /* The stack grows downward. */
3360 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3362 /* Breakpoint manipulation. */
3363 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
3364 aarch64_breakpoint::kind_from_pc
);
3365 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
3366 aarch64_breakpoint::bp_from_kind
);
3367 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3368 set_gdbarch_software_single_step (gdbarch
, aarch64_software_single_step
);
3370 /* Information about registers, etc. */
3371 set_gdbarch_sp_regnum (gdbarch
, AARCH64_SP_REGNUM
);
3372 set_gdbarch_pc_regnum (gdbarch
, AARCH64_PC_REGNUM
);
3373 set_gdbarch_num_regs (gdbarch
, num_regs
);
3375 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudo_regs
);
3376 set_gdbarch_pseudo_register_read_value (gdbarch
, aarch64_pseudo_read_value
);
3377 set_gdbarch_pseudo_register_write (gdbarch
, aarch64_pseudo_write
);
3378 set_tdesc_pseudo_register_name (gdbarch
, aarch64_pseudo_register_name
);
3379 set_tdesc_pseudo_register_type (gdbarch
, aarch64_pseudo_register_type
);
3380 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3381 aarch64_pseudo_register_reggroup_p
);
3382 set_gdbarch_cannot_store_register (gdbarch
, aarch64_cannot_store_register
);
3385 set_gdbarch_short_bit (gdbarch
, 16);
3386 set_gdbarch_int_bit (gdbarch
, 32);
3387 set_gdbarch_float_bit (gdbarch
, 32);
3388 set_gdbarch_double_bit (gdbarch
, 64);
3389 set_gdbarch_long_double_bit (gdbarch
, 128);
3390 set_gdbarch_long_bit (gdbarch
, 64);
3391 set_gdbarch_long_long_bit (gdbarch
, 64);
3392 set_gdbarch_ptr_bit (gdbarch
, 64);
3393 set_gdbarch_char_signed (gdbarch
, 0);
3394 set_gdbarch_wchar_signed (gdbarch
, 0);
3395 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3396 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3397 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
3398 set_gdbarch_type_align (gdbarch
, aarch64_type_align
);
3400 /* Internal <-> external register number maps. */
3401 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, aarch64_dwarf_reg_to_regnum
);
3403 /* Returning results. */
3404 set_gdbarch_return_value (gdbarch
, aarch64_return_value
);
3407 set_gdbarch_print_insn (gdbarch
, aarch64_gdb_print_insn
);
3409 /* Virtual tables. */
3410 set_gdbarch_vbit_in_delta (gdbarch
, 1);
3412 /* Register architecture. */
3413 aarch64_add_reggroups (gdbarch
);
3415 /* Hook in the ABI-specific overrides, if they have been registered. */
3416 info
.target_desc
= tdesc
;
3417 info
.tdesc_data
= tdesc_data
;
3418 gdbarch_init_osabi (info
, gdbarch
);
3420 dwarf2_frame_set_init_reg (gdbarch
, aarch64_dwarf2_frame_init_reg
);
3421 /* Register DWARF CFA vendor handler. */
3422 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch
,
3423 aarch64_execute_dwarf_cfa_vendor_op
);
3425 /* Permanent/Program breakpoint handling. */
3426 set_gdbarch_program_breakpoint_here_p (gdbarch
,
3427 aarch64_program_breakpoint_here_p
);
3429 /* Add some default predicates. */
3430 frame_unwind_append_unwinder (gdbarch
, &aarch64_stub_unwind
);
3431 dwarf2_append_unwinders (gdbarch
);
3432 frame_unwind_append_unwinder (gdbarch
, &aarch64_prologue_unwind
);
3434 frame_base_set_default (gdbarch
, &aarch64_normal_base
);
3436 /* Now we have tuned the configuration, set a few final things,
3437 based on what the OS ABI has told us. */
3439 if (tdep
->jb_pc
>= 0)
3440 set_gdbarch_get_longjmp_target (gdbarch
, aarch64_get_longjmp_target
);
3442 set_gdbarch_gen_return_address (gdbarch
, aarch64_gen_return_address
);
3444 set_gdbarch_get_pc_address_flags (gdbarch
, aarch64_get_pc_address_flags
);
3446 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
3448 /* Add standard register aliases. */
3449 for (i
= 0; i
< ARRAY_SIZE (aarch64_register_aliases
); i
++)
3450 user_reg_add (gdbarch
, aarch64_register_aliases
[i
].name
,
3451 value_of_aarch64_user_reg
,
3452 &aarch64_register_aliases
[i
].regnum
);
3454 register_aarch64_ravenscar_ops (gdbarch
);
3460 aarch64_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3462 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3467 fprintf_unfiltered (file
, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3468 paddress (gdbarch
, tdep
->lowest_pc
));
3474 static void aarch64_process_record_test (void);
3478 void _initialize_aarch64_tdep ();
3480 _initialize_aarch64_tdep ()
3482 gdbarch_register (bfd_arch_aarch64
, aarch64_gdbarch_init
,
3485 /* Debug this file's internals. */
3486 add_setshow_boolean_cmd ("aarch64", class_maintenance
, &aarch64_debug
, _("\
3487 Set AArch64 debugging."), _("\
3488 Show AArch64 debugging."), _("\
3489 When on, AArch64 specific debugging is enabled."),
3492 &setdebuglist
, &showdebuglist
);
3495 selftests::register_test ("aarch64-analyze-prologue",
3496 selftests::aarch64_analyze_prologue_test
);
3497 selftests::register_test ("aarch64-process-record",
3498 selftests::aarch64_process_record_test
);
3502 /* AArch64 process record-replay related structures, defines etc. */
3504 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3507 unsigned int reg_len = LENGTH; \
3510 REGS = XNEWVEC (uint32_t, reg_len); \
3511 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3516 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3519 unsigned int mem_len = LENGTH; \
3522 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3523 memcpy(&MEMS->len, &RECORD_BUF[0], \
3524 sizeof(struct aarch64_mem_r) * LENGTH); \
3529 /* AArch64 record/replay structures and enumerations. */
3531 struct aarch64_mem_r
3533 uint64_t len
; /* Record length. */
3534 uint64_t addr
; /* Memory address. */
3537 enum aarch64_record_result
3539 AARCH64_RECORD_SUCCESS
,
3540 AARCH64_RECORD_UNSUPPORTED
,
3541 AARCH64_RECORD_UNKNOWN
3544 typedef struct insn_decode_record_t
3546 struct gdbarch
*gdbarch
;
3547 struct regcache
*regcache
;
3548 CORE_ADDR this_addr
; /* Address of insn to be recorded. */
3549 uint32_t aarch64_insn
; /* Insn to be recorded. */
3550 uint32_t mem_rec_count
; /* Count of memory records. */
3551 uint32_t reg_rec_count
; /* Count of register records. */
3552 uint32_t *aarch64_regs
; /* Registers to be recorded. */
3553 struct aarch64_mem_r
*aarch64_mems
; /* Memory locations to be recorded. */
3554 } insn_decode_record
;
3556 /* Record handler for data processing - register instructions. */
3559 aarch64_record_data_proc_reg (insn_decode_record
*aarch64_insn_r
)
3561 uint8_t reg_rd
, insn_bits24_27
, insn_bits21_23
;
3562 uint32_t record_buf
[4];
3564 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3565 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3566 insn_bits21_23
= bits (aarch64_insn_r
->aarch64_insn
, 21, 23);
3568 if (!bit (aarch64_insn_r
->aarch64_insn
, 28))
3572 /* Logical (shifted register). */
3573 if (insn_bits24_27
== 0x0a)
3574 setflags
= (bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03);
3576 else if (insn_bits24_27
== 0x0b)
3577 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3579 return AARCH64_RECORD_UNKNOWN
;
3581 record_buf
[0] = reg_rd
;
3582 aarch64_insn_r
->reg_rec_count
= 1;
3584 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3588 if (insn_bits24_27
== 0x0b)
3590 /* Data-processing (3 source). */
3591 record_buf
[0] = reg_rd
;
3592 aarch64_insn_r
->reg_rec_count
= 1;
3594 else if (insn_bits24_27
== 0x0a)
3596 if (insn_bits21_23
== 0x00)
3598 /* Add/subtract (with carry). */
3599 record_buf
[0] = reg_rd
;
3600 aarch64_insn_r
->reg_rec_count
= 1;
3601 if (bit (aarch64_insn_r
->aarch64_insn
, 29))
3603 record_buf
[1] = AARCH64_CPSR_REGNUM
;
3604 aarch64_insn_r
->reg_rec_count
= 2;
3607 else if (insn_bits21_23
== 0x02)
3609 /* Conditional compare (register) and conditional compare
3610 (immediate) instructions. */
3611 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3612 aarch64_insn_r
->reg_rec_count
= 1;
3614 else if (insn_bits21_23
== 0x04 || insn_bits21_23
== 0x06)
3616 /* Conditional select. */
3617 /* Data-processing (2 source). */
3618 /* Data-processing (1 source). */
3619 record_buf
[0] = reg_rd
;
3620 aarch64_insn_r
->reg_rec_count
= 1;
3623 return AARCH64_RECORD_UNKNOWN
;
3627 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3629 return AARCH64_RECORD_SUCCESS
;
3632 /* Record handler for data processing - immediate instructions. */
3635 aarch64_record_data_proc_imm (insn_decode_record
*aarch64_insn_r
)
3637 uint8_t reg_rd
, insn_bit23
, insn_bits24_27
, setflags
;
3638 uint32_t record_buf
[4];
3640 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3641 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3642 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3644 if (insn_bits24_27
== 0x00 /* PC rel addressing. */
3645 || insn_bits24_27
== 0x03 /* Bitfield and Extract. */
3646 || (insn_bits24_27
== 0x02 && insn_bit23
)) /* Move wide (immediate). */
3648 record_buf
[0] = reg_rd
;
3649 aarch64_insn_r
->reg_rec_count
= 1;
3651 else if (insn_bits24_27
== 0x01)
3653 /* Add/Subtract (immediate). */
3654 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3655 record_buf
[0] = reg_rd
;
3656 aarch64_insn_r
->reg_rec_count
= 1;
3658 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3660 else if (insn_bits24_27
== 0x02 && !insn_bit23
)
3662 /* Logical (immediate). */
3663 setflags
= bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03;
3664 record_buf
[0] = reg_rd
;
3665 aarch64_insn_r
->reg_rec_count
= 1;
3667 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3670 return AARCH64_RECORD_UNKNOWN
;
3672 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3674 return AARCH64_RECORD_SUCCESS
;
3677 /* Record handler for branch, exception generation and system instructions. */
3680 aarch64_record_branch_except_sys (insn_decode_record
*aarch64_insn_r
)
3682 struct gdbarch_tdep
*tdep
= gdbarch_tdep (aarch64_insn_r
->gdbarch
);
3683 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits22_23
;
3684 uint32_t record_buf
[4];
3686 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3687 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
3688 insn_bits22_23
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3690 if (insn_bits28_31
== 0x0d)
3692 /* Exception generation instructions. */
3693 if (insn_bits24_27
== 0x04)
3695 if (!bits (aarch64_insn_r
->aarch64_insn
, 2, 4)
3696 && !bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
3697 && bits (aarch64_insn_r
->aarch64_insn
, 0, 1) == 0x01)
3699 ULONGEST svc_number
;
3701 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, 8,
3703 return tdep
->aarch64_syscall_record (aarch64_insn_r
->regcache
,
3707 return AARCH64_RECORD_UNSUPPORTED
;
3709 /* System instructions. */
3710 else if (insn_bits24_27
== 0x05 && insn_bits22_23
== 0x00)
3712 uint32_t reg_rt
, reg_crn
;
3714 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3715 reg_crn
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3717 /* Record rt in case of sysl and mrs instructions. */
3718 if (bit (aarch64_insn_r
->aarch64_insn
, 21))
3720 record_buf
[0] = reg_rt
;
3721 aarch64_insn_r
->reg_rec_count
= 1;
3723 /* Record cpsr for hint and msr(immediate) instructions. */
3724 else if (reg_crn
== 0x02 || reg_crn
== 0x04)
3726 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3727 aarch64_insn_r
->reg_rec_count
= 1;
3730 /* Unconditional branch (register). */
3731 else if((insn_bits24_27
& 0x0e) == 0x06)
3733 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3734 if (bits (aarch64_insn_r
->aarch64_insn
, 21, 22) == 0x01)
3735 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3738 return AARCH64_RECORD_UNKNOWN
;
3740 /* Unconditional branch (immediate). */
3741 else if ((insn_bits28_31
& 0x07) == 0x01 && (insn_bits24_27
& 0x0c) == 0x04)
3743 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3744 if (bit (aarch64_insn_r
->aarch64_insn
, 31))
3745 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3748 /* Compare & branch (immediate), Test & branch (immediate) and
3749 Conditional branch (immediate). */
3750 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3752 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3754 return AARCH64_RECORD_SUCCESS
;
3757 /* Record handler for advanced SIMD load and store instructions. */
3760 aarch64_record_asimd_load_store (insn_decode_record
*aarch64_insn_r
)
3763 uint64_t addr_offset
= 0;
3764 uint32_t record_buf
[24];
3765 uint64_t record_buf_mem
[24];
3766 uint32_t reg_rn
, reg_rt
;
3767 uint32_t reg_index
= 0, mem_index
= 0;
3768 uint8_t opcode_bits
, size_bits
;
3770 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3771 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3772 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3773 opcode_bits
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3774 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
, &address
);
3777 debug_printf ("Process record: Advanced SIMD load/store\n");
3779 /* Load/store single structure. */
3780 if (bit (aarch64_insn_r
->aarch64_insn
, 24))
3782 uint8_t sindex
, scale
, selem
, esize
, replicate
= 0;
3783 scale
= opcode_bits
>> 2;
3784 selem
= ((opcode_bits
& 0x02) |
3785 bit (aarch64_insn_r
->aarch64_insn
, 21)) + 1;
3789 if (size_bits
& 0x01)
3790 return AARCH64_RECORD_UNKNOWN
;
3793 if ((size_bits
>> 1) & 0x01)
3794 return AARCH64_RECORD_UNKNOWN
;
3795 if (size_bits
& 0x01)
3797 if (!((opcode_bits
>> 1) & 0x01))
3800 return AARCH64_RECORD_UNKNOWN
;
3804 if (bit (aarch64_insn_r
->aarch64_insn
, 22) && !(opcode_bits
& 0x01))
3811 return AARCH64_RECORD_UNKNOWN
;
3817 for (sindex
= 0; sindex
< selem
; sindex
++)
3819 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3820 reg_rt
= (reg_rt
+ 1) % 32;
3824 for (sindex
= 0; sindex
< selem
; sindex
++)
3826 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3827 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3830 record_buf_mem
[mem_index
++] = esize
/ 8;
3831 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3833 addr_offset
= addr_offset
+ (esize
/ 8);
3834 reg_rt
= (reg_rt
+ 1) % 32;
3838 /* Load/store multiple structure. */
3841 uint8_t selem
, esize
, rpt
, elements
;
3842 uint8_t eindex
, rindex
;
3844 esize
= 8 << size_bits
;
3845 if (bit (aarch64_insn_r
->aarch64_insn
, 30))
3846 elements
= 128 / esize
;
3848 elements
= 64 / esize
;
3850 switch (opcode_bits
)
3852 /*LD/ST4 (4 Registers). */
3857 /*LD/ST1 (4 Registers). */
3862 /*LD/ST3 (3 Registers). */
3867 /*LD/ST1 (3 Registers). */
3872 /*LD/ST1 (1 Register). */
3877 /*LD/ST2 (2 Registers). */
3882 /*LD/ST1 (2 Registers). */
3888 return AARCH64_RECORD_UNSUPPORTED
;
3891 for (rindex
= 0; rindex
< rpt
; rindex
++)
3892 for (eindex
= 0; eindex
< elements
; eindex
++)
3894 uint8_t reg_tt
, sindex
;
3895 reg_tt
= (reg_rt
+ rindex
) % 32;
3896 for (sindex
= 0; sindex
< selem
; sindex
++)
3898 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3899 record_buf
[reg_index
++] = reg_tt
+ AARCH64_V0_REGNUM
;
3902 record_buf_mem
[mem_index
++] = esize
/ 8;
3903 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3905 addr_offset
= addr_offset
+ (esize
/ 8);
3906 reg_tt
= (reg_tt
+ 1) % 32;
3911 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
3912 record_buf
[reg_index
++] = reg_rn
;
3914 aarch64_insn_r
->reg_rec_count
= reg_index
;
3915 aarch64_insn_r
->mem_rec_count
= mem_index
/ 2;
3916 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
3918 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3920 return AARCH64_RECORD_SUCCESS
;
3923 /* Record handler for load and store instructions. */
3926 aarch64_record_load_store (insn_decode_record
*aarch64_insn_r
)
3928 uint8_t insn_bits24_27
, insn_bits28_29
, insn_bits10_11
;
3929 uint8_t insn_bit23
, insn_bit21
;
3930 uint8_t opc
, size_bits
, ld_flag
, vector_flag
;
3931 uint32_t reg_rn
, reg_rt
, reg_rt2
;
3932 uint64_t datasize
, offset
;
3933 uint32_t record_buf
[8];
3934 uint64_t record_buf_mem
[8];
3937 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3938 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3939 insn_bits28_29
= bits (aarch64_insn_r
->aarch64_insn
, 28, 29);
3940 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
3941 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3942 ld_flag
= bit (aarch64_insn_r
->aarch64_insn
, 22);
3943 vector_flag
= bit (aarch64_insn_r
->aarch64_insn
, 26);
3944 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3945 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3946 reg_rt2
= bits (aarch64_insn_r
->aarch64_insn
, 10, 14);
3947 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 30, 31);
3949 /* Load/store exclusive. */
3950 if (insn_bits24_27
== 0x08 && insn_bits28_29
== 0x00)
3953 debug_printf ("Process record: load/store exclusive\n");
3957 record_buf
[0] = reg_rt
;
3958 aarch64_insn_r
->reg_rec_count
= 1;
3961 record_buf
[1] = reg_rt2
;
3962 aarch64_insn_r
->reg_rec_count
= 2;
3968 datasize
= (8 << size_bits
) * 2;
3970 datasize
= (8 << size_bits
);
3971 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
3973 record_buf_mem
[0] = datasize
/ 8;
3974 record_buf_mem
[1] = address
;
3975 aarch64_insn_r
->mem_rec_count
= 1;
3978 /* Save register rs. */
3979 record_buf
[0] = bits (aarch64_insn_r
->aarch64_insn
, 16, 20);
3980 aarch64_insn_r
->reg_rec_count
= 1;
3984 /* Load register (literal) instructions decoding. */
3985 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x01)
3988 debug_printf ("Process record: load register (literal)\n");
3990 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
3992 record_buf
[0] = reg_rt
;
3993 aarch64_insn_r
->reg_rec_count
= 1;
3995 /* All types of load/store pair instructions decoding. */
3996 else if ((insn_bits24_27
& 0x0a) == 0x08 && insn_bits28_29
== 0x02)
3999 debug_printf ("Process record: load/store pair\n");
4005 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4006 record_buf
[1] = reg_rt2
+ AARCH64_V0_REGNUM
;
4010 record_buf
[0] = reg_rt
;
4011 record_buf
[1] = reg_rt2
;
4013 aarch64_insn_r
->reg_rec_count
= 2;
4018 imm7_off
= bits (aarch64_insn_r
->aarch64_insn
, 15, 21);
4020 size_bits
= size_bits
>> 1;
4021 datasize
= 8 << (2 + size_bits
);
4022 offset
= (imm7_off
& 0x40) ? (~imm7_off
& 0x007f) + 1 : imm7_off
;
4023 offset
= offset
<< (2 + size_bits
);
4024 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4026 if (!((insn_bits24_27
& 0x0b) == 0x08 && insn_bit23
))
4028 if (imm7_off
& 0x40)
4029 address
= address
- offset
;
4031 address
= address
+ offset
;
4034 record_buf_mem
[0] = datasize
/ 8;
4035 record_buf_mem
[1] = address
;
4036 record_buf_mem
[2] = datasize
/ 8;
4037 record_buf_mem
[3] = address
+ (datasize
/ 8);
4038 aarch64_insn_r
->mem_rec_count
= 2;
4040 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
4041 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
4043 /* Load/store register (unsigned immediate) instructions. */
4044 else if ((insn_bits24_27
& 0x0b) == 0x09 && insn_bits28_29
== 0x03)
4046 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4056 if (size_bits
== 0x3 && vector_flag
== 0x0 && opc
== 0x2)
4058 /* PRFM (immediate) */
4059 return AARCH64_RECORD_SUCCESS
;
4061 else if (size_bits
== 0x2 && vector_flag
== 0x0 && opc
== 0x2)
4063 /* LDRSW (immediate) */
4077 debug_printf ("Process record: load/store (unsigned immediate):"
4078 " size %x V %d opc %x\n", size_bits
, vector_flag
,
4084 offset
= bits (aarch64_insn_r
->aarch64_insn
, 10, 21);
4085 datasize
= 8 << size_bits
;
4086 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4088 offset
= offset
<< size_bits
;
4089 address
= address
+ offset
;
4091 record_buf_mem
[0] = datasize
>> 3;
4092 record_buf_mem
[1] = address
;
4093 aarch64_insn_r
->mem_rec_count
= 1;
4098 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4100 record_buf
[0] = reg_rt
;
4101 aarch64_insn_r
->reg_rec_count
= 1;
4104 /* Load/store register (register offset) instructions. */
4105 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
4106 && insn_bits10_11
== 0x02 && insn_bit21
)
4109 debug_printf ("Process record: load/store (register offset)\n");
4110 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4117 if (size_bits
!= 0x03)
4120 return AARCH64_RECORD_UNKNOWN
;
4124 ULONGEST reg_rm_val
;
4126 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
,
4127 bits (aarch64_insn_r
->aarch64_insn
, 16, 20), ®_rm_val
);
4128 if (bit (aarch64_insn_r
->aarch64_insn
, 12))
4129 offset
= reg_rm_val
<< size_bits
;
4131 offset
= reg_rm_val
;
4132 datasize
= 8 << size_bits
;
4133 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4135 address
= address
+ offset
;
4136 record_buf_mem
[0] = datasize
>> 3;
4137 record_buf_mem
[1] = address
;
4138 aarch64_insn_r
->mem_rec_count
= 1;
4143 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4145 record_buf
[0] = reg_rt
;
4146 aarch64_insn_r
->reg_rec_count
= 1;
4149 /* Load/store register (immediate and unprivileged) instructions. */
4150 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
4155 debug_printf ("Process record: load/store "
4156 "(immediate and unprivileged)\n");
4158 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4165 if (size_bits
!= 0x03)
4168 return AARCH64_RECORD_UNKNOWN
;
4173 imm9_off
= bits (aarch64_insn_r
->aarch64_insn
, 12, 20);
4174 offset
= (imm9_off
& 0x0100) ? (((~imm9_off
) & 0x01ff) + 1) : imm9_off
;
4175 datasize
= 8 << size_bits
;
4176 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4178 if (insn_bits10_11
!= 0x01)
4180 if (imm9_off
& 0x0100)
4181 address
= address
- offset
;
4183 address
= address
+ offset
;
4185 record_buf_mem
[0] = datasize
>> 3;
4186 record_buf_mem
[1] = address
;
4187 aarch64_insn_r
->mem_rec_count
= 1;
4192 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4194 record_buf
[0] = reg_rt
;
4195 aarch64_insn_r
->reg_rec_count
= 1;
4197 if (insn_bits10_11
== 0x01 || insn_bits10_11
== 0x03)
4198 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
4200 /* Advanced SIMD load/store instructions. */
4202 return aarch64_record_asimd_load_store (aarch64_insn_r
);
4204 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
4206 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4208 return AARCH64_RECORD_SUCCESS
;
4211 /* Record handler for data processing SIMD and floating point instructions. */
4214 aarch64_record_data_proc_simd_fp (insn_decode_record
*aarch64_insn_r
)
4216 uint8_t insn_bit21
, opcode
, rmode
, reg_rd
;
4217 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits10_11
, insn_bits12_15
;
4218 uint8_t insn_bits11_14
;
4219 uint32_t record_buf
[2];
4221 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
4222 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
4223 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
4224 insn_bits12_15
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
4225 insn_bits11_14
= bits (aarch64_insn_r
->aarch64_insn
, 11, 14);
4226 opcode
= bits (aarch64_insn_r
->aarch64_insn
, 16, 18);
4227 rmode
= bits (aarch64_insn_r
->aarch64_insn
, 19, 20);
4228 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
4229 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
4232 debug_printf ("Process record: data processing SIMD/FP: ");
4234 if ((insn_bits28_31
& 0x05) == 0x01 && insn_bits24_27
== 0x0e)
4236 /* Floating point - fixed point conversion instructions. */
4240 debug_printf ("FP - fixed point conversion");
4242 if ((opcode
>> 1) == 0x0 && rmode
== 0x03)
4243 record_buf
[0] = reg_rd
;
4245 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4247 /* Floating point - conditional compare instructions. */
4248 else if (insn_bits10_11
== 0x01)
4251 debug_printf ("FP - conditional compare");
4253 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4255 /* Floating point - data processing (2-source) and
4256 conditional select instructions. */
4257 else if (insn_bits10_11
== 0x02 || insn_bits10_11
== 0x03)
4260 debug_printf ("FP - DP (2-source)");
4262 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4264 else if (insn_bits10_11
== 0x00)
4266 /* Floating point - immediate instructions. */
4267 if ((insn_bits12_15
& 0x01) == 0x01
4268 || (insn_bits12_15
& 0x07) == 0x04)
4271 debug_printf ("FP - immediate");
4272 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4274 /* Floating point - compare instructions. */
4275 else if ((insn_bits12_15
& 0x03) == 0x02)
4278 debug_printf ("FP - immediate");
4279 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4281 /* Floating point - integer conversions instructions. */
4282 else if (insn_bits12_15
== 0x00)
4284 /* Convert float to integer instruction. */
4285 if (!(opcode
>> 1) || ((opcode
>> 1) == 0x02 && !rmode
))
4288 debug_printf ("float to int conversion");
4290 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4292 /* Convert integer to float instruction. */
4293 else if ((opcode
>> 1) == 0x01 && !rmode
)
4296 debug_printf ("int to float conversion");
4298 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4300 /* Move float to integer instruction. */
4301 else if ((opcode
>> 1) == 0x03)
4304 debug_printf ("move float to int");
4306 if (!(opcode
& 0x01))
4307 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4309 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4312 return AARCH64_RECORD_UNKNOWN
;
4315 return AARCH64_RECORD_UNKNOWN
;
4318 return AARCH64_RECORD_UNKNOWN
;
4320 else if ((insn_bits28_31
& 0x09) == 0x00 && insn_bits24_27
== 0x0e)
4323 debug_printf ("SIMD copy");
4325 /* Advanced SIMD copy instructions. */
4326 if (!bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
4327 && !bit (aarch64_insn_r
->aarch64_insn
, 15)
4328 && bit (aarch64_insn_r
->aarch64_insn
, 10))
4330 if (insn_bits11_14
== 0x05 || insn_bits11_14
== 0x07)
4331 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4333 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4336 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4338 /* All remaining floating point or advanced SIMD instructions. */
4342 debug_printf ("all remain");
4344 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4348 debug_printf ("\n");
4350 aarch64_insn_r
->reg_rec_count
++;
4351 gdb_assert (aarch64_insn_r
->reg_rec_count
== 1);
4352 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4354 return AARCH64_RECORD_SUCCESS
;
4357 /* Decodes insns type and invokes its record handler. */
4360 aarch64_record_decode_insn_handler (insn_decode_record
*aarch64_insn_r
)
4362 uint32_t ins_bit25
, ins_bit26
, ins_bit27
, ins_bit28
;
4364 ins_bit25
= bit (aarch64_insn_r
->aarch64_insn
, 25);
4365 ins_bit26
= bit (aarch64_insn_r
->aarch64_insn
, 26);
4366 ins_bit27
= bit (aarch64_insn_r
->aarch64_insn
, 27);
4367 ins_bit28
= bit (aarch64_insn_r
->aarch64_insn
, 28);
4369 /* Data processing - immediate instructions. */
4370 if (!ins_bit26
&& !ins_bit27
&& ins_bit28
)
4371 return aarch64_record_data_proc_imm (aarch64_insn_r
);
4373 /* Branch, exception generation and system instructions. */
4374 if (ins_bit26
&& !ins_bit27
&& ins_bit28
)
4375 return aarch64_record_branch_except_sys (aarch64_insn_r
);
4377 /* Load and store instructions. */
4378 if (!ins_bit25
&& ins_bit27
)
4379 return aarch64_record_load_store (aarch64_insn_r
);
4381 /* Data processing - register instructions. */
4382 if (ins_bit25
&& !ins_bit26
&& ins_bit27
)
4383 return aarch64_record_data_proc_reg (aarch64_insn_r
);
4385 /* Data processing - SIMD and floating point instructions. */
4386 if (ins_bit25
&& ins_bit26
&& ins_bit27
)
4387 return aarch64_record_data_proc_simd_fp (aarch64_insn_r
);
4389 return AARCH64_RECORD_UNSUPPORTED
;
4392 /* Cleans up local record registers and memory allocations. */
4395 deallocate_reg_mem (insn_decode_record
*record
)
4397 xfree (record
->aarch64_regs
);
4398 xfree (record
->aarch64_mems
);
4402 namespace selftests
{
4405 aarch64_process_record_test (void)
4407 struct gdbarch_info info
;
4410 gdbarch_info_init (&info
);
4411 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
4413 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
4414 SELF_CHECK (gdbarch
!= NULL
);
4416 insn_decode_record aarch64_record
;
4418 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4419 aarch64_record
.regcache
= NULL
;
4420 aarch64_record
.this_addr
= 0;
4421 aarch64_record
.gdbarch
= gdbarch
;
4423 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4424 aarch64_record
.aarch64_insn
= 0xf9800020;
4425 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4426 SELF_CHECK (ret
== AARCH64_RECORD_SUCCESS
);
4427 SELF_CHECK (aarch64_record
.reg_rec_count
== 0);
4428 SELF_CHECK (aarch64_record
.mem_rec_count
== 0);
4430 deallocate_reg_mem (&aarch64_record
);
4433 } // namespace selftests
4434 #endif /* GDB_SELF_TEST */
4436 /* Parse the current instruction and record the values of the registers and
4437 memory that will be changed in current instruction to record_arch_list
4438 return -1 if something is wrong. */
4441 aarch64_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4442 CORE_ADDR insn_addr
)
4444 uint32_t rec_no
= 0;
4445 uint8_t insn_size
= 4;
4447 gdb_byte buf
[insn_size
];
4448 insn_decode_record aarch64_record
;
4450 memset (&buf
[0], 0, insn_size
);
4451 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4452 target_read_memory (insn_addr
, &buf
[0], insn_size
);
4453 aarch64_record
.aarch64_insn
4454 = (uint32_t) extract_unsigned_integer (&buf
[0],
4456 gdbarch_byte_order (gdbarch
));
4457 aarch64_record
.regcache
= regcache
;
4458 aarch64_record
.this_addr
= insn_addr
;
4459 aarch64_record
.gdbarch
= gdbarch
;
4461 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4462 if (ret
== AARCH64_RECORD_UNSUPPORTED
)
4464 printf_unfiltered (_("Process record does not support instruction "
4465 "0x%0x at address %s.\n"),
4466 aarch64_record
.aarch64_insn
,
4467 paddress (gdbarch
, insn_addr
));
4473 /* Record registers. */
4474 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4476 /* Always record register CPSR. */
4477 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4478 AARCH64_CPSR_REGNUM
);
4479 if (aarch64_record
.aarch64_regs
)
4480 for (rec_no
= 0; rec_no
< aarch64_record
.reg_rec_count
; rec_no
++)
4481 if (record_full_arch_list_add_reg (aarch64_record
.regcache
,
4482 aarch64_record
.aarch64_regs
[rec_no
]))
4485 /* Record memories. */
4486 if (aarch64_record
.aarch64_mems
)
4487 for (rec_no
= 0; rec_no
< aarch64_record
.mem_rec_count
; rec_no
++)
4488 if (record_full_arch_list_add_mem
4489 ((CORE_ADDR
)aarch64_record
.aarch64_mems
[rec_no
].addr
,
4490 aarch64_record
.aarch64_mems
[rec_no
].len
))
4493 if (record_full_arch_list_add_end ())
4497 deallocate_reg_mem (&aarch64_record
);