1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2017 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #ifndef AARCH64_TDEP_H
23 #define AARCH64_TDEP_H
25 /* Forward declarations. */
29 /* AArch64 Dwarf register numbering. */
30 #define AARCH64_DWARF_X0 0
31 #define AARCH64_DWARF_SP 31
32 #define AARCH64_DWARF_V0 64
34 /* Register numbers of various important registers. */
37 AARCH64_X0_REGNUM
, /* First integer register */
39 /* Frame register in AArch64 code, if used. */
40 AARCH64_FP_REGNUM
= AARCH64_X0_REGNUM
+ 29,
41 AARCH64_LR_REGNUM
= AARCH64_X0_REGNUM
+ 30, /* Return address */
42 AARCH64_SP_REGNUM
, /* Stack pointer */
43 AARCH64_PC_REGNUM
, /* Program counter */
44 AARCH64_CPSR_REGNUM
, /* Contains status register */
45 AARCH64_V0_REGNUM
, /* First floating point / vector register */
47 /* Last floating point / vector register */
48 AARCH64_V31_REGNUM
= AARCH64_V0_REGNUM
+ 31,
49 AARCH64_FPSR_REGNUM
, /* Floating point status register */
50 AARCH64_FPCR_REGNUM
, /* Floating point control register */
52 /* Other useful registers. */
54 /* Last integer-like argument */
55 AARCH64_LAST_X_ARG_REGNUM
= AARCH64_X0_REGNUM
+ 7,
56 AARCH64_STRUCT_RETURN_REGNUM
= AARCH64_X0_REGNUM
+ 8,
57 AARCH64_LAST_V_ARG_REGNUM
= AARCH64_V0_REGNUM
+ 7
60 /* Size of integer registers. */
61 #define X_REGISTER_SIZE 8
62 #define B_REGISTER_SIZE 1
63 #define H_REGISTER_SIZE 2
64 #define S_REGISTER_SIZE 4
65 #define D_REGISTER_SIZE 8
66 #define V_REGISTER_SIZE 16
67 #define Q_REGISTER_SIZE 16
69 /* Total number of general (X) registers. */
70 #define AARCH64_X_REGISTER_COUNT 32
71 /* Total number of D registers. */
72 #define AARCH64_D_REGISTER_COUNT 32
74 /* The maximum number of modified instructions generated for one
75 single-stepped instruction. */
76 #define DISPLACED_MODIFIED_INSNS 1
78 /* Target-dependent structure in gdbarch. */
81 /* Lowest address at which instructions will appear. */
84 /* Offset to PC value in jump buffer. If this is negative, longjmp
85 support will be disabled. */
88 /* And the size of each entry in the buf. */
91 /* Types for AdvSISD registers. */
92 struct type
*vnq_type
;
93 struct type
*vnd_type
;
94 struct type
*vns_type
;
95 struct type
*vnh_type
;
96 struct type
*vnb_type
;
99 int (*aarch64_syscall_record
) (struct regcache
*regcache
, unsigned long svc_number
);
102 extern struct target_desc
*tdesc_aarch64
;
104 extern int aarch64_process_record (struct gdbarch
*gdbarch
,
105 struct regcache
*regcache
, CORE_ADDR addr
);
107 struct displaced_step_closure
*
108 aarch64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
109 CORE_ADDR from
, CORE_ADDR to
,
110 struct regcache
*regs
);
112 void aarch64_displaced_step_fixup (struct gdbarch
*gdbarch
,
113 struct displaced_step_closure
*dsc
,
114 CORE_ADDR from
, CORE_ADDR to
,
115 struct regcache
*regs
);
117 int aarch64_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
118 struct displaced_step_closure
*closure
);
120 #endif /* aarch64-tdep.h */