1 /* Target-dependent code for the ALPHA architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1993-2019 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 /* Standard C++ includes. */
25 /* Local non-gdb includes. */
26 #include "alpha-tdep.h"
27 #include "arch-utils.h"
30 #include "dwarf2-frame.h"
32 #include "frame-base.h"
33 #include "frame-unwind.h"
43 #include "reggroups.h"
46 #include "trad-frame.h"
49 /* Instruction decoding. The notations for registers, immediates and
50 opcodes are the same as the one used in Compaq's Alpha architecture
53 #define INSN_OPCODE(insn) ((insn & 0xfc000000) >> 26)
55 /* Memory instruction format */
56 #define MEM_RA(insn) ((insn & 0x03e00000) >> 21)
57 #define MEM_RB(insn) ((insn & 0x001f0000) >> 16)
58 #define MEM_DISP(insn) \
59 (((insn & 0x8000) == 0) ? (insn & 0xffff) : -((-insn) & 0xffff))
61 static const int lda_opcode
= 0x08;
62 static const int stq_opcode
= 0x2d;
64 /* Branch instruction format */
65 #define BR_RA(insn) MEM_RA(insn)
67 static const int br_opcode
= 0x30;
68 static const int bne_opcode
= 0x3d;
70 /* Operate instruction format */
71 #define OPR_FUNCTION(insn) ((insn & 0xfe0) >> 5)
72 #define OPR_HAS_IMMEDIATE(insn) ((insn & 0x1000) == 0x1000)
73 #define OPR_RA(insn) MEM_RA(insn)
74 #define OPR_RC(insn) ((insn & 0x1f))
75 #define OPR_LIT(insn) ((insn & 0x1fe000) >> 13)
77 static const int subq_opcode
= 0x10;
78 static const int subq_function
= 0x29;
81 /* Return the name of the REGNO register.
83 An empty name corresponds to a register number that used to
84 be used for a virtual register. That virtual register has
85 been removed, but the index is still reserved to maintain
86 compatibility with existing remote alpha targets. */
89 alpha_register_name (struct gdbarch
*gdbarch
, int regno
)
91 static const char * const register_names
[] =
93 "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
94 "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
95 "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
96 "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero",
97 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
98 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
99 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
100 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "fpcr",
106 if (regno
>= ARRAY_SIZE(register_names
))
108 return register_names
[regno
];
112 alpha_cannot_fetch_register (struct gdbarch
*gdbarch
, int regno
)
114 return (strlen (alpha_register_name (gdbarch
, regno
)) == 0);
118 alpha_cannot_store_register (struct gdbarch
*gdbarch
, int regno
)
120 return (regno
== ALPHA_ZERO_REGNUM
121 || strlen (alpha_register_name (gdbarch
, regno
)) == 0);
125 alpha_register_type (struct gdbarch
*gdbarch
, int regno
)
127 if (regno
== ALPHA_SP_REGNUM
|| regno
== ALPHA_GP_REGNUM
)
128 return builtin_type (gdbarch
)->builtin_data_ptr
;
129 if (regno
== ALPHA_PC_REGNUM
)
130 return builtin_type (gdbarch
)->builtin_func_ptr
;
132 /* Don't need to worry about little vs big endian until
133 some jerk tries to port to alpha-unicosmk. */
134 if (regno
>= ALPHA_FP0_REGNUM
&& regno
< ALPHA_FP0_REGNUM
+ 31)
135 return builtin_type (gdbarch
)->builtin_double
;
137 return builtin_type (gdbarch
)->builtin_int64
;
140 /* Is REGNUM a member of REGGROUP? */
143 alpha_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
144 struct reggroup
*group
)
146 /* Filter out any registers eliminated, but whose regnum is
147 reserved for backward compatibility, e.g. the vfp. */
148 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
149 || *gdbarch_register_name (gdbarch
, regnum
) == '\0')
152 if (group
== all_reggroup
)
155 /* Zero should not be saved or restored. Technically it is a general
156 register (just as $f31 would be a float if we represented it), but
157 there's no point displaying it during "info regs", so leave it out
158 of all groups except for "all". */
159 if (regnum
== ALPHA_ZERO_REGNUM
)
162 /* All other registers are saved and restored. */
163 if (group
== save_reggroup
|| group
== restore_reggroup
)
166 /* All other groups are non-overlapping. */
168 /* Since this is really a PALcode memory slot... */
169 if (regnum
== ALPHA_UNIQUE_REGNUM
)
170 return group
== system_reggroup
;
172 /* Force the FPCR to be considered part of the floating point state. */
173 if (regnum
== ALPHA_FPCR_REGNUM
)
174 return group
== float_reggroup
;
176 if (regnum
>= ALPHA_FP0_REGNUM
&& regnum
< ALPHA_FP0_REGNUM
+ 31)
177 return group
== float_reggroup
;
179 return group
== general_reggroup
;
182 /* The following represents exactly the conversion performed by
183 the LDS instruction. This applies to both single-precision
184 floating point and 32-bit integers. */
187 alpha_lds (struct gdbarch
*gdbarch
, void *out
, const void *in
)
189 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
191 = extract_unsigned_integer ((const gdb_byte
*) in
, 4, byte_order
);
192 ULONGEST frac
= (mem
>> 0) & 0x7fffff;
193 ULONGEST sign
= (mem
>> 31) & 1;
194 ULONGEST exp_msb
= (mem
>> 30) & 1;
195 ULONGEST exp_low
= (mem
>> 23) & 0x7f;
198 exp
= (exp_msb
<< 10) | exp_low
;
210 reg
= (sign
<< 63) | (exp
<< 52) | (frac
<< 29);
211 store_unsigned_integer ((gdb_byte
*) out
, 8, byte_order
, reg
);
214 /* Similarly, this represents exactly the conversion performed by
215 the STS instruction. */
218 alpha_sts (struct gdbarch
*gdbarch
, void *out
, const void *in
)
220 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
223 reg
= extract_unsigned_integer ((const gdb_byte
*) in
, 8, byte_order
);
224 mem
= ((reg
>> 32) & 0xc0000000) | ((reg
>> 29) & 0x3fffffff);
225 store_unsigned_integer ((gdb_byte
*) out
, 4, byte_order
, mem
);
228 /* The alpha needs a conversion between register and memory format if the
229 register is a floating point register and memory format is float, as the
230 register format must be double or memory format is an integer with 4
231 bytes, as the representation of integers in floating point
232 registers is different. */
235 alpha_convert_register_p (struct gdbarch
*gdbarch
, int regno
,
238 return (regno
>= ALPHA_FP0_REGNUM
&& regno
< ALPHA_FP0_REGNUM
+ 31
239 && TYPE_LENGTH (type
) == 4);
243 alpha_register_to_value (struct frame_info
*frame
, int regnum
,
244 struct type
*valtype
, gdb_byte
*out
,
245 int *optimizedp
, int *unavailablep
)
247 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
248 struct value
*value
= get_frame_register_value (frame
, regnum
);
250 gdb_assert (value
!= NULL
);
251 *optimizedp
= value_optimized_out (value
);
252 *unavailablep
= !value_entirely_available (value
);
254 if (*optimizedp
|| *unavailablep
)
256 release_value (value
);
260 /* Convert to VALTYPE. */
262 gdb_assert (TYPE_LENGTH (valtype
) == 4);
263 alpha_sts (gdbarch
, out
, value_contents_all (value
));
265 release_value (value
);
270 alpha_value_to_register (struct frame_info
*frame
, int regnum
,
271 struct type
*valtype
, const gdb_byte
*in
)
273 gdb_byte out
[ALPHA_REGISTER_SIZE
];
275 gdb_assert (TYPE_LENGTH (valtype
) == 4);
276 gdb_assert (register_size (get_frame_arch (frame
), regnum
)
277 <= ALPHA_REGISTER_SIZE
);
278 alpha_lds (get_frame_arch (frame
), out
, in
);
280 put_frame_register (frame
, regnum
, out
);
284 /* The alpha passes the first six arguments in the registers, the rest on
285 the stack. The register arguments are stored in ARG_REG_BUFFER, and
286 then moved into the register file; this simplifies the passing of a
287 large struct which extends from the registers to the stack, plus avoids
288 three ptrace invocations per word.
290 We don't bother tracking which register values should go in integer
291 regs or fp regs; we load the same values into both.
293 If the called function is returning a structure, the address of the
294 structure to be returned is passed as a hidden first argument. */
297 alpha_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
298 struct regcache
*regcache
, CORE_ADDR bp_addr
,
299 int nargs
, struct value
**args
, CORE_ADDR sp
,
300 function_call_return_method return_method
,
301 CORE_ADDR struct_addr
)
303 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
305 int accumulate_size
= (return_method
== return_method_struct
) ? 8 : 0;
308 const gdb_byte
*contents
;
312 struct alpha_arg
*alpha_args
= XALLOCAVEC (struct alpha_arg
, nargs
);
313 struct alpha_arg
*m_arg
;
314 gdb_byte arg_reg_buffer
[ALPHA_REGISTER_SIZE
* ALPHA_NUM_ARG_REGS
];
315 int required_arg_regs
;
316 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
318 /* The ABI places the address of the called function in T12. */
319 regcache_cooked_write_signed (regcache
, ALPHA_T12_REGNUM
, func_addr
);
321 /* Set the return address register to point to the entry point
322 of the program, where a breakpoint lies in wait. */
323 regcache_cooked_write_signed (regcache
, ALPHA_RA_REGNUM
, bp_addr
);
325 /* Lay out the arguments in memory. */
326 for (i
= 0, m_arg
= alpha_args
; i
< nargs
; i
++, m_arg
++)
328 struct value
*arg
= args
[i
];
329 struct type
*arg_type
= check_typedef (value_type (arg
));
331 /* Cast argument to long if necessary as the compiler does it too. */
332 switch (TYPE_CODE (arg_type
))
337 case TYPE_CODE_RANGE
:
339 if (TYPE_LENGTH (arg_type
) == 4)
341 /* 32-bit values must be sign-extended to 64 bits
342 even if the base data type is unsigned. */
343 arg_type
= builtin_type (gdbarch
)->builtin_int32
;
344 arg
= value_cast (arg_type
, arg
);
346 if (TYPE_LENGTH (arg_type
) < ALPHA_REGISTER_SIZE
)
348 arg_type
= builtin_type (gdbarch
)->builtin_int64
;
349 arg
= value_cast (arg_type
, arg
);
354 /* "float" arguments loaded in registers must be passed in
355 register format, aka "double". */
356 if (accumulate_size
< sizeof (arg_reg_buffer
)
357 && TYPE_LENGTH (arg_type
) == 4)
359 arg_type
= builtin_type (gdbarch
)->builtin_double
;
360 arg
= value_cast (arg_type
, arg
);
362 /* Tru64 5.1 has a 128-bit long double, and passes this by
363 invisible reference. No one else uses this data type. */
364 else if (TYPE_LENGTH (arg_type
) == 16)
366 /* Allocate aligned storage. */
367 sp
= (sp
& -16) - 16;
369 /* Write the real data into the stack. */
370 write_memory (sp
, value_contents (arg
), 16);
372 /* Construct the indirection. */
373 arg_type
= lookup_pointer_type (arg_type
);
374 arg
= value_from_pointer (arg_type
, sp
);
378 case TYPE_CODE_COMPLEX
:
379 /* ??? The ABI says that complex values are passed as two
380 separate scalar values. This distinction only matters
381 for complex float. However, GCC does not implement this. */
383 /* Tru64 5.1 has a 128-bit long double, and passes this by
384 invisible reference. */
385 if (TYPE_LENGTH (arg_type
) == 32)
387 /* Allocate aligned storage. */
388 sp
= (sp
& -16) - 16;
390 /* Write the real data into the stack. */
391 write_memory (sp
, value_contents (arg
), 32);
393 /* Construct the indirection. */
394 arg_type
= lookup_pointer_type (arg_type
);
395 arg
= value_from_pointer (arg_type
, sp
);
402 m_arg
->len
= TYPE_LENGTH (arg_type
);
403 m_arg
->offset
= accumulate_size
;
404 accumulate_size
= (accumulate_size
+ m_arg
->len
+ 7) & ~7;
405 m_arg
->contents
= value_contents (arg
);
408 /* Determine required argument register loads, loading an argument register
409 is expensive as it uses three ptrace calls. */
410 required_arg_regs
= accumulate_size
/ 8;
411 if (required_arg_regs
> ALPHA_NUM_ARG_REGS
)
412 required_arg_regs
= ALPHA_NUM_ARG_REGS
;
414 /* Make room for the arguments on the stack. */
415 if (accumulate_size
< sizeof(arg_reg_buffer
))
418 accumulate_size
-= sizeof(arg_reg_buffer
);
419 sp
-= accumulate_size
;
421 /* Keep sp aligned to a multiple of 16 as the ABI requires. */
424 /* `Push' arguments on the stack. */
425 for (i
= nargs
; m_arg
--, --i
>= 0;)
427 const gdb_byte
*contents
= m_arg
->contents
;
428 int offset
= m_arg
->offset
;
429 int len
= m_arg
->len
;
431 /* Copy the bytes destined for registers into arg_reg_buffer. */
432 if (offset
< sizeof(arg_reg_buffer
))
434 if (offset
+ len
<= sizeof(arg_reg_buffer
))
436 memcpy (arg_reg_buffer
+ offset
, contents
, len
);
441 int tlen
= sizeof(arg_reg_buffer
) - offset
;
442 memcpy (arg_reg_buffer
+ offset
, contents
, tlen
);
449 /* Everything else goes to the stack. */
450 write_memory (sp
+ offset
- sizeof(arg_reg_buffer
), contents
, len
);
452 if (return_method
== return_method_struct
)
453 store_unsigned_integer (arg_reg_buffer
, ALPHA_REGISTER_SIZE
,
454 byte_order
, struct_addr
);
456 /* Load the argument registers. */
457 for (i
= 0; i
< required_arg_regs
; i
++)
459 regcache
->cooked_write (ALPHA_A0_REGNUM
+ i
,
460 arg_reg_buffer
+ i
* ALPHA_REGISTER_SIZE
);
461 regcache
->cooked_write (ALPHA_FPA0_REGNUM
+ i
,
462 arg_reg_buffer
+ i
* ALPHA_REGISTER_SIZE
);
465 /* Finally, update the stack pointer. */
466 regcache_cooked_write_signed (regcache
, ALPHA_SP_REGNUM
, sp
);
471 /* Extract from REGCACHE the value about to be returned from a function
472 and copy it into VALBUF. */
475 alpha_extract_return_value (struct type
*valtype
, struct regcache
*regcache
,
478 struct gdbarch
*gdbarch
= regcache
->arch ();
479 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
480 gdb_byte raw_buffer
[ALPHA_REGISTER_SIZE
];
483 switch (TYPE_CODE (valtype
))
486 switch (TYPE_LENGTH (valtype
))
489 regcache
->cooked_read (ALPHA_FP0_REGNUM
, raw_buffer
);
490 alpha_sts (gdbarch
, valbuf
, raw_buffer
);
494 regcache
->cooked_read (ALPHA_FP0_REGNUM
, valbuf
);
498 regcache_cooked_read_unsigned (regcache
, ALPHA_V0_REGNUM
, &l
);
499 read_memory (l
, valbuf
, 16);
503 internal_error (__FILE__
, __LINE__
,
504 _("unknown floating point width"));
508 case TYPE_CODE_COMPLEX
:
509 switch (TYPE_LENGTH (valtype
))
512 /* ??? This isn't correct wrt the ABI, but it's what GCC does. */
513 regcache
->cooked_read (ALPHA_FP0_REGNUM
, valbuf
);
517 regcache
->cooked_read (ALPHA_FP0_REGNUM
, valbuf
);
518 regcache
->cooked_read (ALPHA_FP0_REGNUM
+ 1, valbuf
+ 8);
522 regcache_cooked_read_unsigned (regcache
, ALPHA_V0_REGNUM
, &l
);
523 read_memory (l
, valbuf
, 32);
527 internal_error (__FILE__
, __LINE__
,
528 _("unknown floating point width"));
533 /* Assume everything else degenerates to an integer. */
534 regcache_cooked_read_unsigned (regcache
, ALPHA_V0_REGNUM
, &l
);
535 store_unsigned_integer (valbuf
, TYPE_LENGTH (valtype
), byte_order
, l
);
540 /* Insert the given value into REGCACHE as if it was being
541 returned by a function. */
544 alpha_store_return_value (struct type
*valtype
, struct regcache
*regcache
,
545 const gdb_byte
*valbuf
)
547 struct gdbarch
*gdbarch
= regcache
->arch ();
548 gdb_byte raw_buffer
[ALPHA_REGISTER_SIZE
];
551 switch (TYPE_CODE (valtype
))
554 switch (TYPE_LENGTH (valtype
))
557 alpha_lds (gdbarch
, raw_buffer
, valbuf
);
558 regcache
->cooked_write (ALPHA_FP0_REGNUM
, raw_buffer
);
562 regcache
->cooked_write (ALPHA_FP0_REGNUM
, valbuf
);
566 /* FIXME: 128-bit long doubles are returned like structures:
567 by writing into indirect storage provided by the caller
568 as the first argument. */
569 error (_("Cannot set a 128-bit long double return value."));
572 internal_error (__FILE__
, __LINE__
,
573 _("unknown floating point width"));
577 case TYPE_CODE_COMPLEX
:
578 switch (TYPE_LENGTH (valtype
))
581 /* ??? This isn't correct wrt the ABI, but it's what GCC does. */
582 regcache
->cooked_write (ALPHA_FP0_REGNUM
, valbuf
);
586 regcache
->cooked_write (ALPHA_FP0_REGNUM
, valbuf
);
587 regcache
->cooked_write (ALPHA_FP0_REGNUM
+ 1, valbuf
+ 8);
591 /* FIXME: 128-bit long doubles are returned like structures:
592 by writing into indirect storage provided by the caller
593 as the first argument. */
594 error (_("Cannot set a 128-bit long double return value."));
597 internal_error (__FILE__
, __LINE__
,
598 _("unknown floating point width"));
603 /* Assume everything else degenerates to an integer. */
604 /* 32-bit values must be sign-extended to 64 bits
605 even if the base data type is unsigned. */
606 if (TYPE_LENGTH (valtype
) == 4)
607 valtype
= builtin_type (gdbarch
)->builtin_int32
;
608 l
= unpack_long (valtype
, valbuf
);
609 regcache_cooked_write_unsigned (regcache
, ALPHA_V0_REGNUM
, l
);
614 static enum return_value_convention
615 alpha_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
616 struct type
*type
, struct regcache
*regcache
,
617 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
619 enum type_code code
= TYPE_CODE (type
);
621 if ((code
== TYPE_CODE_STRUCT
622 || code
== TYPE_CODE_UNION
623 || code
== TYPE_CODE_ARRAY
)
624 && gdbarch_tdep (gdbarch
)->return_in_memory (type
))
629 regcache_raw_read_unsigned (regcache
, ALPHA_V0_REGNUM
, &addr
);
630 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
633 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
637 alpha_extract_return_value (type
, regcache
, readbuf
);
639 alpha_store_return_value (type
, regcache
, writebuf
);
641 return RETURN_VALUE_REGISTER_CONVENTION
;
645 alpha_return_in_memory_always (struct type
*type
)
651 constexpr gdb_byte alpha_break_insn
[] = { 0x80, 0, 0, 0 }; /* call_pal bpt */
653 typedef BP_MANIPULATION (alpha_break_insn
) alpha_breakpoint
;
656 /* This returns the PC of the first insn after the prologue.
657 If we can't find the prologue, then return 0. */
660 alpha_after_prologue (CORE_ADDR pc
)
662 struct symtab_and_line sal
;
663 CORE_ADDR func_addr
, func_end
;
665 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
668 sal
= find_pc_line (func_addr
, 0);
669 if (sal
.end
< func_end
)
672 /* The line after the prologue is after the end of the function. In this
673 case, tell the caller to find the prologue the hard way. */
677 /* Read an instruction from memory at PC, looking through breakpoints. */
680 alpha_read_insn (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
682 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
683 gdb_byte buf
[ALPHA_INSN_SIZE
];
686 res
= target_read_memory (pc
, buf
, sizeof (buf
));
688 memory_error (TARGET_XFER_E_IO
, pc
);
689 return extract_unsigned_integer (buf
, sizeof (buf
), byte_order
);
692 /* To skip prologues, I use this predicate. Returns either PC itself
693 if the code at PC does not look like a function prologue; otherwise
694 returns an address that (if we're lucky) follows the prologue. If
695 LENIENT, then we must skip everything which is involved in setting
696 up the frame (it's OK to skip more, just so long as we don't skip
697 anything which might clobber the registers which are being saved. */
700 alpha_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
704 CORE_ADDR post_prologue_pc
;
705 gdb_byte buf
[ALPHA_INSN_SIZE
];
707 /* Silently return the unaltered pc upon memory errors.
708 This could happen on OSF/1 if decode_line_1 tries to skip the
709 prologue for quickstarted shared library functions when the
710 shared library is not yet mapped in.
711 Reading target memory is slow over serial lines, so we perform
712 this check only if the target has shared libraries (which all
713 Alpha targets do). */
714 if (target_read_memory (pc
, buf
, sizeof (buf
)))
717 /* See if we can determine the end of the prologue via the symbol table.
718 If so, then return either PC, or the PC after the prologue, whichever
721 post_prologue_pc
= alpha_after_prologue (pc
);
722 if (post_prologue_pc
!= 0)
723 return std::max (pc
, post_prologue_pc
);
725 /* Can't determine prologue from the symbol table, need to examine
728 /* Skip the typical prologue instructions. These are the stack adjustment
729 instruction and the instructions that save registers on the stack
730 or in the gcc frame. */
731 for (offset
= 0; offset
< 100; offset
+= ALPHA_INSN_SIZE
)
733 inst
= alpha_read_insn (gdbarch
, pc
+ offset
);
735 if ((inst
& 0xffff0000) == 0x27bb0000) /* ldah $gp,n($t12) */
737 if ((inst
& 0xffff0000) == 0x23bd0000) /* lda $gp,n($gp) */
739 if ((inst
& 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */
741 if ((inst
& 0xffe01fff) == 0x43c0153e) /* subq $sp,n,$sp */
744 if (((inst
& 0xfc1f0000) == 0xb41e0000 /* stq reg,n($sp) */
745 || (inst
& 0xfc1f0000) == 0x9c1e0000) /* stt reg,n($sp) */
746 && (inst
& 0x03e00000) != 0x03e00000) /* reg != $zero */
749 if (inst
== 0x47de040f) /* bis sp,sp,fp */
751 if (inst
== 0x47fe040f) /* bis zero,sp,fp */
760 static const int ldl_l_opcode
= 0x2a;
761 static const int ldq_l_opcode
= 0x2b;
762 static const int stl_c_opcode
= 0x2e;
763 static const int stq_c_opcode
= 0x2f;
765 /* Checks for an atomic sequence of instructions beginning with a LDL_L/LDQ_L
766 instruction and ending with a STL_C/STQ_C instruction. If such a sequence
767 is found, attempt to step through it. A breakpoint is placed at the end of
770 static std::vector
<CORE_ADDR
>
771 alpha_deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
773 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
775 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
776 unsigned int insn
= alpha_read_insn (gdbarch
, loc
);
779 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
780 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
781 int bc_insn_count
= 0; /* Conditional branch instruction count. */
783 /* Assume all atomic sequences start with a LDL_L/LDQ_L instruction. */
784 if (INSN_OPCODE (insn
) != ldl_l_opcode
785 && INSN_OPCODE (insn
) != ldq_l_opcode
)
788 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
790 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
792 loc
+= ALPHA_INSN_SIZE
;
793 insn
= alpha_read_insn (gdbarch
, loc
);
795 /* Assume that there is at most one branch in the atomic
796 sequence. If a branch is found, put a breakpoint in
797 its destination address. */
798 if (INSN_OPCODE (insn
) >= br_opcode
)
800 int immediate
= (insn
& 0x001fffff) << 2;
802 immediate
= (immediate
^ 0x400000) - 0x400000;
804 if (bc_insn_count
>= 1)
805 return {}; /* More than one branch found, fallback
806 to the standard single-step code. */
808 breaks
[1] = loc
+ ALPHA_INSN_SIZE
+ immediate
;
814 if (INSN_OPCODE (insn
) == stl_c_opcode
815 || INSN_OPCODE (insn
) == stq_c_opcode
)
819 /* Assume that the atomic sequence ends with a STL_C/STQ_C instruction. */
820 if (INSN_OPCODE (insn
) != stl_c_opcode
821 && INSN_OPCODE (insn
) != stq_c_opcode
)
825 loc
+= ALPHA_INSN_SIZE
;
827 /* Insert a breakpoint right after the end of the atomic sequence. */
830 /* Check for duplicated breakpoints. Check also for a breakpoint
831 placed (branch instruction's destination) anywhere in sequence. */
833 && (breaks
[1] == breaks
[0]
834 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
837 std::vector
<CORE_ADDR
> next_pcs
;
839 for (index
= 0; index
<= last_breakpoint
; index
++)
840 next_pcs
.push_back (breaks
[index
]);
846 /* Figure out where the longjmp will land.
847 We expect the first arg to be a pointer to the jmp_buf structure from
848 which we extract the PC (JB_PC) that we will land at. The PC is copied
849 into the "pc". This routine returns true on success. */
852 alpha_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
854 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
855 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
856 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
858 gdb_byte raw_buffer
[ALPHA_REGISTER_SIZE
];
860 jb_addr
= get_frame_register_unsigned (frame
, ALPHA_A0_REGNUM
);
862 if (target_read_memory (jb_addr
+ (tdep
->jb_pc
* tdep
->jb_elt_size
),
863 raw_buffer
, tdep
->jb_elt_size
))
866 *pc
= extract_unsigned_integer (raw_buffer
, tdep
->jb_elt_size
, byte_order
);
871 /* Frame unwinder for signal trampolines. We use alpha tdep bits that
872 describe the location and shape of the sigcontext structure. After
873 that, all registers are in memory, so it's easy. */
874 /* ??? Shouldn't we be able to do this generically, rather than with
875 OSABI data specific to Alpha? */
877 struct alpha_sigtramp_unwind_cache
879 CORE_ADDR sigcontext_addr
;
882 static struct alpha_sigtramp_unwind_cache
*
883 alpha_sigtramp_frame_unwind_cache (struct frame_info
*this_frame
,
884 void **this_prologue_cache
)
886 struct alpha_sigtramp_unwind_cache
*info
;
887 struct gdbarch_tdep
*tdep
;
889 if (*this_prologue_cache
)
890 return (struct alpha_sigtramp_unwind_cache
*) *this_prologue_cache
;
892 info
= FRAME_OBSTACK_ZALLOC (struct alpha_sigtramp_unwind_cache
);
893 *this_prologue_cache
= info
;
895 tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
896 info
->sigcontext_addr
= tdep
->sigcontext_addr (this_frame
);
901 /* Return the address of REGNUM in a sigtramp frame. Since this is
902 all arithmetic, it doesn't seem worthwhile to cache it. */
905 alpha_sigtramp_register_address (struct gdbarch
*gdbarch
,
906 CORE_ADDR sigcontext_addr
, int regnum
)
908 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
910 if (regnum
>= 0 && regnum
< 32)
911 return sigcontext_addr
+ tdep
->sc_regs_offset
+ regnum
* 8;
912 else if (regnum
>= ALPHA_FP0_REGNUM
&& regnum
< ALPHA_FP0_REGNUM
+ 32)
913 return sigcontext_addr
+ tdep
->sc_fpregs_offset
+ regnum
* 8;
914 else if (regnum
== ALPHA_PC_REGNUM
)
915 return sigcontext_addr
+ tdep
->sc_pc_offset
;
920 /* Given a GDB frame, determine the address of the calling function's
921 frame. This will be used to create a new GDB frame struct. */
924 alpha_sigtramp_frame_this_id (struct frame_info
*this_frame
,
925 void **this_prologue_cache
,
926 struct frame_id
*this_id
)
928 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
929 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
930 struct alpha_sigtramp_unwind_cache
*info
931 = alpha_sigtramp_frame_unwind_cache (this_frame
, this_prologue_cache
);
932 CORE_ADDR stack_addr
, code_addr
;
934 /* If the OSABI couldn't locate the sigcontext, give up. */
935 if (info
->sigcontext_addr
== 0)
938 /* If we have dynamic signal trampolines, find their start.
939 If we do not, then we must assume there is a symbol record
940 that can provide the start address. */
941 if (tdep
->dynamic_sigtramp_offset
)
944 code_addr
= get_frame_pc (this_frame
);
945 offset
= tdep
->dynamic_sigtramp_offset (gdbarch
, code_addr
);
952 code_addr
= get_frame_func (this_frame
);
954 /* The stack address is trivially read from the sigcontext. */
955 stack_addr
= alpha_sigtramp_register_address (gdbarch
, info
->sigcontext_addr
,
957 stack_addr
= get_frame_memory_unsigned (this_frame
, stack_addr
,
958 ALPHA_REGISTER_SIZE
);
960 *this_id
= frame_id_build (stack_addr
, code_addr
);
963 /* Retrieve the value of REGNUM in FRAME. Don't give up! */
965 static struct value
*
966 alpha_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
967 void **this_prologue_cache
, int regnum
)
969 struct alpha_sigtramp_unwind_cache
*info
970 = alpha_sigtramp_frame_unwind_cache (this_frame
, this_prologue_cache
);
973 if (info
->sigcontext_addr
!= 0)
975 /* All integer and fp registers are stored in memory. */
976 addr
= alpha_sigtramp_register_address (get_frame_arch (this_frame
),
977 info
->sigcontext_addr
, regnum
);
979 return frame_unwind_got_memory (this_frame
, regnum
, addr
);
982 /* This extra register may actually be in the sigcontext, but our
983 current description of it in alpha_sigtramp_frame_unwind_cache
984 doesn't include it. Too bad. Fall back on whatever's in the
986 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
990 alpha_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
991 struct frame_info
*this_frame
,
992 void **this_prologue_cache
)
994 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
995 CORE_ADDR pc
= get_frame_pc (this_frame
);
998 /* NOTE: cagney/2004-04-30: Do not copy/clone this code. Instead
999 look at tramp-frame.h and other simplier per-architecture
1000 sigtramp unwinders. */
1002 /* We shouldn't even bother to try if the OSABI didn't register a
1003 sigcontext_addr handler or pc_in_sigtramp hander. */
1004 if (gdbarch_tdep (gdbarch
)->sigcontext_addr
== NULL
)
1006 if (gdbarch_tdep (gdbarch
)->pc_in_sigtramp
== NULL
)
1009 /* Otherwise we should be in a signal frame. */
1010 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
1011 if (gdbarch_tdep (gdbarch
)->pc_in_sigtramp (gdbarch
, pc
, name
))
1017 static const struct frame_unwind alpha_sigtramp_frame_unwind
= {
1019 default_frame_unwind_stop_reason
,
1020 alpha_sigtramp_frame_this_id
,
1021 alpha_sigtramp_frame_prev_register
,
1023 alpha_sigtramp_frame_sniffer
1028 /* Heuristic_proc_start may hunt through the text section for a long
1029 time across a 2400 baud serial line. Allows the user to limit this
1031 static int heuristic_fence_post
= 0;
1033 /* Attempt to locate the start of the function containing PC. We assume that
1034 the previous function ends with an about_to_return insn. Not foolproof by
1035 any means, since gcc is happy to put the epilogue in the middle of a
1036 function. But we're guessing anyway... */
1039 alpha_heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1041 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1042 CORE_ADDR last_non_nop
= pc
;
1043 CORE_ADDR fence
= pc
- heuristic_fence_post
;
1044 CORE_ADDR orig_pc
= pc
;
1046 struct inferior
*inf
;
1051 /* First see if we can find the start of the function from minimal
1052 symbol information. This can succeed with a binary that doesn't
1053 have debug info, but hasn't been stripped. */
1054 func
= get_pc_function_start (pc
);
1058 if (heuristic_fence_post
== -1
1059 || fence
< tdep
->vm_min_address
)
1060 fence
= tdep
->vm_min_address
;
1062 /* Search back for previous return; also stop at a 0, which might be
1063 seen for instance before the start of a code section. Don't include
1064 nops, since this usually indicates padding between functions. */
1065 for (pc
-= ALPHA_INSN_SIZE
; pc
>= fence
; pc
-= ALPHA_INSN_SIZE
)
1067 unsigned int insn
= alpha_read_insn (gdbarch
, pc
);
1070 case 0: /* invalid insn */
1071 case 0x6bfa8001: /* ret $31,($26),1 */
1072 return last_non_nop
;
1074 case 0x2ffe0000: /* unop: ldq_u $31,0($30) */
1075 case 0x47ff041f: /* nop: bis $31,$31,$31 */
1084 inf
= current_inferior ();
1086 /* It's not clear to me why we reach this point when stopping quietly,
1087 but with this test, at least we don't print out warnings for every
1088 child forked (eg, on decstation). 22apr93 rich@cygnus.com. */
1089 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
1091 static int blurb_printed
= 0;
1093 if (fence
== tdep
->vm_min_address
)
1094 warning (_("Hit beginning of text section without finding \
1095 enclosing function for address %s"), paddress (gdbarch
, orig_pc
));
1097 warning (_("Hit heuristic-fence-post without finding \
1098 enclosing function for address %s"), paddress (gdbarch
, orig_pc
));
1102 printf_filtered (_("\
1103 This warning occurs if you are debugging a function without any symbols\n\
1104 (for example, in a stripped executable). In that case, you may wish to\n\
1105 increase the size of the search with the `set heuristic-fence-post' command.\n\
1107 Otherwise, you told GDB there was a function where there isn't one, or\n\
1108 (more likely) you have encountered a bug in GDB.\n"));
1116 /* Fallback alpha frame unwinder. Uses instruction scanning and knows
1117 something about the traditional layout of alpha stack frames. */
1119 struct alpha_heuristic_unwind_cache
1123 struct trad_frame_saved_reg
*saved_regs
;
1127 /* If a probing loop sequence starts at PC, simulate it and compute
1128 FRAME_SIZE and PC after its execution. Otherwise, return with PC and
1129 FRAME_SIZE unchanged. */
1132 alpha_heuristic_analyze_probing_loop (struct gdbarch
*gdbarch
, CORE_ADDR
*pc
,
1135 CORE_ADDR cur_pc
= *pc
;
1136 int cur_frame_size
= *frame_size
;
1137 int nb_of_iterations
, reg_index
, reg_probe
;
1140 /* The following pattern is recognized as a probing loop:
1142 lda REG_INDEX,NB_OF_ITERATIONS
1143 lda REG_PROBE,<immediate>(sp)
1146 stq zero,<immediate>(REG_PROBE)
1147 subq REG_INDEX,0x1,REG_INDEX
1148 lda REG_PROBE,<immediate>(REG_PROBE)
1149 bne REG_INDEX, LOOP_START
1151 lda sp,<immediate>(REG_PROBE)
1153 If anything different is found, the function returns without
1154 changing PC and FRAME_SIZE. Otherwise, PC will point immediately
1155 after this sequence, and FRAME_SIZE will be updated. */
1157 /* lda REG_INDEX,NB_OF_ITERATIONS */
1159 insn
= alpha_read_insn (gdbarch
, cur_pc
);
1160 if (INSN_OPCODE (insn
) != lda_opcode
)
1162 reg_index
= MEM_RA (insn
);
1163 nb_of_iterations
= MEM_DISP (insn
);
1165 /* lda REG_PROBE,<immediate>(sp) */
1167 cur_pc
+= ALPHA_INSN_SIZE
;
1168 insn
= alpha_read_insn (gdbarch
, cur_pc
);
1169 if (INSN_OPCODE (insn
) != lda_opcode
1170 || MEM_RB (insn
) != ALPHA_SP_REGNUM
)
1172 reg_probe
= MEM_RA (insn
);
1173 cur_frame_size
-= MEM_DISP (insn
);
1175 /* stq zero,<immediate>(REG_PROBE) */
1177 cur_pc
+= ALPHA_INSN_SIZE
;
1178 insn
= alpha_read_insn (gdbarch
, cur_pc
);
1179 if (INSN_OPCODE (insn
) != stq_opcode
1180 || MEM_RA (insn
) != 0x1f
1181 || MEM_RB (insn
) != reg_probe
)
1184 /* subq REG_INDEX,0x1,REG_INDEX */
1186 cur_pc
+= ALPHA_INSN_SIZE
;
1187 insn
= alpha_read_insn (gdbarch
, cur_pc
);
1188 if (INSN_OPCODE (insn
) != subq_opcode
1189 || !OPR_HAS_IMMEDIATE (insn
)
1190 || OPR_FUNCTION (insn
) != subq_function
1191 || OPR_LIT(insn
) != 1
1192 || OPR_RA (insn
) != reg_index
1193 || OPR_RC (insn
) != reg_index
)
1196 /* lda REG_PROBE,<immediate>(REG_PROBE) */
1198 cur_pc
+= ALPHA_INSN_SIZE
;
1199 insn
= alpha_read_insn (gdbarch
, cur_pc
);
1200 if (INSN_OPCODE (insn
) != lda_opcode
1201 || MEM_RA (insn
) != reg_probe
1202 || MEM_RB (insn
) != reg_probe
)
1204 cur_frame_size
-= MEM_DISP (insn
) * nb_of_iterations
;
1206 /* bne REG_INDEX, LOOP_START */
1208 cur_pc
+= ALPHA_INSN_SIZE
;
1209 insn
= alpha_read_insn (gdbarch
, cur_pc
);
1210 if (INSN_OPCODE (insn
) != bne_opcode
1211 || MEM_RA (insn
) != reg_index
)
1214 /* lda sp,<immediate>(REG_PROBE) */
1216 cur_pc
+= ALPHA_INSN_SIZE
;
1217 insn
= alpha_read_insn (gdbarch
, cur_pc
);
1218 if (INSN_OPCODE (insn
) != lda_opcode
1219 || MEM_RA (insn
) != ALPHA_SP_REGNUM
1220 || MEM_RB (insn
) != reg_probe
)
1222 cur_frame_size
-= MEM_DISP (insn
);
1225 *frame_size
= cur_frame_size
;
1228 static struct alpha_heuristic_unwind_cache
*
1229 alpha_heuristic_frame_unwind_cache (struct frame_info
*this_frame
,
1230 void **this_prologue_cache
,
1233 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1234 struct alpha_heuristic_unwind_cache
*info
;
1236 CORE_ADDR limit_pc
, cur_pc
;
1237 int frame_reg
, frame_size
, return_reg
, reg
;
1239 if (*this_prologue_cache
)
1240 return (struct alpha_heuristic_unwind_cache
*) *this_prologue_cache
;
1242 info
= FRAME_OBSTACK_ZALLOC (struct alpha_heuristic_unwind_cache
);
1243 *this_prologue_cache
= info
;
1244 info
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1246 limit_pc
= get_frame_pc (this_frame
);
1248 start_pc
= alpha_heuristic_proc_start (gdbarch
, limit_pc
);
1249 info
->start_pc
= start_pc
;
1251 frame_reg
= ALPHA_SP_REGNUM
;
1255 /* If we've identified a likely place to start, do code scanning. */
1258 /* Limit the forward search to 50 instructions. */
1259 if (start_pc
+ 200 < limit_pc
)
1260 limit_pc
= start_pc
+ 200;
1262 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= ALPHA_INSN_SIZE
)
1264 unsigned int word
= alpha_read_insn (gdbarch
, cur_pc
);
1266 if ((word
& 0xffff0000) == 0x23de0000) /* lda $sp,n($sp) */
1270 /* Consider only the first stack allocation instruction
1271 to contain the static size of the frame. */
1272 if (frame_size
== 0)
1273 frame_size
= (-word
) & 0xffff;
1277 /* Exit loop if a positive stack adjustment is found, which
1278 usually means that the stack cleanup code in the function
1279 epilogue is reached. */
1283 else if ((word
& 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */
1285 reg
= (word
& 0x03e00000) >> 21;
1287 /* Ignore this instruction if we have already encountered
1288 an instruction saving the same register earlier in the
1289 function code. The current instruction does not tell
1290 us where the original value upon function entry is saved.
1291 All it says is that the function we are scanning reused
1292 that register for some computation of its own, and is now
1293 saving its result. */
1294 if (trad_frame_addr_p(info
->saved_regs
, reg
))
1300 /* Do not compute the address where the register was saved yet,
1301 because we don't know yet if the offset will need to be
1302 relative to $sp or $fp (we can not compute the address
1303 relative to $sp if $sp is updated during the execution of
1304 the current subroutine, for instance when doing some alloca).
1305 So just store the offset for the moment, and compute the
1306 address later when we know whether this frame has a frame
1308 /* Hack: temporarily add one, so that the offset is non-zero
1309 and we can tell which registers have save offsets below. */
1310 info
->saved_regs
[reg
].addr
= (word
& 0xffff) + 1;
1312 /* Starting with OSF/1-3.2C, the system libraries are shipped
1313 without local symbols, but they still contain procedure
1314 descriptors without a symbol reference. GDB is currently
1315 unable to find these procedure descriptors and uses
1316 heuristic_proc_desc instead.
1317 As some low level compiler support routines (__div*, __add*)
1318 use a non-standard return address register, we have to
1319 add some heuristics to determine the return address register,
1320 or stepping over these routines will fail.
1321 Usually the return address register is the first register
1322 saved on the stack, but assembler optimization might
1323 rearrange the register saves.
1324 So we recognize only a few registers (t7, t9, ra) within
1325 the procedure prologue as valid return address registers.
1326 If we encounter a return instruction, we extract the
1327 return address register from it.
1329 FIXME: Rewriting GDB to access the procedure descriptors,
1330 e.g. via the minimal symbol table, might obviate this
1332 if (return_reg
== -1
1333 && cur_pc
< (start_pc
+ 80)
1334 && (reg
== ALPHA_T7_REGNUM
1335 || reg
== ALPHA_T9_REGNUM
1336 || reg
== ALPHA_RA_REGNUM
))
1339 else if ((word
& 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */
1340 return_reg
= (word
>> 16) & 0x1f;
1341 else if (word
== 0x47de040f) /* bis sp,sp,fp */
1342 frame_reg
= ALPHA_GCC_FP_REGNUM
;
1343 else if (word
== 0x47fe040f) /* bis zero,sp,fp */
1344 frame_reg
= ALPHA_GCC_FP_REGNUM
;
1346 alpha_heuristic_analyze_probing_loop (gdbarch
, &cur_pc
, &frame_size
);
1349 /* If we haven't found a valid return address register yet, keep
1350 searching in the procedure prologue. */
1351 if (return_reg
== -1)
1353 while (cur_pc
< (limit_pc
+ 80) && cur_pc
< (start_pc
+ 80))
1355 unsigned int word
= alpha_read_insn (gdbarch
, cur_pc
);
1357 if ((word
& 0xfc1f0000) == 0xb41e0000) /* stq reg,n($sp) */
1359 reg
= (word
& 0x03e00000) >> 21;
1360 if (reg
== ALPHA_T7_REGNUM
1361 || reg
== ALPHA_T9_REGNUM
1362 || reg
== ALPHA_RA_REGNUM
)
1368 else if ((word
& 0xffe0ffff) == 0x6be08001) /* ret zero,reg,1 */
1370 return_reg
= (word
>> 16) & 0x1f;
1374 cur_pc
+= ALPHA_INSN_SIZE
;
1379 /* Failing that, do default to the customary RA. */
1380 if (return_reg
== -1)
1381 return_reg
= ALPHA_RA_REGNUM
;
1382 info
->return_reg
= return_reg
;
1384 val
= get_frame_register_unsigned (this_frame
, frame_reg
);
1385 info
->vfp
= val
+ frame_size
;
1387 /* Convert offsets to absolute addresses. See above about adding
1388 one to the offsets to make all detected offsets non-zero. */
1389 for (reg
= 0; reg
< ALPHA_NUM_REGS
; ++reg
)
1390 if (trad_frame_addr_p(info
->saved_regs
, reg
))
1391 info
->saved_regs
[reg
].addr
+= val
- 1;
1393 /* The stack pointer of the previous frame is computed by popping
1394 the current stack frame. */
1395 if (!trad_frame_addr_p (info
->saved_regs
, ALPHA_SP_REGNUM
))
1396 trad_frame_set_value (info
->saved_regs
, ALPHA_SP_REGNUM
, info
->vfp
);
1401 /* Given a GDB frame, determine the address of the calling function's
1402 frame. This will be used to create a new GDB frame struct. */
1405 alpha_heuristic_frame_this_id (struct frame_info
*this_frame
,
1406 void **this_prologue_cache
,
1407 struct frame_id
*this_id
)
1409 struct alpha_heuristic_unwind_cache
*info
1410 = alpha_heuristic_frame_unwind_cache (this_frame
, this_prologue_cache
, 0);
1412 *this_id
= frame_id_build (info
->vfp
, info
->start_pc
);
1415 /* Retrieve the value of REGNUM in FRAME. Don't give up! */
1417 static struct value
*
1418 alpha_heuristic_frame_prev_register (struct frame_info
*this_frame
,
1419 void **this_prologue_cache
, int regnum
)
1421 struct alpha_heuristic_unwind_cache
*info
1422 = alpha_heuristic_frame_unwind_cache (this_frame
, this_prologue_cache
, 0);
1424 /* The PC of the previous frame is stored in the link register of
1425 the current frame. Frob regnum so that we pull the value from
1426 the correct place. */
1427 if (regnum
== ALPHA_PC_REGNUM
)
1428 regnum
= info
->return_reg
;
1430 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
1433 static const struct frame_unwind alpha_heuristic_frame_unwind
= {
1435 default_frame_unwind_stop_reason
,
1436 alpha_heuristic_frame_this_id
,
1437 alpha_heuristic_frame_prev_register
,
1439 default_frame_sniffer
1443 alpha_heuristic_frame_base_address (struct frame_info
*this_frame
,
1444 void **this_prologue_cache
)
1446 struct alpha_heuristic_unwind_cache
*info
1447 = alpha_heuristic_frame_unwind_cache (this_frame
, this_prologue_cache
, 0);
1452 static const struct frame_base alpha_heuristic_frame_base
= {
1453 &alpha_heuristic_frame_unwind
,
1454 alpha_heuristic_frame_base_address
,
1455 alpha_heuristic_frame_base_address
,
1456 alpha_heuristic_frame_base_address
1459 /* Just like reinit_frame_cache, but with the right arguments to be
1460 callable as an sfunc. Used by the "set heuristic-fence-post" command. */
1463 reinit_frame_cache_sfunc (const char *args
,
1464 int from_tty
, struct cmd_list_element
*c
)
1466 reinit_frame_cache ();
1469 /* Helper routines for alpha*-nat.c files to move register sets to and
1470 from core files. The UNIQUE pointer is allowed to be NULL, as most
1471 targets don't supply this value in their core files. */
1474 alpha_supply_int_regs (struct regcache
*regcache
, int regno
,
1475 const void *r0_r30
, const void *pc
, const void *unique
)
1477 const gdb_byte
*regs
= (const gdb_byte
*) r0_r30
;
1480 for (i
= 0; i
< 31; ++i
)
1481 if (regno
== i
|| regno
== -1)
1482 regcache
->raw_supply (i
, regs
+ i
* 8);
1484 if (regno
== ALPHA_ZERO_REGNUM
|| regno
== -1)
1486 const gdb_byte zero
[8] = { 0 };
1488 regcache
->raw_supply (ALPHA_ZERO_REGNUM
, zero
);
1491 if (regno
== ALPHA_PC_REGNUM
|| regno
== -1)
1492 regcache
->raw_supply (ALPHA_PC_REGNUM
, pc
);
1494 if (regno
== ALPHA_UNIQUE_REGNUM
|| regno
== -1)
1495 regcache
->raw_supply (ALPHA_UNIQUE_REGNUM
, unique
);
1499 alpha_fill_int_regs (const struct regcache
*regcache
,
1500 int regno
, void *r0_r30
, void *pc
, void *unique
)
1502 gdb_byte
*regs
= (gdb_byte
*) r0_r30
;
1505 for (i
= 0; i
< 31; ++i
)
1506 if (regno
== i
|| regno
== -1)
1507 regcache
->raw_collect (i
, regs
+ i
* 8);
1509 if (regno
== ALPHA_PC_REGNUM
|| regno
== -1)
1510 regcache
->raw_collect (ALPHA_PC_REGNUM
, pc
);
1512 if (unique
&& (regno
== ALPHA_UNIQUE_REGNUM
|| regno
== -1))
1513 regcache
->raw_collect (ALPHA_UNIQUE_REGNUM
, unique
);
1517 alpha_supply_fp_regs (struct regcache
*regcache
, int regno
,
1518 const void *f0_f30
, const void *fpcr
)
1520 const gdb_byte
*regs
= (const gdb_byte
*) f0_f30
;
1523 for (i
= ALPHA_FP0_REGNUM
; i
< ALPHA_FP0_REGNUM
+ 31; ++i
)
1524 if (regno
== i
|| regno
== -1)
1525 regcache
->raw_supply (i
, regs
+ (i
- ALPHA_FP0_REGNUM
) * 8);
1527 if (regno
== ALPHA_FPCR_REGNUM
|| regno
== -1)
1528 regcache
->raw_supply (ALPHA_FPCR_REGNUM
, fpcr
);
1532 alpha_fill_fp_regs (const struct regcache
*regcache
,
1533 int regno
, void *f0_f30
, void *fpcr
)
1535 gdb_byte
*regs
= (gdb_byte
*) f0_f30
;
1538 for (i
= ALPHA_FP0_REGNUM
; i
< ALPHA_FP0_REGNUM
+ 31; ++i
)
1539 if (regno
== i
|| regno
== -1)
1540 regcache
->raw_collect (i
, regs
+ (i
- ALPHA_FP0_REGNUM
) * 8);
1542 if (regno
== ALPHA_FPCR_REGNUM
|| regno
== -1)
1543 regcache
->raw_collect (ALPHA_FPCR_REGNUM
, fpcr
);
1548 /* Return nonzero if the G_floating register value in REG is equal to
1549 zero for FP control instructions. */
1552 fp_register_zero_p (LONGEST reg
)
1554 /* Check that all bits except the sign bit are zero. */
1555 const LONGEST zero_mask
= ((LONGEST
) 1 << 63) ^ -1;
1557 return ((reg
& zero_mask
) == 0);
1560 /* Return the value of the sign bit for the G_floating register
1561 value held in REG. */
1564 fp_register_sign_bit (LONGEST reg
)
1566 const LONGEST sign_mask
= (LONGEST
) 1 << 63;
1568 return ((reg
& sign_mask
) != 0);
1571 /* alpha_software_single_step() is called just before we want to resume
1572 the inferior, if we want to single-step it but there is no hardware
1573 or kernel single-step support (NetBSD on Alpha, for example). We find
1574 the target of the coming instruction and breakpoint it. */
1577 alpha_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1579 struct gdbarch
*gdbarch
= regcache
->arch ();
1586 insn
= alpha_read_insn (gdbarch
, pc
);
1588 /* Opcode is top 6 bits. */
1589 op
= (insn
>> 26) & 0x3f;
1593 /* Jump format: target PC is:
1595 return (regcache_raw_get_unsigned (regcache
, (insn
>> 16) & 0x1f) & ~3);
1598 if ((op
& 0x30) == 0x30)
1600 /* Branch format: target PC is:
1601 (new PC) + (4 * sext(displacement)) */
1602 if (op
== 0x30 /* BR */
1603 || op
== 0x34) /* BSR */
1606 offset
= (insn
& 0x001fffff);
1607 if (offset
& 0x00100000)
1608 offset
|= 0xffe00000;
1609 offset
*= ALPHA_INSN_SIZE
;
1610 return (pc
+ ALPHA_INSN_SIZE
+ offset
);
1613 /* Need to determine if branch is taken; read RA. */
1614 regno
= (insn
>> 21) & 0x1f;
1617 case 0x31: /* FBEQ */
1618 case 0x36: /* FBGE */
1619 case 0x37: /* FBGT */
1620 case 0x33: /* FBLE */
1621 case 0x32: /* FBLT */
1622 case 0x35: /* FBNE */
1623 regno
+= gdbarch_fp0_regnum (gdbarch
);
1626 rav
= regcache_raw_get_signed (regcache
, regno
);
1630 case 0x38: /* BLBC */
1634 case 0x3c: /* BLBS */
1638 case 0x39: /* BEQ */
1642 case 0x3d: /* BNE */
1646 case 0x3a: /* BLT */
1650 case 0x3b: /* BLE */
1654 case 0x3f: /* BGT */
1658 case 0x3e: /* BGE */
1663 /* Floating point branches. */
1665 case 0x31: /* FBEQ */
1666 if (fp_register_zero_p (rav
))
1669 case 0x36: /* FBGE */
1670 if (fp_register_sign_bit (rav
) == 0 || fp_register_zero_p (rav
))
1673 case 0x37: /* FBGT */
1674 if (fp_register_sign_bit (rav
) == 0 && ! fp_register_zero_p (rav
))
1677 case 0x33: /* FBLE */
1678 if (fp_register_sign_bit (rav
) == 1 || fp_register_zero_p (rav
))
1681 case 0x32: /* FBLT */
1682 if (fp_register_sign_bit (rav
) == 1 && ! fp_register_zero_p (rav
))
1685 case 0x35: /* FBNE */
1686 if (! fp_register_zero_p (rav
))
1692 /* Not a branch or branch not taken; target PC is:
1694 return (pc
+ ALPHA_INSN_SIZE
);
1697 std::vector
<CORE_ADDR
>
1698 alpha_software_single_step (struct regcache
*regcache
)
1700 struct gdbarch
*gdbarch
= regcache
->arch ();
1702 CORE_ADDR pc
= regcache_read_pc (regcache
);
1704 std::vector
<CORE_ADDR
> next_pcs
1705 = alpha_deal_with_atomic_sequence (gdbarch
, pc
);
1706 if (!next_pcs
.empty ())
1709 CORE_ADDR next_pc
= alpha_next_pc (regcache
, pc
);
1714 /* Initialize the current architecture based on INFO. If possible, re-use an
1715 architecture from ARCHES, which is a list of architectures already created
1716 during this debugging session.
1718 Called e.g. at program startup, when reading a core file, and when reading
1721 static struct gdbarch
*
1722 alpha_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1724 struct gdbarch_tdep
*tdep
;
1725 struct gdbarch
*gdbarch
;
1727 /* Find a candidate among extant architectures. */
1728 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1730 return arches
->gdbarch
;
1732 tdep
= XCNEW (struct gdbarch_tdep
);
1733 gdbarch
= gdbarch_alloc (&info
, tdep
);
1735 /* Lowest text address. This is used by heuristic_proc_start()
1736 to decide when to stop looking. */
1737 tdep
->vm_min_address
= (CORE_ADDR
) 0x120000000LL
;
1739 tdep
->dynamic_sigtramp_offset
= NULL
;
1740 tdep
->sigcontext_addr
= NULL
;
1741 tdep
->sc_pc_offset
= 2 * 8;
1742 tdep
->sc_regs_offset
= 4 * 8;
1743 tdep
->sc_fpregs_offset
= tdep
->sc_regs_offset
+ 32 * 8 + 8;
1745 tdep
->jb_pc
= -1; /* longjmp support not enabled by default. */
1747 tdep
->return_in_memory
= alpha_return_in_memory_always
;
1750 set_gdbarch_short_bit (gdbarch
, 16);
1751 set_gdbarch_int_bit (gdbarch
, 32);
1752 set_gdbarch_long_bit (gdbarch
, 64);
1753 set_gdbarch_long_long_bit (gdbarch
, 64);
1754 set_gdbarch_wchar_bit (gdbarch
, 64);
1755 set_gdbarch_wchar_signed (gdbarch
, 0);
1756 set_gdbarch_float_bit (gdbarch
, 32);
1757 set_gdbarch_double_bit (gdbarch
, 64);
1758 set_gdbarch_long_double_bit (gdbarch
, 64);
1759 set_gdbarch_ptr_bit (gdbarch
, 64);
1762 set_gdbarch_num_regs (gdbarch
, ALPHA_NUM_REGS
);
1763 set_gdbarch_sp_regnum (gdbarch
, ALPHA_SP_REGNUM
);
1764 set_gdbarch_pc_regnum (gdbarch
, ALPHA_PC_REGNUM
);
1765 set_gdbarch_fp0_regnum (gdbarch
, ALPHA_FP0_REGNUM
);
1767 set_gdbarch_register_name (gdbarch
, alpha_register_name
);
1768 set_gdbarch_register_type (gdbarch
, alpha_register_type
);
1770 set_gdbarch_cannot_fetch_register (gdbarch
, alpha_cannot_fetch_register
);
1771 set_gdbarch_cannot_store_register (gdbarch
, alpha_cannot_store_register
);
1773 set_gdbarch_convert_register_p (gdbarch
, alpha_convert_register_p
);
1774 set_gdbarch_register_to_value (gdbarch
, alpha_register_to_value
);
1775 set_gdbarch_value_to_register (gdbarch
, alpha_value_to_register
);
1777 set_gdbarch_register_reggroup_p (gdbarch
, alpha_register_reggroup_p
);
1779 /* Prologue heuristics. */
1780 set_gdbarch_skip_prologue (gdbarch
, alpha_skip_prologue
);
1784 set_gdbarch_return_value (gdbarch
, alpha_return_value
);
1786 /* Settings for calling functions in the inferior. */
1787 set_gdbarch_push_dummy_call (gdbarch
, alpha_push_dummy_call
);
1789 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1790 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
1792 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
1793 alpha_breakpoint::kind_from_pc
);
1794 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
1795 alpha_breakpoint::bp_from_kind
);
1796 set_gdbarch_decr_pc_after_break (gdbarch
, ALPHA_INSN_SIZE
);
1797 set_gdbarch_cannot_step_breakpoint (gdbarch
, 1);
1799 /* Handles single stepping of atomic sequences. */
1800 set_gdbarch_software_single_step (gdbarch
, alpha_software_single_step
);
1802 /* Hook in ABI-specific overrides, if they have been registered. */
1803 gdbarch_init_osabi (info
, gdbarch
);
1805 /* Now that we have tuned the configuration, set a few final things
1806 based on what the OS ABI has told us. */
1808 if (tdep
->jb_pc
>= 0)
1809 set_gdbarch_get_longjmp_target (gdbarch
, alpha_get_longjmp_target
);
1811 frame_unwind_append_unwinder (gdbarch
, &alpha_sigtramp_frame_unwind
);
1812 frame_unwind_append_unwinder (gdbarch
, &alpha_heuristic_frame_unwind
);
1814 frame_base_set_default (gdbarch
, &alpha_heuristic_frame_base
);
1820 alpha_dwarf2_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
1822 dwarf2_append_unwinders (gdbarch
);
1823 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
1827 _initialize_alpha_tdep (void)
1830 gdbarch_register (bfd_arch_alpha
, alpha_gdbarch_init
, NULL
);
1832 /* Let the user set the fence post for heuristic_proc_start. */
1834 /* We really would like to have both "0" and "unlimited" work, but
1835 command.c doesn't deal with that. So make it a var_zinteger
1836 because the user can always use "999999" or some such for unlimited. */
1837 /* We need to throw away the frame cache when we set this, since it
1838 might change our ability to get backtraces. */
1839 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
1840 &heuristic_fence_post
, _("\
1841 Set the distance searched for the start of a function."), _("\
1842 Show the distance searched for the start of a function."), _("\
1843 If you are debugging a stripped executable, GDB needs to search through the\n\
1844 program for the start of a function. This command sets the distance of the\n\
1845 search. The only need to set it is when debugging a stripped executable."),
1846 reinit_frame_cache_sfunc
,
1847 NULL
, /* FIXME: i18n: The distance searched for
1848 the start of a function is \"%d\". */
1849 &setlist
, &showlist
);