gdb/am29k-opcode.h

   1 /* Table of opcodes for the AMD 29000
   2    Copyright (C) 1990, 1991 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.  Written by Jim Kingdon.
   4
   5 This file is part of GDB.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program; if not, write to the Free Software
  19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  */
  20
  21 struct am29k_opcode {
  22   /* Name of the instruction.  */
  23   char *name;
  24
  25   /* Opcode (i.e. most significant byte of the word).  */
  26   unsigned char opcode;
  27
  28   /* A string of characters which describe the operands.
  29      Valid characters are:
  30      ,        Itself.  The character appears in the assembly code.
  31      a        RA.  The register number is in bits 8-15 of the instruction.
  32      b        RB.  The register number is in bits 0-7 of the instruction.
  33      c        RC.  The register number is in bits 16-23 of the instruction.
  34      i        An immediate operand is in bits 0-7 of the instruction.
  35      x        Bits 0-7 and 16-23 of the instruction are bits 0-7 and 8-15
  36               (respectively) of the immediate operand.
  37      h        Same as x but the instruction contains bits 16-31 of the
  38               immediate operand.
  39      X        Same as x but bits 16-31 of the signed immediate operand
  40               are set to 1 (thus the operand is always negative).
  41      P,A      Bits 0-7 and 16-23 of the instruction are bits 2-9 and 10-17
  42               (respectively) of the immediate operand.
  43               P=PC-relative, sign-extended to 32 bits.
  44               A=Absolute, zero-extended to 32 bits.
  45      e        CE bit (bit 23) for a load/store instruction.
  46      n        Control field (bits 16-22) for a load/store instruction.
  47      v        Immediate operand in bits 16-23 of the instruction.
  48               (used for trap numbers).
  49      s        SA.  Special-purpose register number in bits 8-15
  50               of the instruction.
  51      u        UI--bit 7 of the instruction.
  52      r        RND--bits 4-6 of the instruction.
  53      d        FD--bits 2-3 of the instruction.
  54      f        FS--bits 0-1 of the instruction.  */
  55   char *args;
  56 };
  57
  58 static struct am29k_opcode am29k_opcodes[] =
  59 {
  60
  61 { "add", 0x14, "c,a,b" },
  62 { "add", 0x15, "c,a,i" },
  63 { "addc", 0x1c, "c,a,b" },
  64 { "addc", 0x1d, "c,a,i" },
  65 { "addcs", 0x18, "c,a,b" },
  66 { "addcs", 0x19, "c,a,i" },
  67 { "addcu", 0x1a, "c,a,b" },
  68 { "addcu", 0x1b, "c,a,i" },
  69 { "adds", 0x10, "c,a,b" },
  70 { "adds", 0x11, "c,a,i" },
  71 { "addu", 0x12, "c,a,b" },
  72 { "addu", 0x13, "c,a,i" },
  73 { "and", 0x90, "c,a,b" },
  74 { "and", 0x91, "c,a,i" },
  75 { "andn", 0x9c, "c,a,b" },
  76 { "andn", 0x9d, "c,a,i" },
  77 { "aseq", 0x70, "v,a,b" },
  78 { "aseq", 0x71, "v,a,i" },
  79 { "asge", 0x5c, "v,a,b" },
  80 { "asge", 0x5d, "v,a,i" },
  81 { "asgeu", 0x5e, "v,a,b" },
  82 { "asgeu", 0x5f, "v,a,i" },
  83 { "asgt", 0x58, "v,a,b" },
  84 { "asgt", 0x59, "v,a,i" },
  85 { "asgtu", 0x5a, "v,a,b" },
  86 { "asgtu", 0x5b, "v,a,i" },
  87 { "asle", 0x54, "v,a,b" },
  88 { "asle", 0x55, "v,a,i" },
  89 { "asleu", 0x56, "v,a,b" },
  90 { "asleu", 0x57, "v,a,i" },
  91 { "aslt", 0x50, "v,a,b" },
  92 { "aslt", 0x51, "v,a,i" },
  93 { "asltu", 0x52, "v,a,b" },
  94 { "asltu", 0x53, "v,a,i" },
  95 { "asneq", 0x72, "v,a,b" },
  96 { "asneq", 0x73, "v,a,i" },
  97 { "call", 0xa8, "a,P" },
  98 { "call", 0xa9, "a,A" },
  99 { "calli", 0xc8, "a,b" },
 100 { "class", 0xe6, "c,a,f" },
 101 { "clz", 0x08, "c,b" },
 102 { "clz", 0x09, "c,i" },
 103 { "const", 0x03, "a,x" },
 104 { "consth", 0x02, "a,h" },
 105 { "consthz", 0x05, "a,h" },
 106 { "constn", 0x01, "a,X" },
 107 { "convert", 0xe4, "c,a,u,r,d,f" },
 108 { "cpbyte", 0x2e, "c,a,b" },
 109 { "cpbyte", 0x2f, "c,a,i" },
 110 { "cpeq", 0x60, "c,a,b" },
 111 { "cpeq", 0x61, "c,a,i" },
 112 { "cpge", 0x4c, "c,a,b" },
 113 { "cpge", 0x4d, "c,a,i" },
 114 { "cpgeu", 0x4e, "c,a,b" },
 115 { "cpgeu", 0x4f, "c,a,i" },
 116 { "cpgt", 0x48, "c,a,b" },
 117 { "cpgt", 0x49, "c,a,i" },
 118 { "cpgtu", 0x4a, "c,a,b" },
 119 { "cpgtu", 0x4b, "c,a,i" },
 120 { "cple", 0x44, "c,a,b" },
 121 { "cple", 0x45, "c,a,i" },
 122 { "cpleu", 0x46, "c,a,b" },
 123 { "cpleu", 0x47, "c,a,i" },
 124 { "cplt", 0x40, "c,a,b" },
 125 { "cplt", 0x41, "c,a,i" },
 126 { "cpltu", 0x42, "c,a,b" },
 127 { "cpltu", 0x43, "c,a,i" },
 128 { "cpneq", 0x62, "c,a,b" },
 129 { "cpneq", 0x63, "c,a,i" },
 130 { "dadd", 0xf1, "c,a,b" },
 131 { "ddiv", 0xf7, "c,a,b" },
 132 { "deq", 0xeb, "c,a,b" },
 133 { "dge", 0xef, "c,a,b" },
 134 { "dgt", 0xed, "c,a,b" },
 135 { "div", 0x6a, "c,a,b" },
 136 { "div", 0x6b, "c,a,i" },
 137 { "div0", 0x68, "c,b" },
 138 { "div0", 0x69, "c,i" },
 139 { "divide", 0xe1, "c,a,b" },
 140 { "dividu", 0xe3, "c,a,b" },
 141 { "divl", 0x6c, "c,a,b" },
 142 { "divl", 0x6d, "c,a,i" },
 143 { "divrem", 0x6e, "c,a,b" },
 144 { "divrem", 0x6f, "c,a,i" },
 145 { "dmac", 0xd9, "F,C,a,b" },
 146 { "dmsm", 0xdb, "c,a,b" },
 147 { "dmul", 0xf5, "c,a,b" },
 148 { "dsub", 0xf3, "c,a,b" },
 149 { "emulate", 0xd7, "v,a,b" },
 150 { "exbyte", 0x0a, "c,a,b" },
 151 { "exbyte", 0x0b, "c,a,i" },
 152 { "exhw", 0x7c, "c,a,b" },
 153 { "exhw", 0x7d, "c,a,i" },
 154 { "exhws", 0x7e, "c,a" },
 155 { "extract", 0x7a, "c,a,b" },
 156 { "extract", 0x7b, "c,a,i" },
 157 { "fadd", 0xf0, "c,a,b" },
 158 { "fdiv", 0xf6, "c,a,b" },
 159 { "fdmul", 0xf9, "c,a,b" },
 160 { "feq", 0xea, "c,a,b" },
 161 { "fge", 0xee, "c,a,b" },
 162 { "fgt", 0xec, "c,a,b" },
 163 { "fmac", 0xd8, "F,C,a,b" },
 164 { "fmsm", 0xda, "c,a,b" },
 165 { "fmul", 0xf4, "c,a,b" },
 166 { "fsub", 0xf2, "c,a,b" },
 167 { "halt", 0x89, "" },
 168 { "inbyte", 0x0c, "c,a,b" },
 169 { "inbyte", 0x0d, "c,a,i" },
 170 { "inhw", 0x78, "c,a,b" },
 171 { "inhw", 0x79, "c,a,i" },
 172 { "inv", 0x9f, "" },
 173 { "iret", 0x88, "" },
 174 { "iretinv", 0x8c, "" },
 175 { "jmp", 0xa0, "P" },
 176 { "jmp", 0xa1, "A" },
 177 { "jmpf", 0xa4, "a,P" },
 178 { "jmpf", 0xa5, "a,A" },
 179 { "jmpfdec", 0xb4, "a,P" },
 180 { "jmpfdec", 0xb5, "a,A" },
 181 { "jmpfi", 0xc4, "a,b" },
 182 { "jmpi", 0xc0, "b" },
 183 { "jmpt", 0xac, "a,P" },
 184 { "jmpt", 0xad, "a,A" },
 185 { "jmpti", 0xcc, "a,b" },
 186 { "load", 0x16, "e,n,a,b" },
 187 { "load", 0x17, "e,n,a,i" },
 188 { "loadl", 0x06, "e,n,a,b" },
 189 { "loadl", 0x07, "e,n,a,i" },
 190 { "loadm", 0x36, "e,n,a,b" },
 191 { "loadm", 0x37, "e,n,a,i" },
 192 { "loadset", 0x26, "e,n,a,b" },
 193 { "loadset", 0x27, "e,n,a,i" },
 194 { "mfacc", 0xe9, "c,d,f" },
 195 { "mfsr", 0xc6, "c,s" },
 196 { "mftlb", 0xb6, "c,a" },
 197 { "mtacc", 0xe8, "a,d,f" },
 198 { "mtsr", 0xce, "s,b" },
 199 { "mtsrim", 0x04, "s,x" },
 200 { "mttlb", 0xbe, "a,b" },
 201 { "mul", 0x64, "c,a,b" },
 202 { "mul", 0x65, "c,a,i" },
 203 { "mull", 0x66, "c,a,b" },
 204 { "mull", 0x67, "c,a,i" },
 205 { "multiplu", 0xe2, "c,a,b" },
 206 { "multiply", 0xe0, "c,a,b" },
 207 { "multm", 0xde, "c,a,b" },
 208 { "multmu", 0xdf, "c,a,b" },
 209 { "mulu", 0x74, "c,a,b" },
 210 { "mulu", 0x75, "c,a,i" },
 211 { "nand", 0x9a, "c,a,b" },
 212 { "nand", 0x9b, "c,a,i" },
 213 { "nor", 0x98, "c,a,b" },
 214 { "nor", 0x99, "c,a,i" },
 215 { "or", 0x92, "c,a,b" },
 216 { "or", 0x93, "c,a,i" },
 217 { "orn", 0xaa, "c,a,b" },
 218 { "orn", 0xab, "c,a,i" },
 219
 220 /* The description of "setip" in Chapter 8 ("instruction set") of the user's
 221    manual claims that these are absolute register numbers.  But section
 222    7.2.1 explains that they are not.  The latter is correct, so print
 223    these normally ("lr0", "lr5", etc.).  */
 224 { "setip", 0x9e, "c,a,b" },
 225
 226 { "sll", 0x80, "c,a,b" },
 227 { "sll", 0x81, "c,a,i" },
 228 { "sqrt", 0xe5, "c,a,f" },
 229 { "sra", 0x86, "c,a,b" },
 230 { "sra", 0x87, "c,a,i" },
 231 { "srl", 0x82, "c,a,b" },
 232 { "srl", 0x83, "c,a,i" },
 233 { "store", 0x1e, "e,n,a,b" },
 234 { "store", 0x1f, "e,n,a,i" },
 235 { "storel", 0x0e, "e,n,a,b" },
 236 { "storel", 0x0f, "e,n,a,i" },
 237 { "storem", 0x3e, "e,n,a,b" },
 238 { "storem", 0x3f, "e,n,a,i" },
 239 { "sub", 0x24, "c,a,b" },
 240 { "sub", 0x25, "c,a,i" },
 241 { "subc", 0x2c, "c,a,b" },
 242 { "subc", 0x2d, "c,a,i" },
 243 { "subcs", 0x28, "c,a,b" },
 244 { "subcs", 0x29, "c,a,i" },
 245 { "subcu", 0x2a, "c,a,b" },
 246 { "subcu", 0x2b, "c,a,i" },
 247 { "subr", 0x34, "c,a,b" },
 248 { "subr", 0x35, "c,a,i" },
 249 { "subrc", 0x3c, "c,a,b" },
 250 { "subrc", 0x3d, "c,a,i" },
 251 { "subrcs", 0x38, "c,a,b" },
 252 { "subrcs", 0x39, "c,a,i" },
 253 { "subrcu", 0x3a, "c,a,b" },
 254 { "subrcu", 0x3b, "c,a,i" },
 255 { "subrs", 0x30, "c,a,b" },
 256 { "subrs", 0x31, "c,a,i" },
 257 { "subru", 0x32, "c,a,b" },
 258 { "subru", 0x33, "c,a,i" },
 259 { "subs", 0x20, "c,a,b" },
 260 { "subs", 0x21, "c,a,i" },
 261 { "subu", 0x22, "c,a,b" },
 262 { "subu", 0x23, "c,a,i" },
 263 { "xnor", 0x96, "c,a,b" },
 264 { "xnor", 0x97, "c,a,i" },
 265 { "xor", 0x94, "c,a,b" },
 266 { "xor", 0x95, "c,a,i" }
 267
 268 };
 269
 270 #define NUM_OPCODES ((sizeof am29k_opcodes) / (sizeof am29k_opcodes[0]))
 271