1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2013 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
39 #include "gdb_assert.h"
40 #include "exceptions.h"
41 #include "amd64-tdep.h"
42 #include "i387-tdep.h"
44 #include "features/i386/amd64.c"
45 #include "features/i386/amd64-avx.c"
46 #include "features/i386/x32.c"
47 #include "features/i386/x32-avx.c"
52 /* Note that the AMD64 architecture was previously known as x86-64.
53 The latter is (forever) engraved into the canonical system name as
54 returned by config.guess, and used as the name for the AMD64 port
55 of GNU/Linux. The BSD's have renamed their ports to amd64; they
56 don't like to shout. For GDB we prefer the amd64_-prefix over the
57 x86_64_-prefix since it's so much easier to type. */
59 /* Register information. */
61 static const char *amd64_register_names
[] =
63 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
65 /* %r8 is indeed register number 8. */
66 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
67 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
69 /* %st0 is register number 24. */
70 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
71 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
73 /* %xmm0 is register number 40. */
74 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
75 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
79 static const char *amd64_ymm_names
[] =
81 "ymm0", "ymm1", "ymm2", "ymm3",
82 "ymm4", "ymm5", "ymm6", "ymm7",
83 "ymm8", "ymm9", "ymm10", "ymm11",
84 "ymm12", "ymm13", "ymm14", "ymm15"
87 static const char *amd64_ymmh_names
[] =
89 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
90 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
91 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
92 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
95 /* The registers used to pass integer arguments during a function call. */
96 static int amd64_dummy_call_integer_regs
[] =
98 AMD64_RDI_REGNUM
, /* %rdi */
99 AMD64_RSI_REGNUM
, /* %rsi */
100 AMD64_RDX_REGNUM
, /* %rdx */
101 AMD64_RCX_REGNUM
, /* %rcx */
106 /* DWARF Register Number Mapping as defined in the System V psABI,
109 static int amd64_dwarf_regmap
[] =
111 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
112 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
113 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
114 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
116 /* Frame Pointer Register RBP. */
119 /* Stack Pointer Register RSP. */
122 /* Extended Integer Registers 8 - 15. */
123 8, 9, 10, 11, 12, 13, 14, 15,
125 /* Return Address RA. Mapped to RIP. */
128 /* SSE Registers 0 - 7. */
129 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
130 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
131 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
132 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
134 /* Extended SSE Registers 8 - 15. */
135 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
136 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
137 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
138 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
140 /* Floating Point Registers 0-7. */
141 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
142 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
143 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
144 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
146 /* Control and Status Flags Register. */
149 /* Selector Registers. */
159 /* Segment Base Address Registers. */
165 /* Special Selector Registers. */
169 /* Floating Point Control Registers. */
175 static const int amd64_dwarf_regmap_len
=
176 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
178 /* Convert DWARF register number REG to the appropriate register
179 number used by GDB. */
182 amd64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
184 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
185 int ymm0_regnum
= tdep
->ymm0_regnum
;
188 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
189 regnum
= amd64_dwarf_regmap
[reg
];
192 warning (_("Unmapped DWARF Register #%d encountered."), reg
);
193 else if (ymm0_regnum
>= 0
194 && i386_xmm_regnum_p (gdbarch
, regnum
))
195 regnum
+= ymm0_regnum
- I387_XMM0_REGNUM (tdep
);
200 /* Map architectural register numbers to gdb register numbers. */
202 static const int amd64_arch_regmap
[16] =
204 AMD64_RAX_REGNUM
, /* %rax */
205 AMD64_RCX_REGNUM
, /* %rcx */
206 AMD64_RDX_REGNUM
, /* %rdx */
207 AMD64_RBX_REGNUM
, /* %rbx */
208 AMD64_RSP_REGNUM
, /* %rsp */
209 AMD64_RBP_REGNUM
, /* %rbp */
210 AMD64_RSI_REGNUM
, /* %rsi */
211 AMD64_RDI_REGNUM
, /* %rdi */
212 AMD64_R8_REGNUM
, /* %r8 */
213 AMD64_R9_REGNUM
, /* %r9 */
214 AMD64_R10_REGNUM
, /* %r10 */
215 AMD64_R11_REGNUM
, /* %r11 */
216 AMD64_R12_REGNUM
, /* %r12 */
217 AMD64_R13_REGNUM
, /* %r13 */
218 AMD64_R14_REGNUM
, /* %r14 */
219 AMD64_R15_REGNUM
/* %r15 */
222 static const int amd64_arch_regmap_len
=
223 (sizeof (amd64_arch_regmap
) / sizeof (amd64_arch_regmap
[0]));
225 /* Convert architectural register number REG to the appropriate register
226 number used by GDB. */
229 amd64_arch_reg_to_regnum (int reg
)
231 gdb_assert (reg
>= 0 && reg
< amd64_arch_regmap_len
);
233 return amd64_arch_regmap
[reg
];
236 /* Register names for byte pseudo-registers. */
238 static const char *amd64_byte_names
[] =
240 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
241 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
242 "ah", "bh", "ch", "dh"
245 /* Number of lower byte registers. */
246 #define AMD64_NUM_LOWER_BYTE_REGS 16
248 /* Register names for word pseudo-registers. */
250 static const char *amd64_word_names
[] =
252 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
253 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
256 /* Register names for dword pseudo-registers. */
258 static const char *amd64_dword_names
[] =
260 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
261 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
265 /* Return the name of register REGNUM. */
268 amd64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
270 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
271 if (i386_byte_regnum_p (gdbarch
, regnum
))
272 return amd64_byte_names
[regnum
- tdep
->al_regnum
];
273 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
274 return amd64_ymm_names
[regnum
- tdep
->ymm0_regnum
];
275 else if (i386_word_regnum_p (gdbarch
, regnum
))
276 return amd64_word_names
[regnum
- tdep
->ax_regnum
];
277 else if (i386_dword_regnum_p (gdbarch
, regnum
))
278 return amd64_dword_names
[regnum
- tdep
->eax_regnum
];
280 return i386_pseudo_register_name (gdbarch
, regnum
);
283 static struct value
*
284 amd64_pseudo_register_read_value (struct gdbarch
*gdbarch
,
285 struct regcache
*regcache
,
288 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
289 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
290 enum register_status status
;
291 struct value
*result_value
;
294 result_value
= allocate_value (register_type (gdbarch
, regnum
));
295 VALUE_LVAL (result_value
) = lval_register
;
296 VALUE_REGNUM (result_value
) = regnum
;
297 buf
= value_contents_raw (result_value
);
299 if (i386_byte_regnum_p (gdbarch
, regnum
))
301 int gpnum
= regnum
- tdep
->al_regnum
;
303 /* Extract (always little endian). */
304 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
306 /* Special handling for AH, BH, CH, DH. */
307 status
= regcache_raw_read (regcache
,
308 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
,
310 if (status
== REG_VALID
)
311 memcpy (buf
, raw_buf
+ 1, 1);
313 mark_value_bytes_unavailable (result_value
, 0,
314 TYPE_LENGTH (value_type (result_value
)));
318 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
319 if (status
== REG_VALID
)
320 memcpy (buf
, raw_buf
, 1);
322 mark_value_bytes_unavailable (result_value
, 0,
323 TYPE_LENGTH (value_type (result_value
)));
326 else if (i386_dword_regnum_p (gdbarch
, regnum
))
328 int gpnum
= regnum
- tdep
->eax_regnum
;
329 /* Extract (always little endian). */
330 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
331 if (status
== REG_VALID
)
332 memcpy (buf
, raw_buf
, 4);
334 mark_value_bytes_unavailable (result_value
, 0,
335 TYPE_LENGTH (value_type (result_value
)));
338 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
,
345 amd64_pseudo_register_write (struct gdbarch
*gdbarch
,
346 struct regcache
*regcache
,
347 int regnum
, const gdb_byte
*buf
)
349 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
350 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
352 if (i386_byte_regnum_p (gdbarch
, regnum
))
354 int gpnum
= regnum
- tdep
->al_regnum
;
356 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
358 /* Read ... AH, BH, CH, DH. */
359 regcache_raw_read (regcache
,
360 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
361 /* ... Modify ... (always little endian). */
362 memcpy (raw_buf
+ 1, buf
, 1);
364 regcache_raw_write (regcache
,
365 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
370 regcache_raw_read (regcache
, gpnum
, raw_buf
);
371 /* ... Modify ... (always little endian). */
372 memcpy (raw_buf
, buf
, 1);
374 regcache_raw_write (regcache
, gpnum
, raw_buf
);
377 else if (i386_dword_regnum_p (gdbarch
, regnum
))
379 int gpnum
= regnum
- tdep
->eax_regnum
;
382 regcache_raw_read (regcache
, gpnum
, raw_buf
);
383 /* ... Modify ... (always little endian). */
384 memcpy (raw_buf
, buf
, 4);
386 regcache_raw_write (regcache
, gpnum
, raw_buf
);
389 i386_pseudo_register_write (gdbarch
, regcache
, regnum
, buf
);
394 /* Return the union class of CLASS1 and CLASS2. See the psABI for
397 static enum amd64_reg_class
398 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
400 /* Rule (a): If both classes are equal, this is the resulting class. */
401 if (class1
== class2
)
404 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
405 is the other class. */
406 if (class1
== AMD64_NO_CLASS
)
408 if (class2
== AMD64_NO_CLASS
)
411 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
412 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
415 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
416 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
417 return AMD64_INTEGER
;
419 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
420 MEMORY is used as class. */
421 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
422 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
423 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
426 /* Rule (f): Otherwise class SSE is used. */
430 /* Return non-zero if TYPE is a non-POD structure or union type. */
433 amd64_non_pod_p (struct type
*type
)
435 /* ??? A class with a base class certainly isn't POD, but does this
436 catch all non-POD structure types? */
437 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
&& TYPE_N_BASECLASSES (type
) > 0)
443 /* Classify TYPE according to the rules for aggregate (structures and
444 arrays) and union types, and store the result in CLASS. */
447 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class
class[2])
449 /* 1. If the size of an object is larger than two eightbytes, or in
450 C++, is a non-POD structure or union type, or contains
451 unaligned fields, it has class memory. */
452 if (TYPE_LENGTH (type
) > 16 || amd64_non_pod_p (type
))
454 class[0] = class[1] = AMD64_MEMORY
;
458 /* 2. Both eightbytes get initialized to class NO_CLASS. */
459 class[0] = class[1] = AMD64_NO_CLASS
;
461 /* 3. Each field of an object is classified recursively so that
462 always two fields are considered. The resulting class is
463 calculated according to the classes of the fields in the
466 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
468 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
470 /* All fields in an array have the same type. */
471 amd64_classify (subtype
, class);
472 if (TYPE_LENGTH (type
) > 8 && class[1] == AMD64_NO_CLASS
)
479 /* Structure or union. */
480 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
481 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
483 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
485 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
486 int pos
= TYPE_FIELD_BITPOS (type
, i
) / 64;
487 enum amd64_reg_class subclass
[2];
488 int bitsize
= TYPE_FIELD_BITSIZE (type
, i
);
492 bitsize
= TYPE_LENGTH (subtype
) * 8;
493 endpos
= (TYPE_FIELD_BITPOS (type
, i
) + bitsize
- 1) / 64;
495 /* Ignore static fields. */
496 if (field_is_static (&TYPE_FIELD (type
, i
)))
499 gdb_assert (pos
== 0 || pos
== 1);
501 amd64_classify (subtype
, subclass
);
502 class[pos
] = amd64_merge_classes (class[pos
], subclass
[0]);
503 if (bitsize
<= 64 && pos
== 0 && endpos
== 1)
504 /* This is a bit of an odd case: We have a field that would
505 normally fit in one of the two eightbytes, except that
506 it is placed in a way that this field straddles them.
507 This has been seen with a structure containing an array.
509 The ABI is a bit unclear in this case, but we assume that
510 this field's class (stored in subclass[0]) must also be merged
511 into class[1]. In other words, our field has a piece stored
512 in the second eight-byte, and thus its class applies to
513 the second eight-byte as well.
515 In the case where the field length exceeds 8 bytes,
516 it should not be necessary to merge the field class
517 into class[1]. As LEN > 8, subclass[1] is necessarily
518 different from AMD64_NO_CLASS. If subclass[1] is equal
519 to subclass[0], then the normal class[1]/subclass[1]
520 merging will take care of everything. For subclass[1]
521 to be different from subclass[0], I can only see the case
522 where we have a SSE/SSEUP or X87/X87UP pair, which both
523 use up all 16 bytes of the aggregate, and are already
524 handled just fine (because each portion sits on its own
526 class[1] = amd64_merge_classes (class[1], subclass
[0]);
528 class[1] = amd64_merge_classes (class[1], subclass
[1]);
532 /* 4. Then a post merger cleanup is done: */
534 /* Rule (a): If one of the classes is MEMORY, the whole argument is
536 if (class[0] == AMD64_MEMORY
|| class[1] == AMD64_MEMORY
)
537 class[0] = class[1] = AMD64_MEMORY
;
539 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
541 if (class[0] == AMD64_SSEUP
)
542 class[0] = AMD64_SSE
;
543 if (class[1] == AMD64_SSEUP
&& class[0] != AMD64_SSE
)
544 class[1] = AMD64_SSE
;
547 /* Classify TYPE, and store the result in CLASS. */
550 amd64_classify (struct type
*type
, enum amd64_reg_class
class[2])
552 enum type_code code
= TYPE_CODE (type
);
553 int len
= TYPE_LENGTH (type
);
555 class[0] = class[1] = AMD64_NO_CLASS
;
557 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
558 long, long long, and pointers are in the INTEGER class. Similarly,
559 range types, used by languages such as Ada, are also in the INTEGER
561 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
562 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
563 || code
== TYPE_CODE_CHAR
564 || code
== TYPE_CODE_PTR
|| code
== TYPE_CODE_REF
)
565 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
566 class[0] = AMD64_INTEGER
;
568 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
570 else if ((code
== TYPE_CODE_FLT
|| code
== TYPE_CODE_DECFLOAT
)
571 && (len
== 4 || len
== 8))
573 class[0] = AMD64_SSE
;
575 /* Arguments of types __float128, _Decimal128 and __m128 are split into
576 two halves. The least significant ones belong to class SSE, the most
577 significant one to class SSEUP. */
578 else if (code
== TYPE_CODE_DECFLOAT
&& len
== 16)
579 /* FIXME: __float128, __m128. */
580 class[0] = AMD64_SSE
, class[1] = AMD64_SSEUP
;
582 /* The 64-bit mantissa of arguments of type long double belongs to
583 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
585 else if (code
== TYPE_CODE_FLT
&& len
== 16)
586 /* Class X87 and X87UP. */
587 class[0] = AMD64_X87
, class[1] = AMD64_X87UP
;
589 /* Arguments of complex T where T is one of the types float or
590 double get treated as if they are implemented as:
596 else if (code
== TYPE_CODE_COMPLEX
&& len
== 8)
597 class[0] = AMD64_SSE
;
598 else if (code
== TYPE_CODE_COMPLEX
&& len
== 16)
599 class[0] = class[1] = AMD64_SSE
;
601 /* A variable of type complex long double is classified as type
603 else if (code
== TYPE_CODE_COMPLEX
&& len
== 32)
604 class[0] = AMD64_COMPLEX_X87
;
607 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
608 || code
== TYPE_CODE_UNION
)
609 amd64_classify_aggregate (type
, class);
612 static enum return_value_convention
613 amd64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
614 struct type
*type
, struct regcache
*regcache
,
615 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
617 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
618 enum amd64_reg_class
class[2];
619 int len
= TYPE_LENGTH (type
);
620 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
621 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
626 gdb_assert (!(readbuf
&& writebuf
));
627 gdb_assert (tdep
->classify
);
629 /* 1. Classify the return type with the classification algorithm. */
630 tdep
->classify (type
, class);
632 /* 2. If the type has class MEMORY, then the caller provides space
633 for the return value and passes the address of this storage in
634 %rdi as if it were the first argument to the function. In effect,
635 this address becomes a hidden first argument.
637 On return %rax will contain the address that has been passed in
638 by the caller in %rdi. */
639 if (class[0] == AMD64_MEMORY
)
641 /* As indicated by the comment above, the ABI guarantees that we
642 can always find the return value just after the function has
649 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
650 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
653 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
656 /* 8. If the class is COMPLEX_X87, the real part of the value is
657 returned in %st0 and the imaginary part in %st1. */
658 if (class[0] == AMD64_COMPLEX_X87
)
662 regcache_raw_read (regcache
, AMD64_ST0_REGNUM
, readbuf
);
663 regcache_raw_read (regcache
, AMD64_ST1_REGNUM
, readbuf
+ 16);
668 i387_return_value (gdbarch
, regcache
);
669 regcache_raw_write (regcache
, AMD64_ST0_REGNUM
, writebuf
);
670 regcache_raw_write (regcache
, AMD64_ST1_REGNUM
, writebuf
+ 16);
672 /* Fix up the tag word such that both %st(0) and %st(1) are
674 regcache_raw_write_unsigned (regcache
, AMD64_FTAG_REGNUM
, 0xfff);
677 return RETURN_VALUE_REGISTER_CONVENTION
;
680 gdb_assert (class[1] != AMD64_MEMORY
);
681 gdb_assert (len
<= 16);
683 for (i
= 0; len
> 0; i
++, len
-= 8)
691 /* 3. If the class is INTEGER, the next available register
692 of the sequence %rax, %rdx is used. */
693 regnum
= integer_regnum
[integer_reg
++];
697 /* 4. If the class is SSE, the next available SSE register
698 of the sequence %xmm0, %xmm1 is used. */
699 regnum
= sse_regnum
[sse_reg
++];
703 /* 5. If the class is SSEUP, the eightbyte is passed in the
704 upper half of the last used SSE register. */
705 gdb_assert (sse_reg
> 0);
706 regnum
= sse_regnum
[sse_reg
- 1];
711 /* 6. If the class is X87, the value is returned on the X87
712 stack in %st0 as 80-bit x87 number. */
713 regnum
= AMD64_ST0_REGNUM
;
715 i387_return_value (gdbarch
, regcache
);
719 /* 7. If the class is X87UP, the value is returned together
720 with the previous X87 value in %st0. */
721 gdb_assert (i
> 0 && class[0] == AMD64_X87
);
722 regnum
= AMD64_ST0_REGNUM
;
731 gdb_assert (!"Unexpected register class.");
734 gdb_assert (regnum
!= -1);
737 regcache_raw_read_part (regcache
, regnum
, offset
, min (len
, 8),
740 regcache_raw_write_part (regcache
, regnum
, offset
, min (len
, 8),
744 return RETURN_VALUE_REGISTER_CONVENTION
;
749 amd64_push_arguments (struct regcache
*regcache
, int nargs
,
750 struct value
**args
, CORE_ADDR sp
, int struct_return
)
752 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
753 int *integer_regs
= tdep
->call_dummy_integer_regs
;
754 int num_integer_regs
= tdep
->call_dummy_num_integer_regs
;
756 static int sse_regnum
[] =
758 /* %xmm0 ... %xmm7 */
759 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
760 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
761 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
762 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
764 struct value
**stack_args
= alloca (nargs
* sizeof (struct value
*));
765 int num_stack_args
= 0;
766 int num_elements
= 0;
772 gdb_assert (tdep
->classify
);
774 /* Reserve a register for the "hidden" argument. */
778 for (i
= 0; i
< nargs
; i
++)
780 struct type
*type
= value_type (args
[i
]);
781 int len
= TYPE_LENGTH (type
);
782 enum amd64_reg_class
class[2];
783 int needed_integer_regs
= 0;
784 int needed_sse_regs
= 0;
787 /* Classify argument. */
788 tdep
->classify (type
, class);
790 /* Calculate the number of integer and SSE registers needed for
792 for (j
= 0; j
< 2; j
++)
794 if (class[j
] == AMD64_INTEGER
)
795 needed_integer_regs
++;
796 else if (class[j
] == AMD64_SSE
)
800 /* Check whether enough registers are available, and if the
801 argument should be passed in registers at all. */
802 if (integer_reg
+ needed_integer_regs
> num_integer_regs
803 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
804 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
806 /* The argument will be passed on the stack. */
807 num_elements
+= ((len
+ 7) / 8);
808 stack_args
[num_stack_args
++] = args
[i
];
812 /* The argument will be passed in registers. */
813 const gdb_byte
*valbuf
= value_contents (args
[i
]);
816 gdb_assert (len
<= 16);
818 for (j
= 0; len
> 0; j
++, len
-= 8)
826 regnum
= integer_regs
[integer_reg
++];
830 regnum
= sse_regnum
[sse_reg
++];
834 gdb_assert (sse_reg
> 0);
835 regnum
= sse_regnum
[sse_reg
- 1];
840 gdb_assert (!"Unexpected register class.");
843 gdb_assert (regnum
!= -1);
844 memset (buf
, 0, sizeof buf
);
845 memcpy (buf
, valbuf
+ j
* 8, min (len
, 8));
846 regcache_raw_write_part (regcache
, regnum
, offset
, 8, buf
);
851 /* Allocate space for the arguments on the stack. */
852 sp
-= num_elements
* 8;
854 /* The psABI says that "The end of the input argument area shall be
855 aligned on a 16 byte boundary." */
858 /* Write out the arguments to the stack. */
859 for (i
= 0; i
< num_stack_args
; i
++)
861 struct type
*type
= value_type (stack_args
[i
]);
862 const gdb_byte
*valbuf
= value_contents (stack_args
[i
]);
863 int len
= TYPE_LENGTH (type
);
865 write_memory (sp
+ element
* 8, valbuf
, len
);
866 element
+= ((len
+ 7) / 8);
869 /* The psABI says that "For calls that may call functions that use
870 varargs or stdargs (prototype-less calls or calls to functions
871 containing ellipsis (...) in the declaration) %al is used as
872 hidden argument to specify the number of SSE registers used. */
873 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
878 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
879 struct regcache
*regcache
, CORE_ADDR bp_addr
,
880 int nargs
, struct value
**args
, CORE_ADDR sp
,
881 int struct_return
, CORE_ADDR struct_addr
)
883 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
884 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
887 /* Pass arguments. */
888 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, struct_return
);
890 /* Pass "hidden" argument". */
893 /* The "hidden" argument is passed throught the first argument
895 const int arg_regnum
= tdep
->call_dummy_integer_regs
[0];
897 store_unsigned_integer (buf
, 8, byte_order
, struct_addr
);
898 regcache_cooked_write (regcache
, arg_regnum
, buf
);
901 /* Store return address. */
903 store_unsigned_integer (buf
, 8, byte_order
, bp_addr
);
904 write_memory (sp
, buf
, 8);
906 /* Finally, update the stack pointer... */
907 store_unsigned_integer (buf
, 8, byte_order
, sp
);
908 regcache_cooked_write (regcache
, AMD64_RSP_REGNUM
, buf
);
910 /* ...and fake a frame pointer. */
911 regcache_cooked_write (regcache
, AMD64_RBP_REGNUM
, buf
);
916 /* Displaced instruction handling. */
918 /* A partially decoded instruction.
919 This contains enough details for displaced stepping purposes. */
923 /* The number of opcode bytes. */
925 /* The offset of the rex prefix or -1 if not present. */
927 /* The offset to the first opcode byte. */
929 /* The offset to the modrm byte or -1 if not present. */
932 /* The raw instruction. */
936 struct displaced_step_closure
938 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
943 /* Details of the instruction. */
944 struct amd64_insn insn_details
;
946 /* Amount of space allocated to insn_buf. */
949 /* The possibly modified insn.
950 This is a variable-length field. */
951 gdb_byte insn_buf
[1];
954 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
955 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
956 at which point delete these in favor of libopcodes' versions). */
958 static const unsigned char onebyte_has_modrm
[256] = {
959 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
960 /* ------------------------------- */
961 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
962 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
963 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
964 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
965 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
966 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
967 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
968 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
969 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
970 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
971 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
972 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
973 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
974 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
975 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
976 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
977 /* ------------------------------- */
978 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
981 static const unsigned char twobyte_has_modrm
[256] = {
982 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
983 /* ------------------------------- */
984 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
985 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
986 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
987 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
988 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
989 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
990 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
991 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
992 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
993 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
994 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
995 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
996 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
997 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
998 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
999 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1000 /* ------------------------------- */
1001 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1004 static int amd64_syscall_p (const struct amd64_insn
*insn
, int *lengthp
);
1007 rex_prefix_p (gdb_byte pfx
)
1009 return REX_PREFIX_P (pfx
);
1012 /* Skip the legacy instruction prefixes in INSN.
1013 We assume INSN is properly sentineled so we don't have to worry
1014 about falling off the end of the buffer. */
1017 amd64_skip_prefixes (gdb_byte
*insn
)
1023 case DATA_PREFIX_OPCODE
:
1024 case ADDR_PREFIX_OPCODE
:
1025 case CS_PREFIX_OPCODE
:
1026 case DS_PREFIX_OPCODE
:
1027 case ES_PREFIX_OPCODE
:
1028 case FS_PREFIX_OPCODE
:
1029 case GS_PREFIX_OPCODE
:
1030 case SS_PREFIX_OPCODE
:
1031 case LOCK_PREFIX_OPCODE
:
1032 case REPE_PREFIX_OPCODE
:
1033 case REPNE_PREFIX_OPCODE
:
1045 /* Return an integer register (other than RSP) that is unused as an input
1047 In order to not require adding a rex prefix if the insn doesn't already
1048 have one, the result is restricted to RAX ... RDI, sans RSP.
1049 The register numbering of the result follows architecture ordering,
1053 amd64_get_unused_input_int_reg (const struct amd64_insn
*details
)
1055 /* 1 bit for each reg */
1056 int used_regs_mask
= 0;
1058 /* There can be at most 3 int regs used as inputs in an insn, and we have
1059 7 to choose from (RAX ... RDI, sans RSP).
1060 This allows us to take a conservative approach and keep things simple.
1061 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1062 that implicitly specify RAX. */
1065 used_regs_mask
|= 1 << EAX_REG_NUM
;
1066 /* Similarily avoid RDX, implicit operand in divides. */
1067 used_regs_mask
|= 1 << EDX_REG_NUM
;
1069 used_regs_mask
|= 1 << ESP_REG_NUM
;
1071 /* If the opcode is one byte long and there's no ModRM byte,
1072 assume the opcode specifies a register. */
1073 if (details
->opcode_len
== 1 && details
->modrm_offset
== -1)
1074 used_regs_mask
|= 1 << (details
->raw_insn
[details
->opcode_offset
] & 7);
1076 /* Mark used regs in the modrm/sib bytes. */
1077 if (details
->modrm_offset
!= -1)
1079 int modrm
= details
->raw_insn
[details
->modrm_offset
];
1080 int mod
= MODRM_MOD_FIELD (modrm
);
1081 int reg
= MODRM_REG_FIELD (modrm
);
1082 int rm
= MODRM_RM_FIELD (modrm
);
1083 int have_sib
= mod
!= 3 && rm
== 4;
1085 /* Assume the reg field of the modrm byte specifies a register. */
1086 used_regs_mask
|= 1 << reg
;
1090 int base
= SIB_BASE_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1091 int idx
= SIB_INDEX_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1092 used_regs_mask
|= 1 << base
;
1093 used_regs_mask
|= 1 << idx
;
1097 used_regs_mask
|= 1 << rm
;
1101 gdb_assert (used_regs_mask
< 256);
1102 gdb_assert (used_regs_mask
!= 255);
1104 /* Finally, find a free reg. */
1108 for (i
= 0; i
< 8; ++i
)
1110 if (! (used_regs_mask
& (1 << i
)))
1114 /* We shouldn't get here. */
1115 internal_error (__FILE__
, __LINE__
, _("unable to find free reg"));
1119 /* Extract the details of INSN that we need. */
1122 amd64_get_insn_details (gdb_byte
*insn
, struct amd64_insn
*details
)
1124 gdb_byte
*start
= insn
;
1127 details
->raw_insn
= insn
;
1129 details
->opcode_len
= -1;
1130 details
->rex_offset
= -1;
1131 details
->opcode_offset
= -1;
1132 details
->modrm_offset
= -1;
1134 /* Skip legacy instruction prefixes. */
1135 insn
= amd64_skip_prefixes (insn
);
1137 /* Skip REX instruction prefix. */
1138 if (rex_prefix_p (*insn
))
1140 details
->rex_offset
= insn
- start
;
1144 details
->opcode_offset
= insn
- start
;
1146 if (*insn
== TWO_BYTE_OPCODE_ESCAPE
)
1148 /* Two or three-byte opcode. */
1150 need_modrm
= twobyte_has_modrm
[*insn
];
1152 /* Check for three-byte opcode. */
1162 details
->opcode_len
= 3;
1165 details
->opcode_len
= 2;
1171 /* One-byte opcode. */
1172 need_modrm
= onebyte_has_modrm
[*insn
];
1173 details
->opcode_len
= 1;
1179 details
->modrm_offset
= insn
- start
;
1183 /* Update %rip-relative addressing in INSN.
1185 %rip-relative addressing only uses a 32-bit displacement.
1186 32 bits is not enough to be guaranteed to cover the distance between where
1187 the real instruction is and where its copy is.
1188 Convert the insn to use base+disp addressing.
1189 We set base = pc + insn_length so we can leave disp unchanged. */
1192 fixup_riprel (struct gdbarch
*gdbarch
, struct displaced_step_closure
*dsc
,
1193 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1195 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1196 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1197 int modrm_offset
= insn_details
->modrm_offset
;
1198 gdb_byte
*insn
= insn_details
->raw_insn
+ modrm_offset
;
1202 int arch_tmp_regno
, tmp_regno
;
1203 ULONGEST orig_value
;
1205 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1208 /* Compute the rip-relative address. */
1209 disp
= extract_signed_integer (insn
, sizeof (int32_t), byte_order
);
1210 insn_length
= gdb_buffered_insn_length (gdbarch
, dsc
->insn_buf
,
1211 dsc
->max_len
, from
);
1212 rip_base
= from
+ insn_length
;
1214 /* We need a register to hold the address.
1215 Pick one not used in the insn.
1216 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1217 arch_tmp_regno
= amd64_get_unused_input_int_reg (insn_details
);
1218 tmp_regno
= amd64_arch_reg_to_regnum (arch_tmp_regno
);
1220 /* REX.B should be unset as we were using rip-relative addressing,
1221 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1222 if (insn_details
->rex_offset
!= -1)
1223 dsc
->insn_buf
[insn_details
->rex_offset
] &= ~REX_B
;
1225 regcache_cooked_read_unsigned (regs
, tmp_regno
, &orig_value
);
1226 dsc
->tmp_regno
= tmp_regno
;
1227 dsc
->tmp_save
= orig_value
;
1230 /* Convert the ModRM field to be base+disp. */
1231 dsc
->insn_buf
[modrm_offset
] &= ~0xc7;
1232 dsc
->insn_buf
[modrm_offset
] |= 0x80 + arch_tmp_regno
;
1234 regcache_cooked_write_unsigned (regs
, tmp_regno
, rip_base
);
1236 if (debug_displaced
)
1237 fprintf_unfiltered (gdb_stdlog
, "displaced: %%rip-relative addressing used.\n"
1238 "displaced: using temp reg %d, old value %s, new value %s\n",
1239 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
),
1240 paddress (gdbarch
, rip_base
));
1244 fixup_displaced_copy (struct gdbarch
*gdbarch
,
1245 struct displaced_step_closure
*dsc
,
1246 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1248 const struct amd64_insn
*details
= &dsc
->insn_details
;
1250 if (details
->modrm_offset
!= -1)
1252 gdb_byte modrm
= details
->raw_insn
[details
->modrm_offset
];
1254 if ((modrm
& 0xc7) == 0x05)
1256 /* The insn uses rip-relative addressing.
1258 fixup_riprel (gdbarch
, dsc
, from
, to
, regs
);
1263 struct displaced_step_closure
*
1264 amd64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1265 CORE_ADDR from
, CORE_ADDR to
,
1266 struct regcache
*regs
)
1268 int len
= gdbarch_max_insn_length (gdbarch
);
1269 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1270 continually watch for running off the end of the buffer. */
1271 int fixup_sentinel_space
= len
;
1272 struct displaced_step_closure
*dsc
=
1273 xmalloc (sizeof (*dsc
) + len
+ fixup_sentinel_space
);
1274 gdb_byte
*buf
= &dsc
->insn_buf
[0];
1275 struct amd64_insn
*details
= &dsc
->insn_details
;
1278 dsc
->max_len
= len
+ fixup_sentinel_space
;
1280 read_memory (from
, buf
, len
);
1282 /* Set up the sentinel space so we don't have to worry about running
1283 off the end of the buffer. An excessive number of leading prefixes
1284 could otherwise cause this. */
1285 memset (buf
+ len
, 0, fixup_sentinel_space
);
1287 amd64_get_insn_details (buf
, details
);
1289 /* GDB may get control back after the insn after the syscall.
1290 Presumably this is a kernel bug.
1291 If this is a syscall, make sure there's a nop afterwards. */
1295 if (amd64_syscall_p (details
, &syscall_length
))
1296 buf
[details
->opcode_offset
+ syscall_length
] = NOP_OPCODE
;
1299 /* Modify the insn to cope with the address where it will be executed from.
1300 In particular, handle any rip-relative addressing. */
1301 fixup_displaced_copy (gdbarch
, dsc
, from
, to
, regs
);
1303 write_memory (to
, buf
, len
);
1305 if (debug_displaced
)
1307 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1308 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1309 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1316 amd64_absolute_jmp_p (const struct amd64_insn
*details
)
1318 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1320 if (insn
[0] == 0xff)
1322 /* jump near, absolute indirect (/4) */
1323 if ((insn
[1] & 0x38) == 0x20)
1326 /* jump far, absolute indirect (/5) */
1327 if ((insn
[1] & 0x38) == 0x28)
1335 amd64_absolute_call_p (const struct amd64_insn
*details
)
1337 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1339 if (insn
[0] == 0xff)
1341 /* Call near, absolute indirect (/2) */
1342 if ((insn
[1] & 0x38) == 0x10)
1345 /* Call far, absolute indirect (/3) */
1346 if ((insn
[1] & 0x38) == 0x18)
1354 amd64_ret_p (const struct amd64_insn
*details
)
1356 /* NOTE: gcc can emit "repz ; ret". */
1357 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1361 case 0xc2: /* ret near, pop N bytes */
1362 case 0xc3: /* ret near */
1363 case 0xca: /* ret far, pop N bytes */
1364 case 0xcb: /* ret far */
1365 case 0xcf: /* iret */
1374 amd64_call_p (const struct amd64_insn
*details
)
1376 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1378 if (amd64_absolute_call_p (details
))
1381 /* call near, relative */
1382 if (insn
[0] == 0xe8)
1388 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1389 length in bytes. Otherwise, return zero. */
1392 amd64_syscall_p (const struct amd64_insn
*details
, int *lengthp
)
1394 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1396 if (insn
[0] == 0x0f && insn
[1] == 0x05)
1405 /* Fix up the state of registers and memory after having single-stepped
1406 a displaced instruction. */
1409 amd64_displaced_step_fixup (struct gdbarch
*gdbarch
,
1410 struct displaced_step_closure
*dsc
,
1411 CORE_ADDR from
, CORE_ADDR to
,
1412 struct regcache
*regs
)
1414 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1415 /* The offset we applied to the instruction's address. */
1416 ULONGEST insn_offset
= to
- from
;
1417 gdb_byte
*insn
= dsc
->insn_buf
;
1418 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1420 if (debug_displaced
)
1421 fprintf_unfiltered (gdb_stdlog
,
1422 "displaced: fixup (%s, %s), "
1423 "insn = 0x%02x 0x%02x ...\n",
1424 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1427 /* If we used a tmp reg, restore it. */
1431 if (debug_displaced
)
1432 fprintf_unfiltered (gdb_stdlog
, "displaced: restoring reg %d to %s\n",
1433 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
));
1434 regcache_cooked_write_unsigned (regs
, dsc
->tmp_regno
, dsc
->tmp_save
);
1437 /* The list of issues to contend with here is taken from
1438 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1439 Yay for Free Software! */
1441 /* Relocate the %rip back to the program's instruction stream,
1444 /* Except in the case of absolute or indirect jump or call
1445 instructions, or a return instruction, the new rip is relative to
1446 the displaced instruction; make it relative to the original insn.
1447 Well, signal handler returns don't need relocation either, but we use the
1448 value of %rip to recognize those; see below. */
1449 if (! amd64_absolute_jmp_p (insn_details
)
1450 && ! amd64_absolute_call_p (insn_details
)
1451 && ! amd64_ret_p (insn_details
))
1456 regcache_cooked_read_unsigned (regs
, AMD64_RIP_REGNUM
, &orig_rip
);
1458 /* A signal trampoline system call changes the %rip, resuming
1459 execution of the main program after the signal handler has
1460 returned. That makes them like 'return' instructions; we
1461 shouldn't relocate %rip.
1463 But most system calls don't, and we do need to relocate %rip.
1465 Our heuristic for distinguishing these cases: if stepping
1466 over the system call instruction left control directly after
1467 the instruction, the we relocate --- control almost certainly
1468 doesn't belong in the displaced copy. Otherwise, we assume
1469 the instruction has put control where it belongs, and leave
1470 it unrelocated. Goodness help us if there are PC-relative
1472 if (amd64_syscall_p (insn_details
, &insn_len
)
1473 && orig_rip
!= to
+ insn_len
1474 /* GDB can get control back after the insn after the syscall.
1475 Presumably this is a kernel bug.
1476 Fixup ensures its a nop, we add one to the length for it. */
1477 && orig_rip
!= to
+ insn_len
+ 1)
1479 if (debug_displaced
)
1480 fprintf_unfiltered (gdb_stdlog
,
1481 "displaced: syscall changed %%rip; "
1482 "not relocating\n");
1486 ULONGEST rip
= orig_rip
- insn_offset
;
1488 /* If we just stepped over a breakpoint insn, we don't backup
1489 the pc on purpose; this is to match behaviour without
1492 regcache_cooked_write_unsigned (regs
, AMD64_RIP_REGNUM
, rip
);
1494 if (debug_displaced
)
1495 fprintf_unfiltered (gdb_stdlog
,
1497 "relocated %%rip from %s to %s\n",
1498 paddress (gdbarch
, orig_rip
),
1499 paddress (gdbarch
, rip
));
1503 /* If the instruction was PUSHFL, then the TF bit will be set in the
1504 pushed value, and should be cleared. We'll leave this for later,
1505 since GDB already messes up the TF flag when stepping over a
1508 /* If the instruction was a call, the return address now atop the
1509 stack is the address following the copied instruction. We need
1510 to make it the address following the original instruction. */
1511 if (amd64_call_p (insn_details
))
1515 const ULONGEST retaddr_len
= 8;
1517 regcache_cooked_read_unsigned (regs
, AMD64_RSP_REGNUM
, &rsp
);
1518 retaddr
= read_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
);
1519 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
1520 write_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
, retaddr
);
1522 if (debug_displaced
)
1523 fprintf_unfiltered (gdb_stdlog
,
1524 "displaced: relocated return addr at %s "
1526 paddress (gdbarch
, rsp
),
1527 paddress (gdbarch
, retaddr
));
1531 /* If the instruction INSN uses RIP-relative addressing, return the
1532 offset into the raw INSN where the displacement to be adjusted is
1533 found. Returns 0 if the instruction doesn't use RIP-relative
1537 rip_relative_offset (struct amd64_insn
*insn
)
1539 if (insn
->modrm_offset
!= -1)
1541 gdb_byte modrm
= insn
->raw_insn
[insn
->modrm_offset
];
1543 if ((modrm
& 0xc7) == 0x05)
1545 /* The displacement is found right after the ModRM byte. */
1546 return insn
->modrm_offset
+ 1;
1554 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
1556 target_write_memory (*to
, buf
, len
);
1561 amd64_relocate_instruction (struct gdbarch
*gdbarch
,
1562 CORE_ADDR
*to
, CORE_ADDR oldloc
)
1564 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1565 int len
= gdbarch_max_insn_length (gdbarch
);
1566 /* Extra space for sentinels. */
1567 int fixup_sentinel_space
= len
;
1568 gdb_byte
*buf
= xmalloc (len
+ fixup_sentinel_space
);
1569 struct amd64_insn insn_details
;
1571 LONGEST rel32
, newrel
;
1575 read_memory (oldloc
, buf
, len
);
1577 /* Set up the sentinel space so we don't have to worry about running
1578 off the end of the buffer. An excessive number of leading prefixes
1579 could otherwise cause this. */
1580 memset (buf
+ len
, 0, fixup_sentinel_space
);
1583 amd64_get_insn_details (insn
, &insn_details
);
1585 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
, len
, oldloc
);
1587 /* Skip legacy instruction prefixes. */
1588 insn
= amd64_skip_prefixes (insn
);
1590 /* Adjust calls with 32-bit relative addresses as push/jump, with
1591 the address pushed being the location where the original call in
1592 the user program would return to. */
1593 if (insn
[0] == 0xe8)
1595 gdb_byte push_buf
[16];
1596 unsigned int ret_addr
;
1598 /* Where "ret" in the original code will return to. */
1599 ret_addr
= oldloc
+ insn_length
;
1600 push_buf
[0] = 0x68; /* pushq $... */
1601 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
1602 /* Push the push. */
1603 append_insns (to
, 5, push_buf
);
1605 /* Convert the relative call to a relative jump. */
1608 /* Adjust the destination offset. */
1609 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1610 newrel
= (oldloc
- *to
) + rel32
;
1611 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1613 if (debug_displaced
)
1614 fprintf_unfiltered (gdb_stdlog
,
1615 "Adjusted insn rel32=%s at %s to"
1616 " rel32=%s at %s\n",
1617 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1618 hex_string (newrel
), paddress (gdbarch
, *to
));
1620 /* Write the adjusted jump into its displaced location. */
1621 append_insns (to
, 5, insn
);
1625 offset
= rip_relative_offset (&insn_details
);
1628 /* Adjust jumps with 32-bit relative addresses. Calls are
1629 already handled above. */
1630 if (insn
[0] == 0xe9)
1632 /* Adjust conditional jumps. */
1633 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1639 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1640 newrel
= (oldloc
- *to
) + rel32
;
1641 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1642 if (debug_displaced
)
1643 fprintf_unfiltered (gdb_stdlog
,
1644 "Adjusted insn rel32=%s at %s to"
1645 " rel32=%s at %s\n",
1646 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1647 hex_string (newrel
), paddress (gdbarch
, *to
));
1650 /* Write the adjusted instruction into its displaced location. */
1651 append_insns (to
, insn_length
, buf
);
1655 /* The maximum number of saved registers. This should include %rip. */
1656 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1658 struct amd64_frame_cache
1663 CORE_ADDR sp_offset
;
1666 /* Saved registers. */
1667 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
1671 /* Do we have a frame? */
1675 /* Initialize a frame cache. */
1678 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
1685 cache
->sp_offset
= -8;
1688 /* Saved registers. We initialize these to -1 since zero is a valid
1689 offset (that's where %rbp is supposed to be stored).
1690 The values start out as being offsets, and are later converted to
1691 addresses (at which point -1 is interpreted as an address, still meaning
1693 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1694 cache
->saved_regs
[i
] = -1;
1695 cache
->saved_sp
= 0;
1696 cache
->saved_sp_reg
= -1;
1698 /* Frameless until proven otherwise. */
1699 cache
->frameless_p
= 1;
1702 /* Allocate and initialize a frame cache. */
1704 static struct amd64_frame_cache
*
1705 amd64_alloc_frame_cache (void)
1707 struct amd64_frame_cache
*cache
;
1709 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
1710 amd64_init_frame_cache (cache
);
1714 /* GCC 4.4 and later, can put code in the prologue to realign the
1715 stack pointer. Check whether PC points to such code, and update
1716 CACHE accordingly. Return the first instruction after the code
1717 sequence or CURRENT_PC, whichever is smaller. If we don't
1718 recognize the code, return PC. */
1721 amd64_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1722 struct amd64_frame_cache
*cache
)
1724 /* There are 2 code sequences to re-align stack before the frame
1727 1. Use a caller-saved saved register:
1733 2. Use a callee-saved saved register:
1740 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1742 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1743 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1748 int offset
, offset_and
;
1750 if (target_read_memory (pc
, buf
, sizeof buf
))
1753 /* Check caller-saved saved register. The first instruction has
1754 to be "leaq 8(%rsp), %reg". */
1755 if ((buf
[0] & 0xfb) == 0x48
1760 /* MOD must be binary 10 and R/M must be binary 100. */
1761 if ((buf
[2] & 0xc7) != 0x44)
1764 /* REG has register number. */
1765 reg
= (buf
[2] >> 3) & 7;
1767 /* Check the REX.R bit. */
1775 /* Check callee-saved saved register. The first instruction
1776 has to be "pushq %reg". */
1778 if ((buf
[0] & 0xf8) == 0x50)
1780 else if ((buf
[0] & 0xf6) == 0x40
1781 && (buf
[1] & 0xf8) == 0x50)
1783 /* Check the REX.B bit. */
1784 if ((buf
[0] & 1) != 0)
1793 reg
+= buf
[offset
] & 0x7;
1797 /* The next instruction has to be "leaq 16(%rsp), %reg". */
1798 if ((buf
[offset
] & 0xfb) != 0x48
1799 || buf
[offset
+ 1] != 0x8d
1800 || buf
[offset
+ 3] != 0x24
1801 || buf
[offset
+ 4] != 0x10)
1804 /* MOD must be binary 10 and R/M must be binary 100. */
1805 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
1808 /* REG has register number. */
1809 r
= (buf
[offset
+ 2] >> 3) & 7;
1811 /* Check the REX.R bit. */
1812 if (buf
[offset
] == 0x4c)
1815 /* Registers in pushq and leaq have to be the same. */
1822 /* Rigister can't be %rsp nor %rbp. */
1823 if (reg
== 4 || reg
== 5)
1826 /* The next instruction has to be "andq $-XXX, %rsp". */
1827 if (buf
[offset
] != 0x48
1828 || buf
[offset
+ 2] != 0xe4
1829 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
1832 offset_and
= offset
;
1833 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
1835 /* The next instruction has to be "pushq -8(%reg)". */
1837 if (buf
[offset
] == 0xff)
1839 else if ((buf
[offset
] & 0xf6) == 0x40
1840 && buf
[offset
+ 1] == 0xff)
1842 /* Check the REX.B bit. */
1843 if ((buf
[offset
] & 0x1) != 0)
1850 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
1852 if (buf
[offset
+ 1] != 0xf8
1853 || (buf
[offset
] & 0xf8) != 0x70)
1856 /* R/M has register. */
1857 r
+= buf
[offset
] & 7;
1859 /* Registers in leaq and pushq have to be the same. */
1863 if (current_pc
> pc
+ offset_and
)
1864 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
1866 return min (pc
+ offset
+ 2, current_pc
);
1869 /* Similar to amd64_analyze_stack_align for x32. */
1872 amd64_x32_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1873 struct amd64_frame_cache
*cache
)
1875 /* There are 2 code sequences to re-align stack before the frame
1878 1. Use a caller-saved saved register:
1886 [addr32] leal 8(%rsp), %reg
1888 [addr32] pushq -8(%reg)
1890 2. Use a callee-saved saved register:
1900 [addr32] leal 16(%rsp), %reg
1902 [addr32] pushq -8(%reg)
1904 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1906 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1907 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1909 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1911 0x83 0xe4 0xf0 andl $-16, %esp
1912 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1917 int offset
, offset_and
;
1919 if (target_read_memory (pc
, buf
, sizeof buf
))
1922 /* Skip optional addr32 prefix. */
1923 offset
= buf
[0] == 0x67 ? 1 : 0;
1925 /* Check caller-saved saved register. The first instruction has
1926 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
1927 if (((buf
[offset
] & 0xfb) == 0x48 || (buf
[offset
] & 0xfb) == 0x40)
1928 && buf
[offset
+ 1] == 0x8d
1929 && buf
[offset
+ 3] == 0x24
1930 && buf
[offset
+ 4] == 0x8)
1932 /* MOD must be binary 10 and R/M must be binary 100. */
1933 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
1936 /* REG has register number. */
1937 reg
= (buf
[offset
+ 2] >> 3) & 7;
1939 /* Check the REX.R bit. */
1940 if ((buf
[offset
] & 0x4) != 0)
1947 /* Check callee-saved saved register. The first instruction
1948 has to be "pushq %reg". */
1950 if ((buf
[offset
] & 0xf6) == 0x40
1951 && (buf
[offset
+ 1] & 0xf8) == 0x50)
1953 /* Check the REX.B bit. */
1954 if ((buf
[offset
] & 1) != 0)
1959 else if ((buf
[offset
] & 0xf8) != 0x50)
1963 reg
+= buf
[offset
] & 0x7;
1967 /* Skip optional addr32 prefix. */
1968 if (buf
[offset
] == 0x67)
1971 /* The next instruction has to be "leaq 16(%rsp), %reg" or
1972 "leal 16(%rsp), %reg". */
1973 if (((buf
[offset
] & 0xfb) != 0x48 && (buf
[offset
] & 0xfb) != 0x40)
1974 || buf
[offset
+ 1] != 0x8d
1975 || buf
[offset
+ 3] != 0x24
1976 || buf
[offset
+ 4] != 0x10)
1979 /* MOD must be binary 10 and R/M must be binary 100. */
1980 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
1983 /* REG has register number. */
1984 r
= (buf
[offset
+ 2] >> 3) & 7;
1986 /* Check the REX.R bit. */
1987 if ((buf
[offset
] & 0x4) != 0)
1990 /* Registers in pushq and leaq have to be the same. */
1997 /* Rigister can't be %rsp nor %rbp. */
1998 if (reg
== 4 || reg
== 5)
2001 /* The next instruction may be "andq $-XXX, %rsp" or
2002 "andl $-XXX, %esp". */
2003 if (buf
[offset
] != 0x48)
2006 if (buf
[offset
+ 2] != 0xe4
2007 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2010 offset_and
= offset
;
2011 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2013 /* Skip optional addr32 prefix. */
2014 if (buf
[offset
] == 0x67)
2017 /* The next instruction has to be "pushq -8(%reg)". */
2019 if (buf
[offset
] == 0xff)
2021 else if ((buf
[offset
] & 0xf6) == 0x40
2022 && buf
[offset
+ 1] == 0xff)
2024 /* Check the REX.B bit. */
2025 if ((buf
[offset
] & 0x1) != 0)
2032 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2034 if (buf
[offset
+ 1] != 0xf8
2035 || (buf
[offset
] & 0xf8) != 0x70)
2038 /* R/M has register. */
2039 r
+= buf
[offset
] & 7;
2041 /* Registers in leaq and pushq have to be the same. */
2045 if (current_pc
> pc
+ offset_and
)
2046 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2048 return min (pc
+ offset
+ 2, current_pc
);
2051 /* Do a limited analysis of the prologue at PC and update CACHE
2052 accordingly. Bail out early if CURRENT_PC is reached. Return the
2053 address where the analysis stopped.
2055 We will handle only functions beginning with:
2058 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2060 or (for the X32 ABI):
2063 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2065 Any function that doesn't start with one of these sequences will be
2066 assumed to have no prologue and thus no valid frame pointer in
2070 amd64_analyze_prologue (struct gdbarch
*gdbarch
,
2071 CORE_ADDR pc
, CORE_ADDR current_pc
,
2072 struct amd64_frame_cache
*cache
)
2074 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2075 /* There are two variations of movq %rsp, %rbp. */
2076 static const gdb_byte mov_rsp_rbp_1
[3] = { 0x48, 0x89, 0xe5 };
2077 static const gdb_byte mov_rsp_rbp_2
[3] = { 0x48, 0x8b, 0xec };
2078 /* Ditto for movl %esp, %ebp. */
2079 static const gdb_byte mov_esp_ebp_1
[2] = { 0x89, 0xe5 };
2080 static const gdb_byte mov_esp_ebp_2
[2] = { 0x8b, 0xec };
2085 if (current_pc
<= pc
)
2088 if (gdbarch_ptr_bit (gdbarch
) == 32)
2089 pc
= amd64_x32_analyze_stack_align (pc
, current_pc
, cache
);
2091 pc
= amd64_analyze_stack_align (pc
, current_pc
, cache
);
2093 op
= read_memory_unsigned_integer (pc
, 1, byte_order
);
2095 if (op
== 0x55) /* pushq %rbp */
2097 /* Take into account that we've executed the `pushq %rbp' that
2098 starts this instruction sequence. */
2099 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
2100 cache
->sp_offset
+= 8;
2102 /* If that's all, return now. */
2103 if (current_pc
<= pc
+ 1)
2106 read_memory (pc
+ 1, buf
, 3);
2108 /* Check for `movq %rsp, %rbp'. */
2109 if (memcmp (buf
, mov_rsp_rbp_1
, 3) == 0
2110 || memcmp (buf
, mov_rsp_rbp_2
, 3) == 0)
2112 /* OK, we actually have a frame. */
2113 cache
->frameless_p
= 0;
2117 /* For X32, also check for `movq %esp, %ebp'. */
2118 if (gdbarch_ptr_bit (gdbarch
) == 32)
2120 if (memcmp (buf
, mov_esp_ebp_1
, 2) == 0
2121 || memcmp (buf
, mov_esp_ebp_2
, 2) == 0)
2123 /* OK, we actually have a frame. */
2124 cache
->frameless_p
= 0;
2135 /* Work around false termination of prologue - GCC PR debug/48827.
2137 START_PC is the first instruction of a function, PC is its minimal already
2138 determined advanced address. Function returns PC if it has nothing to do.
2142 <-- here is 0 lines advance - the false prologue end marker.
2143 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2144 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2145 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2146 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2147 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2148 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2149 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2150 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2154 amd64_skip_xmm_prologue (CORE_ADDR pc
, CORE_ADDR start_pc
)
2156 struct symtab_and_line start_pc_sal
, next_sal
;
2157 gdb_byte buf
[4 + 8 * 7];
2163 start_pc_sal
= find_pc_sect_line (start_pc
, NULL
, 0);
2164 if (start_pc_sal
.symtab
== NULL
2165 || producer_is_gcc_ge_4 (start_pc_sal
.symtab
->producer
) < 6
2166 || start_pc_sal
.pc
!= start_pc
|| pc
>= start_pc_sal
.end
)
2169 next_sal
= find_pc_sect_line (start_pc_sal
.end
, NULL
, 0);
2170 if (next_sal
.line
!= start_pc_sal
.line
)
2173 /* START_PC can be from overlayed memory, ignored here. */
2174 if (target_read_memory (next_sal
.pc
- 4, buf
, sizeof (buf
)) != 0)
2178 if (buf
[0] != 0x84 || buf
[1] != 0xc0)
2185 for (xmmreg
= 0; xmmreg
< 8; xmmreg
++)
2187 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2188 if (buf
[offset
] != 0x0f || buf
[offset
+ 1] != 0x29
2189 || (buf
[offset
+ 2] & 0x3f) != (xmmreg
<< 3 | 0x5))
2193 if ((buf
[offset
+ 2] & 0xc0) == 0x40)
2195 /* 8-bit displacement. */
2199 else if ((buf
[offset
+ 2] & 0xc0) == 0x80)
2201 /* 32-bit displacement. */
2209 if (offset
- 4 != buf
[3])
2212 return next_sal
.end
;
2215 /* Return PC of first real instruction. */
2218 amd64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2220 struct amd64_frame_cache cache
;
2222 CORE_ADDR func_addr
;
2224 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
2226 CORE_ADDR post_prologue_pc
2227 = skip_prologue_using_sal (gdbarch
, func_addr
);
2228 struct symtab
*s
= find_pc_symtab (func_addr
);
2230 /* Clang always emits a line note before the prologue and another
2231 one after. We trust clang to emit usable line notes. */
2232 if (post_prologue_pc
2234 && s
->producer
!= NULL
2235 && strncmp (s
->producer
, "clang ", sizeof ("clang ") - 1) == 0))
2236 return max (start_pc
, post_prologue_pc
);
2239 amd64_init_frame_cache (&cache
);
2240 pc
= amd64_analyze_prologue (gdbarch
, start_pc
, 0xffffffffffffffffLL
,
2242 if (cache
.frameless_p
)
2245 return amd64_skip_xmm_prologue (pc
, start_pc
);
2249 /* Normal frames. */
2252 amd64_frame_cache_1 (struct frame_info
*this_frame
,
2253 struct amd64_frame_cache
*cache
)
2255 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2256 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2260 cache
->pc
= get_frame_func (this_frame
);
2262 amd64_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2265 if (cache
->frameless_p
)
2267 /* We didn't find a valid frame. If we're at the start of a
2268 function, or somewhere half-way its prologue, the function's
2269 frame probably hasn't been fully setup yet. Try to
2270 reconstruct the base address for the stack frame by looking
2271 at the stack pointer. For truly "frameless" functions this
2274 if (cache
->saved_sp_reg
!= -1)
2276 /* Stack pointer has been saved. */
2277 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2278 cache
->saved_sp
= extract_unsigned_integer (buf
, 8, byte_order
);
2280 /* We're halfway aligning the stack. */
2281 cache
->base
= ((cache
->saved_sp
- 8) & 0xfffffffffffffff0LL
) - 8;
2282 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->saved_sp
- 8;
2284 /* This will be added back below. */
2285 cache
->saved_regs
[AMD64_RIP_REGNUM
] -= cache
->base
;
2289 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2290 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
)
2296 get_frame_register (this_frame
, AMD64_RBP_REGNUM
, buf
);
2297 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
);
2300 /* Now that we have the base address for the stack frame we can
2301 calculate the value of %rsp in the calling frame. */
2302 cache
->saved_sp
= cache
->base
+ 16;
2304 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2305 frame we find it at the same offset from the reconstructed base
2306 address. If we're halfway aligning the stack, %rip is handled
2307 differently (see above). */
2308 if (!cache
->frameless_p
|| cache
->saved_sp_reg
== -1)
2309 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
2311 /* Adjust all the saved registers such that they contain addresses
2312 instead of offsets. */
2313 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
2314 if (cache
->saved_regs
[i
] != -1)
2315 cache
->saved_regs
[i
] += cache
->base
;
2320 static struct amd64_frame_cache
*
2321 amd64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2323 volatile struct gdb_exception ex
;
2324 struct amd64_frame_cache
*cache
;
2329 cache
= amd64_alloc_frame_cache ();
2330 *this_cache
= cache
;
2332 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2334 amd64_frame_cache_1 (this_frame
, cache
);
2336 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2337 throw_exception (ex
);
2342 static enum unwind_stop_reason
2343 amd64_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2346 struct amd64_frame_cache
*cache
=
2347 amd64_frame_cache (this_frame
, this_cache
);
2350 return UNWIND_UNAVAILABLE
;
2352 /* This marks the outermost frame. */
2353 if (cache
->base
== 0)
2354 return UNWIND_OUTERMOST
;
2356 return UNWIND_NO_REASON
;
2360 amd64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2361 struct frame_id
*this_id
)
2363 struct amd64_frame_cache
*cache
=
2364 amd64_frame_cache (this_frame
, this_cache
);
2369 /* This marks the outermost frame. */
2370 if (cache
->base
== 0)
2373 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
2376 static struct value
*
2377 amd64_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2380 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2381 struct amd64_frame_cache
*cache
=
2382 amd64_frame_cache (this_frame
, this_cache
);
2384 gdb_assert (regnum
>= 0);
2386 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2387 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2389 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2390 return frame_unwind_got_memory (this_frame
, regnum
,
2391 cache
->saved_regs
[regnum
]);
2393 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2396 static const struct frame_unwind amd64_frame_unwind
=
2399 amd64_frame_unwind_stop_reason
,
2400 amd64_frame_this_id
,
2401 amd64_frame_prev_register
,
2403 default_frame_sniffer
2406 /* Generate a bytecode expression to get the value of the saved PC. */
2409 amd64_gen_return_address (struct gdbarch
*gdbarch
,
2410 struct agent_expr
*ax
, struct axs_value
*value
,
2413 /* The following sequence assumes the traditional use of the base
2415 ax_reg (ax
, AMD64_RBP_REGNUM
);
2417 ax_simple (ax
, aop_add
);
2418 value
->type
= register_type (gdbarch
, AMD64_RIP_REGNUM
);
2419 value
->kind
= axs_lvalue_memory
;
2423 /* Signal trampolines. */
2425 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2426 64-bit variants. This would require using identical frame caches
2427 on both platforms. */
2429 static struct amd64_frame_cache
*
2430 amd64_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2432 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2433 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2434 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2435 volatile struct gdb_exception ex
;
2436 struct amd64_frame_cache
*cache
;
2444 cache
= amd64_alloc_frame_cache ();
2446 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2448 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2449 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
) - 8;
2451 addr
= tdep
->sigcontext_addr (this_frame
);
2452 gdb_assert (tdep
->sc_reg_offset
);
2453 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
2454 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2455 if (tdep
->sc_reg_offset
[i
] != -1)
2456 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2460 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2461 throw_exception (ex
);
2463 *this_cache
= cache
;
2467 static enum unwind_stop_reason
2468 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2471 struct amd64_frame_cache
*cache
=
2472 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2475 return UNWIND_UNAVAILABLE
;
2477 return UNWIND_NO_REASON
;
2481 amd64_sigtramp_frame_this_id (struct frame_info
*this_frame
,
2482 void **this_cache
, struct frame_id
*this_id
)
2484 struct amd64_frame_cache
*cache
=
2485 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2490 (*this_id
) = frame_id_build (cache
->base
+ 16, get_frame_pc (this_frame
));
2493 static struct value
*
2494 amd64_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2495 void **this_cache
, int regnum
)
2497 /* Make sure we've initialized the cache. */
2498 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2500 return amd64_frame_prev_register (this_frame
, this_cache
, regnum
);
2504 amd64_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2505 struct frame_info
*this_frame
,
2508 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2510 /* We shouldn't even bother if we don't have a sigcontext_addr
2512 if (tdep
->sigcontext_addr
== NULL
)
2515 if (tdep
->sigtramp_p
!= NULL
)
2517 if (tdep
->sigtramp_p (this_frame
))
2521 if (tdep
->sigtramp_start
!= 0)
2523 CORE_ADDR pc
= get_frame_pc (this_frame
);
2525 gdb_assert (tdep
->sigtramp_end
!= 0);
2526 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2533 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
2536 amd64_sigtramp_frame_unwind_stop_reason
,
2537 amd64_sigtramp_frame_this_id
,
2538 amd64_sigtramp_frame_prev_register
,
2540 amd64_sigtramp_frame_sniffer
2545 amd64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2547 struct amd64_frame_cache
*cache
=
2548 amd64_frame_cache (this_frame
, this_cache
);
2553 static const struct frame_base amd64_frame_base
=
2555 &amd64_frame_unwind
,
2556 amd64_frame_base_address
,
2557 amd64_frame_base_address
,
2558 amd64_frame_base_address
2561 /* Normal frames, but in a function epilogue. */
2563 /* The epilogue is defined here as the 'ret' instruction, which will
2564 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2565 the function's stack frame. */
2568 amd64_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2571 struct symtab
*symtab
;
2573 symtab
= find_pc_symtab (pc
);
2574 if (symtab
&& symtab
->epilogue_unwind_valid
)
2577 if (target_read_memory (pc
, &insn
, 1))
2578 return 0; /* Can't read memory at pc. */
2580 if (insn
!= 0xc3) /* 'ret' instruction. */
2587 amd64_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2588 struct frame_info
*this_frame
,
2589 void **this_prologue_cache
)
2591 if (frame_relative_level (this_frame
) == 0)
2592 return amd64_in_function_epilogue_p (get_frame_arch (this_frame
),
2593 get_frame_pc (this_frame
));
2598 static struct amd64_frame_cache
*
2599 amd64_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2601 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2602 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2603 volatile struct gdb_exception ex
;
2604 struct amd64_frame_cache
*cache
;
2610 cache
= amd64_alloc_frame_cache ();
2611 *this_cache
= cache
;
2613 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
2615 /* Cache base will be %esp plus cache->sp_offset (-8). */
2616 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2617 cache
->base
= extract_unsigned_integer (buf
, 8,
2618 byte_order
) + cache
->sp_offset
;
2620 /* Cache pc will be the frame func. */
2621 cache
->pc
= get_frame_pc (this_frame
);
2623 /* The saved %esp will be at cache->base plus 16. */
2624 cache
->saved_sp
= cache
->base
+ 16;
2626 /* The saved %eip will be at cache->base plus 8. */
2627 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->base
+ 8;
2631 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
2632 throw_exception (ex
);
2637 static enum unwind_stop_reason
2638 amd64_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2641 struct amd64_frame_cache
*cache
2642 = amd64_epilogue_frame_cache (this_frame
, this_cache
);
2645 return UNWIND_UNAVAILABLE
;
2647 return UNWIND_NO_REASON
;
2651 amd64_epilogue_frame_this_id (struct frame_info
*this_frame
,
2653 struct frame_id
*this_id
)
2655 struct amd64_frame_cache
*cache
= amd64_epilogue_frame_cache (this_frame
,
2661 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2664 static const struct frame_unwind amd64_epilogue_frame_unwind
=
2667 amd64_epilogue_frame_unwind_stop_reason
,
2668 amd64_epilogue_frame_this_id
,
2669 amd64_frame_prev_register
,
2671 amd64_epilogue_frame_sniffer
2674 static struct frame_id
2675 amd64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2679 fp
= get_frame_register_unsigned (this_frame
, AMD64_RBP_REGNUM
);
2681 return frame_id_build (fp
+ 16, get_frame_pc (this_frame
));
2684 /* 16 byte align the SP per frame requirements. */
2687 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2689 return sp
& -(CORE_ADDR
)16;
2693 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2694 in the floating-point register set REGSET to register cache
2695 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2698 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2699 int regnum
, const void *fpregs
, size_t len
)
2701 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2703 gdb_assert (len
== tdep
->sizeof_fpregset
);
2704 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
2707 /* Collect register REGNUM from the register cache REGCACHE and store
2708 it in the buffer specified by FPREGS and LEN as described by the
2709 floating-point register set REGSET. If REGNUM is -1, do this for
2710 all registers in REGSET. */
2713 amd64_collect_fpregset (const struct regset
*regset
,
2714 const struct regcache
*regcache
,
2715 int regnum
, void *fpregs
, size_t len
)
2717 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (regset
->arch
);
2719 gdb_assert (len
== tdep
->sizeof_fpregset
);
2720 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
2723 /* Similar to amd64_supply_fpregset, but use XSAVE extended state. */
2726 amd64_supply_xstateregset (const struct regset
*regset
,
2727 struct regcache
*regcache
, int regnum
,
2728 const void *xstateregs
, size_t len
)
2730 amd64_supply_xsave (regcache
, regnum
, xstateregs
);
2733 /* Similar to amd64_collect_fpregset, but use XSAVE extended state. */
2736 amd64_collect_xstateregset (const struct regset
*regset
,
2737 const struct regcache
*regcache
,
2738 int regnum
, void *xstateregs
, size_t len
)
2740 amd64_collect_xsave (regcache
, regnum
, xstateregs
, 1);
2743 /* Return the appropriate register set for the core section identified
2744 by SECT_NAME and SECT_SIZE. */
2746 static const struct regset
*
2747 amd64_regset_from_core_section (struct gdbarch
*gdbarch
,
2748 const char *sect_name
, size_t sect_size
)
2750 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2752 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
2754 if (tdep
->fpregset
== NULL
)
2755 tdep
->fpregset
= regset_alloc (gdbarch
, amd64_supply_fpregset
,
2756 amd64_collect_fpregset
);
2758 return tdep
->fpregset
;
2761 if (strcmp (sect_name
, ".reg-xstate") == 0)
2763 if (tdep
->xstateregset
== NULL
)
2764 tdep
->xstateregset
= regset_alloc (gdbarch
,
2765 amd64_supply_xstateregset
,
2766 amd64_collect_xstateregset
);
2768 return tdep
->xstateregset
;
2771 return i386_regset_from_core_section (gdbarch
, sect_name
, sect_size
);
2775 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2776 %rdi. We expect its value to be a pointer to the jmp_buf structure
2777 from which we extract the address that we will land at. This
2778 address is copied into PC. This routine returns non-zero on
2782 amd64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2786 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2787 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2788 int len
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_func_ptr
);
2790 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2791 longjmp will land. */
2792 if (jb_pc_offset
== -1)
2795 get_frame_register (frame
, AMD64_RDI_REGNUM
, buf
);
2796 jb_addr
= extract_typed_address
2797 (buf
, builtin_type (gdbarch
)->builtin_data_ptr
);
2798 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, len
))
2801 *pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
2806 static const int amd64_record_regmap
[] =
2808 AMD64_RAX_REGNUM
, AMD64_RCX_REGNUM
, AMD64_RDX_REGNUM
, AMD64_RBX_REGNUM
,
2809 AMD64_RSP_REGNUM
, AMD64_RBP_REGNUM
, AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
2810 AMD64_R8_REGNUM
, AMD64_R9_REGNUM
, AMD64_R10_REGNUM
, AMD64_R11_REGNUM
,
2811 AMD64_R12_REGNUM
, AMD64_R13_REGNUM
, AMD64_R14_REGNUM
, AMD64_R15_REGNUM
,
2812 AMD64_RIP_REGNUM
, AMD64_EFLAGS_REGNUM
, AMD64_CS_REGNUM
, AMD64_SS_REGNUM
,
2813 AMD64_DS_REGNUM
, AMD64_ES_REGNUM
, AMD64_FS_REGNUM
, AMD64_GS_REGNUM
2817 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2819 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2820 const struct target_desc
*tdesc
= info
.target_desc
;
2822 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
2823 floating-point registers. */
2824 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
2826 if (! tdesc_has_registers (tdesc
))
2827 tdesc
= tdesc_amd64
;
2828 tdep
->tdesc
= tdesc
;
2830 tdep
->num_core_regs
= AMD64_NUM_GREGS
+ I387_NUM_REGS
;
2831 tdep
->register_names
= amd64_register_names
;
2833 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx") != NULL
)
2835 tdep
->ymmh_register_names
= amd64_ymmh_names
;
2836 tdep
->num_ymm_regs
= 16;
2837 tdep
->ymm0h_regnum
= AMD64_YMM0H_REGNUM
;
2840 tdep
->num_byte_regs
= 20;
2841 tdep
->num_word_regs
= 16;
2842 tdep
->num_dword_regs
= 16;
2843 /* Avoid wiring in the MMX registers for now. */
2844 tdep
->num_mmx_regs
= 0;
2846 set_gdbarch_pseudo_register_read_value (gdbarch
,
2847 amd64_pseudo_register_read_value
);
2848 set_gdbarch_pseudo_register_write (gdbarch
,
2849 amd64_pseudo_register_write
);
2851 set_tdesc_pseudo_register_name (gdbarch
, amd64_pseudo_register_name
);
2853 /* AMD64 has an FPU and 16 SSE registers. */
2854 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
2855 tdep
->num_xmm_regs
= 16;
2857 /* This is what all the fuss is about. */
2858 set_gdbarch_long_bit (gdbarch
, 64);
2859 set_gdbarch_long_long_bit (gdbarch
, 64);
2860 set_gdbarch_ptr_bit (gdbarch
, 64);
2862 /* In contrast to the i386, on AMD64 a `long double' actually takes
2863 up 128 bits, even though it's still based on the i387 extended
2864 floating-point format which has only 80 significant bits. */
2865 set_gdbarch_long_double_bit (gdbarch
, 128);
2867 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
2869 /* Register numbers of various important registers. */
2870 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
2871 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
2872 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
2873 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
2875 /* The "default" register numbering scheme for AMD64 is referred to
2876 as the "DWARF Register Number Mapping" in the System V psABI.
2877 The preferred debugging format for all known AMD64 targets is
2878 actually DWARF2, and GCC doesn't seem to support DWARF (that is
2879 DWARF-1), but we provide the same mapping just in case. This
2880 mapping is also used for stabs, which GCC does support. */
2881 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
2882 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
2884 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
2885 be in use on any of the supported AMD64 targets. */
2887 /* Call dummy code. */
2888 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
2889 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
2890 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
2891 tdep
->call_dummy_num_integer_regs
=
2892 ARRAY_SIZE (amd64_dummy_call_integer_regs
);
2893 tdep
->call_dummy_integer_regs
= amd64_dummy_call_integer_regs
;
2894 tdep
->classify
= amd64_classify
;
2896 set_gdbarch_convert_register_p (gdbarch
, i387_convert_register_p
);
2897 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
2898 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
2900 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
2902 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
2904 tdep
->record_regmap
= amd64_record_regmap
;
2906 set_gdbarch_dummy_id (gdbarch
, amd64_dummy_id
);
2908 /* Hook the function epilogue frame unwinder. This unwinder is
2909 appended to the list first, so that it supercedes the other
2910 unwinders in function epilogues. */
2911 frame_unwind_prepend_unwinder (gdbarch
, &amd64_epilogue_frame_unwind
);
2913 /* Hook the prologue-based frame unwinders. */
2914 frame_unwind_append_unwinder (gdbarch
, &amd64_sigtramp_frame_unwind
);
2915 frame_unwind_append_unwinder (gdbarch
, &amd64_frame_unwind
);
2916 frame_base_set_default (gdbarch
, &amd64_frame_base
);
2918 /* If we have a register mapping, enable the generic core file support. */
2919 if (tdep
->gregset_reg_offset
)
2920 set_gdbarch_regset_from_core_section (gdbarch
,
2921 amd64_regset_from_core_section
);
2923 set_gdbarch_get_longjmp_target (gdbarch
, amd64_get_longjmp_target
);
2925 set_gdbarch_relocate_instruction (gdbarch
, amd64_relocate_instruction
);
2927 set_gdbarch_gen_return_address (gdbarch
, amd64_gen_return_address
);
2929 /* SystemTap variables and functions. */
2930 set_gdbarch_stap_integer_prefix (gdbarch
, "$");
2931 set_gdbarch_stap_register_prefix (gdbarch
, "%");
2932 set_gdbarch_stap_register_indirection_prefix (gdbarch
, "(");
2933 set_gdbarch_stap_register_indirection_suffix (gdbarch
, ")");
2934 set_gdbarch_stap_is_single_operand (gdbarch
,
2935 i386_stap_is_single_operand
);
2936 set_gdbarch_stap_parse_special_token (gdbarch
,
2937 i386_stap_parse_special_token
);
2941 static struct type
*
2942 amd64_x32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2944 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2946 switch (regnum
- tdep
->eax_regnum
)
2948 case AMD64_RBP_REGNUM
: /* %ebp */
2949 case AMD64_RSP_REGNUM
: /* %esp */
2950 return builtin_type (gdbarch
)->builtin_data_ptr
;
2951 case AMD64_RIP_REGNUM
: /* %eip */
2952 return builtin_type (gdbarch
)->builtin_func_ptr
;
2955 return i386_pseudo_register_type (gdbarch
, regnum
);
2959 amd64_x32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2961 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2962 const struct target_desc
*tdesc
= info
.target_desc
;
2964 amd64_init_abi (info
, gdbarch
);
2966 if (! tdesc_has_registers (tdesc
))
2968 tdep
->tdesc
= tdesc
;
2970 tdep
->num_dword_regs
= 17;
2971 set_tdesc_pseudo_register_type (gdbarch
, amd64_x32_pseudo_register_type
);
2973 set_gdbarch_long_bit (gdbarch
, 32);
2974 set_gdbarch_ptr_bit (gdbarch
, 32);
2977 /* Provide a prototype to silence -Wmissing-prototypes. */
2978 void _initialize_amd64_tdep (void);
2981 _initialize_amd64_tdep (void)
2983 initialize_tdesc_amd64 ();
2984 initialize_tdesc_amd64_avx ();
2985 initialize_tdesc_x32 ();
2986 initialize_tdesc_x32_avx ();
2990 /* The 64-bit FXSAVE format differs from the 32-bit format in the
2991 sense that the instruction pointer and data pointer are simply
2992 64-bit offsets into the code segment and the data segment instead
2993 of a selector offset pair. The functions below store the upper 32
2994 bits of these pointers (instead of just the 16-bits of the segment
2997 /* Fill register REGNUM in REGCACHE with the appropriate
2998 floating-point or SSE register value from *FXSAVE. If REGNUM is
2999 -1, do this for all registers. This function masks off any of the
3000 reserved bits in *FXSAVE. */
3003 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
3006 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3007 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3009 i387_supply_fxsave (regcache
, regnum
, fxsave
);
3012 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3014 const gdb_byte
*regs
= fxsave
;
3016 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3017 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
3018 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3019 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3023 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3026 amd64_supply_xsave (struct regcache
*regcache
, int regnum
,
3029 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3030 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3032 i387_supply_xsave (regcache
, regnum
, xsave
);
3035 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3037 const gdb_byte
*regs
= xsave
;
3039 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3040 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
),
3042 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3043 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
),
3048 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3049 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3050 all registers. This function doesn't touch any of the reserved
3054 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
3057 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3058 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3059 gdb_byte
*regs
= fxsave
;
3061 i387_collect_fxsave (regcache
, regnum
, fxsave
);
3063 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3065 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3066 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
3067 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3068 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3072 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3075 amd64_collect_xsave (const struct regcache
*regcache
, int regnum
,
3076 void *xsave
, int gcore
)
3078 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3079 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3080 gdb_byte
*regs
= xsave
;
3082 i387_collect_xsave (regcache
, regnum
, xsave
, gcore
);
3084 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3086 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3087 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
),
3089 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3090 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
),