1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2020 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
42 #include "gdbsupport/x86-xstate.h"
44 #include "target-descriptions.h"
45 #include "arch/amd64.h"
49 #include "gdbsupport/byte-vector.h"
53 /* Note that the AMD64 architecture was previously known as x86-64.
54 The latter is (forever) engraved into the canonical system name as
55 returned by config.guess, and used as the name for the AMD64 port
56 of GNU/Linux. The BSD's have renamed their ports to amd64; they
57 don't like to shout. For GDB we prefer the amd64_-prefix over the
58 x86_64_-prefix since it's so much easier to type. */
60 /* Register information. */
62 static const char *amd64_register_names
[] =
64 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
66 /* %r8 is indeed register number 8. */
67 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
68 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
70 /* %st0 is register number 24. */
71 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
72 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
74 /* %xmm0 is register number 40. */
75 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
76 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
80 static const char *amd64_ymm_names
[] =
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
84 "ymm8", "ymm9", "ymm10", "ymm11",
85 "ymm12", "ymm13", "ymm14", "ymm15"
88 static const char *amd64_ymm_avx512_names
[] =
90 "ymm16", "ymm17", "ymm18", "ymm19",
91 "ymm20", "ymm21", "ymm22", "ymm23",
92 "ymm24", "ymm25", "ymm26", "ymm27",
93 "ymm28", "ymm29", "ymm30", "ymm31"
96 static const char *amd64_ymmh_names
[] =
98 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
99 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
100 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
101 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
104 static const char *amd64_ymmh_avx512_names
[] =
106 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
107 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
108 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
109 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
112 static const char *amd64_mpx_names
[] =
114 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
117 static const char *amd64_k_names
[] =
119 "k0", "k1", "k2", "k3",
120 "k4", "k5", "k6", "k7"
123 static const char *amd64_zmmh_names
[] =
125 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
126 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
127 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
128 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
129 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
130 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
131 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
132 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
135 static const char *amd64_zmm_names
[] =
137 "zmm0", "zmm1", "zmm2", "zmm3",
138 "zmm4", "zmm5", "zmm6", "zmm7",
139 "zmm8", "zmm9", "zmm10", "zmm11",
140 "zmm12", "zmm13", "zmm14", "zmm15",
141 "zmm16", "zmm17", "zmm18", "zmm19",
142 "zmm20", "zmm21", "zmm22", "zmm23",
143 "zmm24", "zmm25", "zmm26", "zmm27",
144 "zmm28", "zmm29", "zmm30", "zmm31"
147 static const char *amd64_xmm_avx512_names
[] = {
148 "xmm16", "xmm17", "xmm18", "xmm19",
149 "xmm20", "xmm21", "xmm22", "xmm23",
150 "xmm24", "xmm25", "xmm26", "xmm27",
151 "xmm28", "xmm29", "xmm30", "xmm31"
154 static const char *amd64_pkeys_names
[] = {
158 /* DWARF Register Number Mapping as defined in the System V psABI,
161 static int amd64_dwarf_regmap
[] =
163 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
164 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
165 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
166 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
168 /* Frame Pointer Register RBP. */
171 /* Stack Pointer Register RSP. */
174 /* Extended Integer Registers 8 - 15. */
175 AMD64_R8_REGNUM
, /* %r8 */
176 AMD64_R9_REGNUM
, /* %r9 */
177 AMD64_R10_REGNUM
, /* %r10 */
178 AMD64_R11_REGNUM
, /* %r11 */
179 AMD64_R12_REGNUM
, /* %r12 */
180 AMD64_R13_REGNUM
, /* %r13 */
181 AMD64_R14_REGNUM
, /* %r14 */
182 AMD64_R15_REGNUM
, /* %r15 */
184 /* Return Address RA. Mapped to RIP. */
187 /* SSE Registers 0 - 7. */
188 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
189 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
190 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
191 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
193 /* Extended SSE Registers 8 - 15. */
194 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
195 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
196 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
197 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
199 /* Floating Point Registers 0-7. */
200 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
201 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
202 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
203 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
205 /* MMX Registers 0 - 7.
206 We have to handle those registers specifically, as their register
207 number within GDB depends on the target (or they may even not be
208 available at all). */
209 -1, -1, -1, -1, -1, -1, -1, -1,
211 /* Control and Status Flags Register. */
214 /* Selector Registers. */
224 /* Segment Base Address Registers. */
230 /* Special Selector Registers. */
234 /* Floating Point Control Registers. */
240 static const int amd64_dwarf_regmap_len
=
241 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
243 /* Convert DWARF register number REG to the appropriate register
244 number used by GDB. */
247 amd64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
249 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
250 int ymm0_regnum
= tdep
->ymm0_regnum
;
253 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
254 regnum
= amd64_dwarf_regmap
[reg
];
257 && i386_xmm_regnum_p (gdbarch
, regnum
))
258 regnum
+= ymm0_regnum
- I387_XMM0_REGNUM (tdep
);
263 /* Map architectural register numbers to gdb register numbers. */
265 static const int amd64_arch_regmap
[16] =
267 AMD64_RAX_REGNUM
, /* %rax */
268 AMD64_RCX_REGNUM
, /* %rcx */
269 AMD64_RDX_REGNUM
, /* %rdx */
270 AMD64_RBX_REGNUM
, /* %rbx */
271 AMD64_RSP_REGNUM
, /* %rsp */
272 AMD64_RBP_REGNUM
, /* %rbp */
273 AMD64_RSI_REGNUM
, /* %rsi */
274 AMD64_RDI_REGNUM
, /* %rdi */
275 AMD64_R8_REGNUM
, /* %r8 */
276 AMD64_R9_REGNUM
, /* %r9 */
277 AMD64_R10_REGNUM
, /* %r10 */
278 AMD64_R11_REGNUM
, /* %r11 */
279 AMD64_R12_REGNUM
, /* %r12 */
280 AMD64_R13_REGNUM
, /* %r13 */
281 AMD64_R14_REGNUM
, /* %r14 */
282 AMD64_R15_REGNUM
/* %r15 */
285 static const int amd64_arch_regmap_len
=
286 (sizeof (amd64_arch_regmap
) / sizeof (amd64_arch_regmap
[0]));
288 /* Convert architectural register number REG to the appropriate register
289 number used by GDB. */
292 amd64_arch_reg_to_regnum (int reg
)
294 gdb_assert (reg
>= 0 && reg
< amd64_arch_regmap_len
);
296 return amd64_arch_regmap
[reg
];
299 /* Register names for byte pseudo-registers. */
301 static const char *amd64_byte_names
[] =
303 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
304 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
305 "ah", "bh", "ch", "dh"
308 /* Number of lower byte registers. */
309 #define AMD64_NUM_LOWER_BYTE_REGS 16
311 /* Register names for word pseudo-registers. */
313 static const char *amd64_word_names
[] =
315 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
316 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
319 /* Register names for dword pseudo-registers. */
321 static const char *amd64_dword_names
[] =
323 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
324 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
328 /* Return the name of register REGNUM. */
331 amd64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
333 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
334 if (i386_byte_regnum_p (gdbarch
, regnum
))
335 return amd64_byte_names
[regnum
- tdep
->al_regnum
];
336 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
337 return amd64_zmm_names
[regnum
- tdep
->zmm0_regnum
];
338 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
339 return amd64_ymm_names
[regnum
- tdep
->ymm0_regnum
];
340 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
341 return amd64_ymm_avx512_names
[regnum
- tdep
->ymm16_regnum
];
342 else if (i386_word_regnum_p (gdbarch
, regnum
))
343 return amd64_word_names
[regnum
- tdep
->ax_regnum
];
344 else if (i386_dword_regnum_p (gdbarch
, regnum
))
345 return amd64_dword_names
[regnum
- tdep
->eax_regnum
];
347 return i386_pseudo_register_name (gdbarch
, regnum
);
350 static struct value
*
351 amd64_pseudo_register_read_value (struct gdbarch
*gdbarch
,
352 readable_regcache
*regcache
,
355 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
357 value
*result_value
= allocate_value (register_type (gdbarch
, regnum
));
358 VALUE_LVAL (result_value
) = lval_register
;
359 VALUE_REGNUM (result_value
) = regnum
;
360 gdb_byte
*buf
= value_contents_raw (result_value
);
362 if (i386_byte_regnum_p (gdbarch
, regnum
))
364 int gpnum
= regnum
- tdep
->al_regnum
;
366 /* Extract (always little endian). */
367 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
369 gpnum
-= AMD64_NUM_LOWER_BYTE_REGS
;
370 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
372 /* Special handling for AH, BH, CH, DH. */
373 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
374 if (status
== REG_VALID
)
375 memcpy (buf
, raw_buf
+ 1, 1);
377 mark_value_bytes_unavailable (result_value
, 0,
378 TYPE_LENGTH (value_type (result_value
)));
382 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
383 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
384 if (status
== REG_VALID
)
385 memcpy (buf
, raw_buf
, 1);
387 mark_value_bytes_unavailable (result_value
, 0,
388 TYPE_LENGTH (value_type (result_value
)));
391 else if (i386_dword_regnum_p (gdbarch
, regnum
))
393 int gpnum
= regnum
- tdep
->eax_regnum
;
394 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
395 /* Extract (always little endian). */
396 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
397 if (status
== REG_VALID
)
398 memcpy (buf
, raw_buf
, 4);
400 mark_value_bytes_unavailable (result_value
, 0,
401 TYPE_LENGTH (value_type (result_value
)));
404 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
,
411 amd64_pseudo_register_write (struct gdbarch
*gdbarch
,
412 struct regcache
*regcache
,
413 int regnum
, const gdb_byte
*buf
)
415 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
417 if (i386_byte_regnum_p (gdbarch
, regnum
))
419 int gpnum
= regnum
- tdep
->al_regnum
;
421 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
423 gpnum
-= AMD64_NUM_LOWER_BYTE_REGS
;
424 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
426 /* Read ... AH, BH, CH, DH. */
427 regcache
->raw_read (gpnum
, raw_buf
);
428 /* ... Modify ... (always little endian). */
429 memcpy (raw_buf
+ 1, buf
, 1);
431 regcache
->raw_write (gpnum
, raw_buf
);
435 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
438 regcache
->raw_read (gpnum
, raw_buf
);
439 /* ... Modify ... (always little endian). */
440 memcpy (raw_buf
, buf
, 1);
442 regcache
->raw_write (gpnum
, raw_buf
);
445 else if (i386_dword_regnum_p (gdbarch
, regnum
))
447 int gpnum
= regnum
- tdep
->eax_regnum
;
448 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
451 regcache
->raw_read (gpnum
, raw_buf
);
452 /* ... Modify ... (always little endian). */
453 memcpy (raw_buf
, buf
, 4);
455 regcache
->raw_write (gpnum
, raw_buf
);
458 i386_pseudo_register_write (gdbarch
, regcache
, regnum
, buf
);
461 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
464 amd64_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
465 struct agent_expr
*ax
, int regnum
)
467 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
469 if (i386_byte_regnum_p (gdbarch
, regnum
))
471 int gpnum
= regnum
- tdep
->al_regnum
;
473 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
474 ax_reg_mask (ax
, gpnum
- AMD64_NUM_LOWER_BYTE_REGS
);
476 ax_reg_mask (ax
, gpnum
);
479 else if (i386_dword_regnum_p (gdbarch
, regnum
))
481 int gpnum
= regnum
- tdep
->eax_regnum
;
483 ax_reg_mask (ax
, gpnum
);
487 return i386_ax_pseudo_register_collect (gdbarch
, ax
, regnum
);
492 /* Register classes as defined in the psABI. */
506 /* Return the union class of CLASS1 and CLASS2. See the psABI for
509 static enum amd64_reg_class
510 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
512 /* Rule (a): If both classes are equal, this is the resulting class. */
513 if (class1
== class2
)
516 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
517 is the other class. */
518 if (class1
== AMD64_NO_CLASS
)
520 if (class2
== AMD64_NO_CLASS
)
523 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
524 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
527 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
528 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
529 return AMD64_INTEGER
;
531 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
532 MEMORY is used as class. */
533 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
534 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
535 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
538 /* Rule (f): Otherwise class SSE is used. */
542 static void amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2]);
544 /* Return true if TYPE is a structure or union with unaligned fields. */
547 amd64_has_unaligned_fields (struct type
*type
)
549 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
550 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
552 for (int i
= 0; i
< TYPE_NFIELDS (type
); i
++)
554 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
555 int bitpos
= TYPE_FIELD_BITPOS (type
, i
);
556 int align
= type_align(subtype
);
558 /* Ignore static fields, empty fields (for example nested
559 empty structures), and bitfields (these are handled by
561 if (field_is_static (&TYPE_FIELD (type
, i
))
562 || (TYPE_FIELD_BITSIZE (type
, i
) == 0
563 && TYPE_LENGTH (subtype
) == 0)
564 || TYPE_FIELD_PACKED (type
, i
))
570 int bytepos
= bitpos
/ 8;
571 if (bytepos
% align
!= 0)
574 if (amd64_has_unaligned_fields (subtype
))
582 /* Classify field I of TYPE starting at BITOFFSET according to the rules for
583 structures and union types, and store the result in THECLASS. */
586 amd64_classify_aggregate_field (struct type
*type
, int i
,
587 enum amd64_reg_class theclass
[2],
588 unsigned int bitoffset
)
590 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
591 int bitpos
= bitoffset
+ TYPE_FIELD_BITPOS (type
, i
);
592 int pos
= bitpos
/ 64;
593 enum amd64_reg_class subclass
[2];
594 int bitsize
= TYPE_FIELD_BITSIZE (type
, i
);
598 bitsize
= TYPE_LENGTH (subtype
) * 8;
599 endpos
= (bitpos
+ bitsize
- 1) / 64;
601 /* Ignore static fields, or empty fields, for example nested
603 if (field_is_static (&TYPE_FIELD (type
, i
)) || bitsize
== 0)
606 if (TYPE_CODE (subtype
) == TYPE_CODE_STRUCT
607 || TYPE_CODE (subtype
) == TYPE_CODE_UNION
)
609 /* Each field of an object is classified recursively. */
611 for (j
= 0; j
< TYPE_NFIELDS (subtype
); j
++)
612 amd64_classify_aggregate_field (subtype
, j
, theclass
, bitpos
);
616 gdb_assert (pos
== 0 || pos
== 1);
618 amd64_classify (subtype
, subclass
);
619 theclass
[pos
] = amd64_merge_classes (theclass
[pos
], subclass
[0]);
620 if (bitsize
<= 64 && pos
== 0 && endpos
== 1)
621 /* This is a bit of an odd case: We have a field that would
622 normally fit in one of the two eightbytes, except that
623 it is placed in a way that this field straddles them.
624 This has been seen with a structure containing an array.
626 The ABI is a bit unclear in this case, but we assume that
627 this field's class (stored in subclass[0]) must also be merged
628 into class[1]. In other words, our field has a piece stored
629 in the second eight-byte, and thus its class applies to
630 the second eight-byte as well.
632 In the case where the field length exceeds 8 bytes,
633 it should not be necessary to merge the field class
634 into class[1]. As LEN > 8, subclass[1] is necessarily
635 different from AMD64_NO_CLASS. If subclass[1] is equal
636 to subclass[0], then the normal class[1]/subclass[1]
637 merging will take care of everything. For subclass[1]
638 to be different from subclass[0], I can only see the case
639 where we have a SSE/SSEUP or X87/X87UP pair, which both
640 use up all 16 bytes of the aggregate, and are already
641 handled just fine (because each portion sits on its own
643 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[0]);
645 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[1]);
648 /* Classify TYPE according to the rules for aggregate (structures and
649 arrays) and union types, and store the result in CLASS. */
652 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class theclass
[2])
654 /* 1. If the size of an object is larger than two eightbytes, or it has
655 unaligned fields, it has class memory. */
656 if (TYPE_LENGTH (type
) > 16 || amd64_has_unaligned_fields (type
))
658 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
662 /* 2. Both eightbytes get initialized to class NO_CLASS. */
663 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
665 /* 3. Each field of an object is classified recursively so that
666 always two fields are considered. The resulting class is
667 calculated according to the classes of the fields in the
670 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
672 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
674 /* All fields in an array have the same type. */
675 amd64_classify (subtype
, theclass
);
676 if (TYPE_LENGTH (type
) > 8 && theclass
[1] == AMD64_NO_CLASS
)
677 theclass
[1] = theclass
[0];
683 /* Structure or union. */
684 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
685 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
687 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
688 amd64_classify_aggregate_field (type
, i
, theclass
, 0);
691 /* 4. Then a post merger cleanup is done: */
693 /* Rule (a): If one of the classes is MEMORY, the whole argument is
695 if (theclass
[0] == AMD64_MEMORY
|| theclass
[1] == AMD64_MEMORY
)
696 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
698 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
700 if (theclass
[0] == AMD64_SSEUP
)
701 theclass
[0] = AMD64_SSE
;
702 if (theclass
[1] == AMD64_SSEUP
&& theclass
[0] != AMD64_SSE
)
703 theclass
[1] = AMD64_SSE
;
706 /* Classify TYPE, and store the result in CLASS. */
709 amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2])
711 enum type_code code
= TYPE_CODE (type
);
712 int len
= TYPE_LENGTH (type
);
714 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
716 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
717 long, long long, and pointers are in the INTEGER class. Similarly,
718 range types, used by languages such as Ada, are also in the INTEGER
720 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
721 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
722 || code
== TYPE_CODE_CHAR
723 || code
== TYPE_CODE_PTR
|| TYPE_IS_REFERENCE (type
))
724 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
725 theclass
[0] = AMD64_INTEGER
;
727 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
729 else if ((code
== TYPE_CODE_FLT
|| code
== TYPE_CODE_DECFLOAT
)
730 && (len
== 4 || len
== 8))
732 theclass
[0] = AMD64_SSE
;
734 /* Arguments of types __float128, _Decimal128 and __m128 are split into
735 two halves. The least significant ones belong to class SSE, the most
736 significant one to class SSEUP. */
737 else if (code
== TYPE_CODE_DECFLOAT
&& len
== 16)
738 /* FIXME: __float128, __m128. */
739 theclass
[0] = AMD64_SSE
, theclass
[1] = AMD64_SSEUP
;
741 /* The 64-bit mantissa of arguments of type long double belongs to
742 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
744 else if (code
== TYPE_CODE_FLT
&& len
== 16)
745 /* Class X87 and X87UP. */
746 theclass
[0] = AMD64_X87
, theclass
[1] = AMD64_X87UP
;
748 /* Arguments of complex T where T is one of the types float or
749 double get treated as if they are implemented as:
757 else if (code
== TYPE_CODE_COMPLEX
&& len
== 8)
758 theclass
[0] = AMD64_SSE
;
759 else if (code
== TYPE_CODE_COMPLEX
&& len
== 16)
760 theclass
[0] = theclass
[1] = AMD64_SSE
;
762 /* A variable of type complex long double is classified as type
764 else if (code
== TYPE_CODE_COMPLEX
&& len
== 32)
765 theclass
[0] = AMD64_COMPLEX_X87
;
768 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
769 || code
== TYPE_CODE_UNION
)
770 amd64_classify_aggregate (type
, theclass
);
773 static enum return_value_convention
774 amd64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
775 struct type
*type
, struct regcache
*regcache
,
776 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
778 enum amd64_reg_class theclass
[2];
779 int len
= TYPE_LENGTH (type
);
780 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
781 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
786 gdb_assert (!(readbuf
&& writebuf
));
788 /* 1. Classify the return type with the classification algorithm. */
789 amd64_classify (type
, theclass
);
791 /* 2. If the type has class MEMORY, then the caller provides space
792 for the return value and passes the address of this storage in
793 %rdi as if it were the first argument to the function. In effect,
794 this address becomes a hidden first argument.
796 On return %rax will contain the address that has been passed in
797 by the caller in %rdi. */
798 if (theclass
[0] == AMD64_MEMORY
)
800 /* As indicated by the comment above, the ABI guarantees that we
801 can always find the return value just after the function has
808 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
809 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
812 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
815 /* 8. If the class is COMPLEX_X87, the real part of the value is
816 returned in %st0 and the imaginary part in %st1. */
817 if (theclass
[0] == AMD64_COMPLEX_X87
)
821 regcache
->raw_read (AMD64_ST0_REGNUM
, readbuf
);
822 regcache
->raw_read (AMD64_ST1_REGNUM
, readbuf
+ 16);
827 i387_return_value (gdbarch
, regcache
);
828 regcache
->raw_write (AMD64_ST0_REGNUM
, writebuf
);
829 regcache
->raw_write (AMD64_ST1_REGNUM
, writebuf
+ 16);
831 /* Fix up the tag word such that both %st(0) and %st(1) are
833 regcache_raw_write_unsigned (regcache
, AMD64_FTAG_REGNUM
, 0xfff);
836 return RETURN_VALUE_REGISTER_CONVENTION
;
839 gdb_assert (theclass
[1] != AMD64_MEMORY
);
840 gdb_assert (len
<= 16);
842 for (i
= 0; len
> 0; i
++, len
-= 8)
850 /* 3. If the class is INTEGER, the next available register
851 of the sequence %rax, %rdx is used. */
852 regnum
= integer_regnum
[integer_reg
++];
856 /* 4. If the class is SSE, the next available SSE register
857 of the sequence %xmm0, %xmm1 is used. */
858 regnum
= sse_regnum
[sse_reg
++];
862 /* 5. If the class is SSEUP, the eightbyte is passed in the
863 upper half of the last used SSE register. */
864 gdb_assert (sse_reg
> 0);
865 regnum
= sse_regnum
[sse_reg
- 1];
870 /* 6. If the class is X87, the value is returned on the X87
871 stack in %st0 as 80-bit x87 number. */
872 regnum
= AMD64_ST0_REGNUM
;
874 i387_return_value (gdbarch
, regcache
);
878 /* 7. If the class is X87UP, the value is returned together
879 with the previous X87 value in %st0. */
880 gdb_assert (i
> 0 && theclass
[0] == AMD64_X87
);
881 regnum
= AMD64_ST0_REGNUM
;
890 gdb_assert (!"Unexpected register class.");
893 gdb_assert (regnum
!= -1);
896 regcache
->raw_read_part (regnum
, offset
, std::min (len
, 8),
899 regcache
->raw_write_part (regnum
, offset
, std::min (len
, 8),
903 return RETURN_VALUE_REGISTER_CONVENTION
;
908 amd64_push_arguments (struct regcache
*regcache
, int nargs
, struct value
**args
,
909 CORE_ADDR sp
, function_call_return_method return_method
)
911 static int integer_regnum
[] =
913 AMD64_RDI_REGNUM
, /* %rdi */
914 AMD64_RSI_REGNUM
, /* %rsi */
915 AMD64_RDX_REGNUM
, /* %rdx */
916 AMD64_RCX_REGNUM
, /* %rcx */
917 AMD64_R8_REGNUM
, /* %r8 */
918 AMD64_R9_REGNUM
/* %r9 */
920 static int sse_regnum
[] =
922 /* %xmm0 ... %xmm7 */
923 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
924 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
925 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
926 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
928 struct value
**stack_args
= XALLOCAVEC (struct value
*, nargs
);
929 int num_stack_args
= 0;
930 int num_elements
= 0;
936 /* Reserve a register for the "hidden" argument. */
937 if (return_method
== return_method_struct
)
940 for (i
= 0; i
< nargs
; i
++)
942 struct type
*type
= value_type (args
[i
]);
943 int len
= TYPE_LENGTH (type
);
944 enum amd64_reg_class theclass
[2];
945 int needed_integer_regs
= 0;
946 int needed_sse_regs
= 0;
949 /* Classify argument. */
950 amd64_classify (type
, theclass
);
952 /* Calculate the number of integer and SSE registers needed for
954 for (j
= 0; j
< 2; j
++)
956 if (theclass
[j
] == AMD64_INTEGER
)
957 needed_integer_regs
++;
958 else if (theclass
[j
] == AMD64_SSE
)
962 /* Check whether enough registers are available, and if the
963 argument should be passed in registers at all. */
964 if (integer_reg
+ needed_integer_regs
> ARRAY_SIZE (integer_regnum
)
965 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
966 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
968 /* The argument will be passed on the stack. */
969 num_elements
+= ((len
+ 7) / 8);
970 stack_args
[num_stack_args
++] = args
[i
];
974 /* The argument will be passed in registers. */
975 const gdb_byte
*valbuf
= value_contents (args
[i
]);
978 gdb_assert (len
<= 16);
980 for (j
= 0; len
> 0; j
++, len
-= 8)
988 regnum
= integer_regnum
[integer_reg
++];
992 regnum
= sse_regnum
[sse_reg
++];
996 gdb_assert (sse_reg
> 0);
997 regnum
= sse_regnum
[sse_reg
- 1];
1001 case AMD64_NO_CLASS
:
1005 gdb_assert (!"Unexpected register class.");
1008 gdb_assert (regnum
!= -1);
1009 memset (buf
, 0, sizeof buf
);
1010 memcpy (buf
, valbuf
+ j
* 8, std::min (len
, 8));
1011 regcache
->raw_write_part (regnum
, offset
, 8, buf
);
1016 /* Allocate space for the arguments on the stack. */
1017 sp
-= num_elements
* 8;
1019 /* The psABI says that "The end of the input argument area shall be
1020 aligned on a 16 byte boundary." */
1023 /* Write out the arguments to the stack. */
1024 for (i
= 0; i
< num_stack_args
; i
++)
1026 struct type
*type
= value_type (stack_args
[i
]);
1027 const gdb_byte
*valbuf
= value_contents (stack_args
[i
]);
1028 int len
= TYPE_LENGTH (type
);
1030 write_memory (sp
+ element
* 8, valbuf
, len
);
1031 element
+= ((len
+ 7) / 8);
1034 /* The psABI says that "For calls that may call functions that use
1035 varargs or stdargs (prototype-less calls or calls to functions
1036 containing ellipsis (...) in the declaration) %al is used as
1037 hidden argument to specify the number of SSE registers used. */
1038 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
1043 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1044 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1045 int nargs
, struct value
**args
, CORE_ADDR sp
,
1046 function_call_return_method return_method
,
1047 CORE_ADDR struct_addr
)
1049 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1052 /* BND registers can be in arbitrary values at the moment of the
1053 inferior call. This can cause boundary violations that are not
1054 due to a real bug or even desired by the user. The best to be done
1055 is set the BND registers to allow access to the whole memory, INIT
1056 state, before pushing the inferior call. */
1057 i387_reset_bnd_regs (gdbarch
, regcache
);
1059 /* Pass arguments. */
1060 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, return_method
);
1062 /* Pass "hidden" argument". */
1063 if (return_method
== return_method_struct
)
1065 store_unsigned_integer (buf
, 8, byte_order
, struct_addr
);
1066 regcache
->cooked_write (AMD64_RDI_REGNUM
, buf
);
1069 /* Store return address. */
1071 store_unsigned_integer (buf
, 8, byte_order
, bp_addr
);
1072 write_memory (sp
, buf
, 8);
1074 /* Finally, update the stack pointer... */
1075 store_unsigned_integer (buf
, 8, byte_order
, sp
);
1076 regcache
->cooked_write (AMD64_RSP_REGNUM
, buf
);
1078 /* ...and fake a frame pointer. */
1079 regcache
->cooked_write (AMD64_RBP_REGNUM
, buf
);
1084 /* Displaced instruction handling. */
1086 /* A partially decoded instruction.
1087 This contains enough details for displaced stepping purposes. */
1091 /* The number of opcode bytes. */
1093 /* The offset of the REX/VEX instruction encoding prefix or -1 if
1095 int enc_prefix_offset
;
1096 /* The offset to the first opcode byte. */
1098 /* The offset to the modrm byte or -1 if not present. */
1101 /* The raw instruction. */
1105 struct amd64_displaced_step_closure
: public displaced_step_closure
1107 amd64_displaced_step_closure (int insn_buf_len
)
1108 : insn_buf (insn_buf_len
, 0)
1111 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1116 /* Details of the instruction. */
1117 struct amd64_insn insn_details
;
1119 /* The possibly modified insn. */
1120 gdb::byte_vector insn_buf
;
1123 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1124 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1125 at which point delete these in favor of libopcodes' versions). */
1127 static const unsigned char onebyte_has_modrm
[256] = {
1128 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1129 /* ------------------------------- */
1130 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1131 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1132 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1133 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1134 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1135 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1136 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1137 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1138 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1139 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1140 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1141 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1142 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1143 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1144 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1145 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1146 /* ------------------------------- */
1147 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1150 static const unsigned char twobyte_has_modrm
[256] = {
1151 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1152 /* ------------------------------- */
1153 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1154 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1155 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1156 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1157 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1158 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1159 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1160 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1161 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1162 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1163 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1164 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1165 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1166 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1167 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1168 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1169 /* ------------------------------- */
1170 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1173 static int amd64_syscall_p (const struct amd64_insn
*insn
, int *lengthp
);
1176 rex_prefix_p (gdb_byte pfx
)
1178 return REX_PREFIX_P (pfx
);
1181 /* True if PFX is the start of the 2-byte VEX prefix. */
1184 vex2_prefix_p (gdb_byte pfx
)
1189 /* True if PFX is the start of the 3-byte VEX prefix. */
1192 vex3_prefix_p (gdb_byte pfx
)
1197 /* Skip the legacy instruction prefixes in INSN.
1198 We assume INSN is properly sentineled so we don't have to worry
1199 about falling off the end of the buffer. */
1202 amd64_skip_prefixes (gdb_byte
*insn
)
1208 case DATA_PREFIX_OPCODE
:
1209 case ADDR_PREFIX_OPCODE
:
1210 case CS_PREFIX_OPCODE
:
1211 case DS_PREFIX_OPCODE
:
1212 case ES_PREFIX_OPCODE
:
1213 case FS_PREFIX_OPCODE
:
1214 case GS_PREFIX_OPCODE
:
1215 case SS_PREFIX_OPCODE
:
1216 case LOCK_PREFIX_OPCODE
:
1217 case REPE_PREFIX_OPCODE
:
1218 case REPNE_PREFIX_OPCODE
:
1230 /* Return an integer register (other than RSP) that is unused as an input
1232 In order to not require adding a rex prefix if the insn doesn't already
1233 have one, the result is restricted to RAX ... RDI, sans RSP.
1234 The register numbering of the result follows architecture ordering,
1238 amd64_get_unused_input_int_reg (const struct amd64_insn
*details
)
1240 /* 1 bit for each reg */
1241 int used_regs_mask
= 0;
1243 /* There can be at most 3 int regs used as inputs in an insn, and we have
1244 7 to choose from (RAX ... RDI, sans RSP).
1245 This allows us to take a conservative approach and keep things simple.
1246 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1247 that implicitly specify RAX. */
1250 used_regs_mask
|= 1 << EAX_REG_NUM
;
1251 /* Similarily avoid RDX, implicit operand in divides. */
1252 used_regs_mask
|= 1 << EDX_REG_NUM
;
1254 used_regs_mask
|= 1 << ESP_REG_NUM
;
1256 /* If the opcode is one byte long and there's no ModRM byte,
1257 assume the opcode specifies a register. */
1258 if (details
->opcode_len
== 1 && details
->modrm_offset
== -1)
1259 used_regs_mask
|= 1 << (details
->raw_insn
[details
->opcode_offset
] & 7);
1261 /* Mark used regs in the modrm/sib bytes. */
1262 if (details
->modrm_offset
!= -1)
1264 int modrm
= details
->raw_insn
[details
->modrm_offset
];
1265 int mod
= MODRM_MOD_FIELD (modrm
);
1266 int reg
= MODRM_REG_FIELD (modrm
);
1267 int rm
= MODRM_RM_FIELD (modrm
);
1268 int have_sib
= mod
!= 3 && rm
== 4;
1270 /* Assume the reg field of the modrm byte specifies a register. */
1271 used_regs_mask
|= 1 << reg
;
1275 int base
= SIB_BASE_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1276 int idx
= SIB_INDEX_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1277 used_regs_mask
|= 1 << base
;
1278 used_regs_mask
|= 1 << idx
;
1282 used_regs_mask
|= 1 << rm
;
1286 gdb_assert (used_regs_mask
< 256);
1287 gdb_assert (used_regs_mask
!= 255);
1289 /* Finally, find a free reg. */
1293 for (i
= 0; i
< 8; ++i
)
1295 if (! (used_regs_mask
& (1 << i
)))
1299 /* We shouldn't get here. */
1300 internal_error (__FILE__
, __LINE__
, _("unable to find free reg"));
1304 /* Extract the details of INSN that we need. */
1307 amd64_get_insn_details (gdb_byte
*insn
, struct amd64_insn
*details
)
1309 gdb_byte
*start
= insn
;
1312 details
->raw_insn
= insn
;
1314 details
->opcode_len
= -1;
1315 details
->enc_prefix_offset
= -1;
1316 details
->opcode_offset
= -1;
1317 details
->modrm_offset
= -1;
1319 /* Skip legacy instruction prefixes. */
1320 insn
= amd64_skip_prefixes (insn
);
1322 /* Skip REX/VEX instruction encoding prefixes. */
1323 if (rex_prefix_p (*insn
))
1325 details
->enc_prefix_offset
= insn
- start
;
1328 else if (vex2_prefix_p (*insn
))
1330 /* Don't record the offset in this case because this prefix has
1331 no REX.B equivalent. */
1334 else if (vex3_prefix_p (*insn
))
1336 details
->enc_prefix_offset
= insn
- start
;
1340 details
->opcode_offset
= insn
- start
;
1342 if (*insn
== TWO_BYTE_OPCODE_ESCAPE
)
1344 /* Two or three-byte opcode. */
1346 need_modrm
= twobyte_has_modrm
[*insn
];
1348 /* Check for three-byte opcode. */
1358 details
->opcode_len
= 3;
1361 details
->opcode_len
= 2;
1367 /* One-byte opcode. */
1368 need_modrm
= onebyte_has_modrm
[*insn
];
1369 details
->opcode_len
= 1;
1375 details
->modrm_offset
= insn
- start
;
1379 /* Update %rip-relative addressing in INSN.
1381 %rip-relative addressing only uses a 32-bit displacement.
1382 32 bits is not enough to be guaranteed to cover the distance between where
1383 the real instruction is and where its copy is.
1384 Convert the insn to use base+disp addressing.
1385 We set base = pc + insn_length so we can leave disp unchanged. */
1388 fixup_riprel (struct gdbarch
*gdbarch
, amd64_displaced_step_closure
*dsc
,
1389 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1391 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1392 int modrm_offset
= insn_details
->modrm_offset
;
1393 gdb_byte
*insn
= insn_details
->raw_insn
+ modrm_offset
;
1396 int arch_tmp_regno
, tmp_regno
;
1397 ULONGEST orig_value
;
1399 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1402 /* Compute the rip-relative address. */
1403 insn_length
= gdb_buffered_insn_length (gdbarch
, dsc
->insn_buf
.data (),
1404 dsc
->insn_buf
.size (), from
);
1405 rip_base
= from
+ insn_length
;
1407 /* We need a register to hold the address.
1408 Pick one not used in the insn.
1409 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1410 arch_tmp_regno
= amd64_get_unused_input_int_reg (insn_details
);
1411 tmp_regno
= amd64_arch_reg_to_regnum (arch_tmp_regno
);
1413 /* Position of the not-B bit in the 3-byte VEX prefix (in byte 1). */
1414 static constexpr gdb_byte VEX3_NOT_B
= 0x20;
1416 /* REX.B should be unset (VEX.!B set) as we were using rip-relative
1417 addressing, but ensure it's unset (set for VEX) anyway, tmp_regno
1419 if (insn_details
->enc_prefix_offset
!= -1)
1421 gdb_byte
*pfx
= &dsc
->insn_buf
[insn_details
->enc_prefix_offset
];
1422 if (rex_prefix_p (pfx
[0]))
1424 else if (vex3_prefix_p (pfx
[0]))
1425 pfx
[1] |= VEX3_NOT_B
;
1427 gdb_assert_not_reached ("unhandled prefix");
1430 regcache_cooked_read_unsigned (regs
, tmp_regno
, &orig_value
);
1431 dsc
->tmp_regno
= tmp_regno
;
1432 dsc
->tmp_save
= orig_value
;
1435 /* Convert the ModRM field to be base+disp. */
1436 dsc
->insn_buf
[modrm_offset
] &= ~0xc7;
1437 dsc
->insn_buf
[modrm_offset
] |= 0x80 + arch_tmp_regno
;
1439 regcache_cooked_write_unsigned (regs
, tmp_regno
, rip_base
);
1441 if (debug_displaced
)
1442 fprintf_unfiltered (gdb_stdlog
, "displaced: %%rip-relative addressing used.\n"
1443 "displaced: using temp reg %d, old value %s, new value %s\n",
1444 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
),
1445 paddress (gdbarch
, rip_base
));
1449 fixup_displaced_copy (struct gdbarch
*gdbarch
,
1450 amd64_displaced_step_closure
*dsc
,
1451 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1453 const struct amd64_insn
*details
= &dsc
->insn_details
;
1455 if (details
->modrm_offset
!= -1)
1457 gdb_byte modrm
= details
->raw_insn
[details
->modrm_offset
];
1459 if ((modrm
& 0xc7) == 0x05)
1461 /* The insn uses rip-relative addressing.
1463 fixup_riprel (gdbarch
, dsc
, from
, to
, regs
);
1468 displaced_step_closure_up
1469 amd64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1470 CORE_ADDR from
, CORE_ADDR to
,
1471 struct regcache
*regs
)
1473 int len
= gdbarch_max_insn_length (gdbarch
);
1474 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1475 continually watch for running off the end of the buffer. */
1476 int fixup_sentinel_space
= len
;
1477 std::unique_ptr
<amd64_displaced_step_closure
> dsc
1478 (new amd64_displaced_step_closure (len
+ fixup_sentinel_space
));
1479 gdb_byte
*buf
= &dsc
->insn_buf
[0];
1480 struct amd64_insn
*details
= &dsc
->insn_details
;
1482 read_memory (from
, buf
, len
);
1484 /* Set up the sentinel space so we don't have to worry about running
1485 off the end of the buffer. An excessive number of leading prefixes
1486 could otherwise cause this. */
1487 memset (buf
+ len
, 0, fixup_sentinel_space
);
1489 amd64_get_insn_details (buf
, details
);
1491 /* GDB may get control back after the insn after the syscall.
1492 Presumably this is a kernel bug.
1493 If this is a syscall, make sure there's a nop afterwards. */
1497 if (amd64_syscall_p (details
, &syscall_length
))
1498 buf
[details
->opcode_offset
+ syscall_length
] = NOP_OPCODE
;
1501 /* Modify the insn to cope with the address where it will be executed from.
1502 In particular, handle any rip-relative addressing. */
1503 fixup_displaced_copy (gdbarch
, dsc
.get (), from
, to
, regs
);
1505 write_memory (to
, buf
, len
);
1507 if (debug_displaced
)
1509 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1510 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1511 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1514 /* This is a work around for a problem with g++ 4.8. */
1515 return displaced_step_closure_up (dsc
.release ());
1519 amd64_absolute_jmp_p (const struct amd64_insn
*details
)
1521 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1523 if (insn
[0] == 0xff)
1525 /* jump near, absolute indirect (/4) */
1526 if ((insn
[1] & 0x38) == 0x20)
1529 /* jump far, absolute indirect (/5) */
1530 if ((insn
[1] & 0x38) == 0x28)
1537 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1540 amd64_jmp_p (const struct amd64_insn
*details
)
1542 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1544 /* jump short, relative. */
1545 if (insn
[0] == 0xeb)
1548 /* jump near, relative. */
1549 if (insn
[0] == 0xe9)
1552 return amd64_absolute_jmp_p (details
);
1556 amd64_absolute_call_p (const struct amd64_insn
*details
)
1558 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1560 if (insn
[0] == 0xff)
1562 /* Call near, absolute indirect (/2) */
1563 if ((insn
[1] & 0x38) == 0x10)
1566 /* Call far, absolute indirect (/3) */
1567 if ((insn
[1] & 0x38) == 0x18)
1575 amd64_ret_p (const struct amd64_insn
*details
)
1577 /* NOTE: gcc can emit "repz ; ret". */
1578 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1582 case 0xc2: /* ret near, pop N bytes */
1583 case 0xc3: /* ret near */
1584 case 0xca: /* ret far, pop N bytes */
1585 case 0xcb: /* ret far */
1586 case 0xcf: /* iret */
1595 amd64_call_p (const struct amd64_insn
*details
)
1597 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1599 if (amd64_absolute_call_p (details
))
1602 /* call near, relative */
1603 if (insn
[0] == 0xe8)
1609 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1610 length in bytes. Otherwise, return zero. */
1613 amd64_syscall_p (const struct amd64_insn
*details
, int *lengthp
)
1615 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1617 if (insn
[0] == 0x0f && insn
[1] == 0x05)
1626 /* Classify the instruction at ADDR using PRED.
1627 Throw an error if the memory can't be read. */
1630 amd64_classify_insn_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
1631 int (*pred
) (const struct amd64_insn
*))
1633 struct amd64_insn details
;
1635 int len
, classification
;
1637 len
= gdbarch_max_insn_length (gdbarch
);
1638 buf
= (gdb_byte
*) alloca (len
);
1640 read_code (addr
, buf
, len
);
1641 amd64_get_insn_details (buf
, &details
);
1643 classification
= pred (&details
);
1645 return classification
;
1648 /* The gdbarch insn_is_call method. */
1651 amd64_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1653 return amd64_classify_insn_at (gdbarch
, addr
, amd64_call_p
);
1656 /* The gdbarch insn_is_ret method. */
1659 amd64_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1661 return amd64_classify_insn_at (gdbarch
, addr
, amd64_ret_p
);
1664 /* The gdbarch insn_is_jump method. */
1667 amd64_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1669 return amd64_classify_insn_at (gdbarch
, addr
, amd64_jmp_p
);
1672 /* Fix up the state of registers and memory after having single-stepped
1673 a displaced instruction. */
1676 amd64_displaced_step_fixup (struct gdbarch
*gdbarch
,
1677 struct displaced_step_closure
*dsc_
,
1678 CORE_ADDR from
, CORE_ADDR to
,
1679 struct regcache
*regs
)
1681 amd64_displaced_step_closure
*dsc
= (amd64_displaced_step_closure
*) dsc_
;
1682 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1683 /* The offset we applied to the instruction's address. */
1684 ULONGEST insn_offset
= to
- from
;
1685 gdb_byte
*insn
= dsc
->insn_buf
.data ();
1686 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1688 if (debug_displaced
)
1689 fprintf_unfiltered (gdb_stdlog
,
1690 "displaced: fixup (%s, %s), "
1691 "insn = 0x%02x 0x%02x ...\n",
1692 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1695 /* If we used a tmp reg, restore it. */
1699 if (debug_displaced
)
1700 fprintf_unfiltered (gdb_stdlog
, "displaced: restoring reg %d to %s\n",
1701 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
));
1702 regcache_cooked_write_unsigned (regs
, dsc
->tmp_regno
, dsc
->tmp_save
);
1705 /* The list of issues to contend with here is taken from
1706 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1707 Yay for Free Software! */
1709 /* Relocate the %rip back to the program's instruction stream,
1712 /* Except in the case of absolute or indirect jump or call
1713 instructions, or a return instruction, the new rip is relative to
1714 the displaced instruction; make it relative to the original insn.
1715 Well, signal handler returns don't need relocation either, but we use the
1716 value of %rip to recognize those; see below. */
1717 if (! amd64_absolute_jmp_p (insn_details
)
1718 && ! amd64_absolute_call_p (insn_details
)
1719 && ! amd64_ret_p (insn_details
))
1724 regcache_cooked_read_unsigned (regs
, AMD64_RIP_REGNUM
, &orig_rip
);
1726 /* A signal trampoline system call changes the %rip, resuming
1727 execution of the main program after the signal handler has
1728 returned. That makes them like 'return' instructions; we
1729 shouldn't relocate %rip.
1731 But most system calls don't, and we do need to relocate %rip.
1733 Our heuristic for distinguishing these cases: if stepping
1734 over the system call instruction left control directly after
1735 the instruction, the we relocate --- control almost certainly
1736 doesn't belong in the displaced copy. Otherwise, we assume
1737 the instruction has put control where it belongs, and leave
1738 it unrelocated. Goodness help us if there are PC-relative
1740 if (amd64_syscall_p (insn_details
, &insn_len
)
1741 && orig_rip
!= to
+ insn_len
1742 /* GDB can get control back after the insn after the syscall.
1743 Presumably this is a kernel bug.
1744 Fixup ensures its a nop, we add one to the length for it. */
1745 && orig_rip
!= to
+ insn_len
+ 1)
1747 if (debug_displaced
)
1748 fprintf_unfiltered (gdb_stdlog
,
1749 "displaced: syscall changed %%rip; "
1750 "not relocating\n");
1754 ULONGEST rip
= orig_rip
- insn_offset
;
1756 /* If we just stepped over a breakpoint insn, we don't backup
1757 the pc on purpose; this is to match behaviour without
1760 regcache_cooked_write_unsigned (regs
, AMD64_RIP_REGNUM
, rip
);
1762 if (debug_displaced
)
1763 fprintf_unfiltered (gdb_stdlog
,
1765 "relocated %%rip from %s to %s\n",
1766 paddress (gdbarch
, orig_rip
),
1767 paddress (gdbarch
, rip
));
1771 /* If the instruction was PUSHFL, then the TF bit will be set in the
1772 pushed value, and should be cleared. We'll leave this for later,
1773 since GDB already messes up the TF flag when stepping over a
1776 /* If the instruction was a call, the return address now atop the
1777 stack is the address following the copied instruction. We need
1778 to make it the address following the original instruction. */
1779 if (amd64_call_p (insn_details
))
1783 const ULONGEST retaddr_len
= 8;
1785 regcache_cooked_read_unsigned (regs
, AMD64_RSP_REGNUM
, &rsp
);
1786 retaddr
= read_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
);
1787 retaddr
= (retaddr
- insn_offset
) & 0xffffffffffffffffULL
;
1788 write_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
, retaddr
);
1790 if (debug_displaced
)
1791 fprintf_unfiltered (gdb_stdlog
,
1792 "displaced: relocated return addr at %s "
1794 paddress (gdbarch
, rsp
),
1795 paddress (gdbarch
, retaddr
));
1799 /* If the instruction INSN uses RIP-relative addressing, return the
1800 offset into the raw INSN where the displacement to be adjusted is
1801 found. Returns 0 if the instruction doesn't use RIP-relative
1805 rip_relative_offset (struct amd64_insn
*insn
)
1807 if (insn
->modrm_offset
!= -1)
1809 gdb_byte modrm
= insn
->raw_insn
[insn
->modrm_offset
];
1811 if ((modrm
& 0xc7) == 0x05)
1813 /* The displacement is found right after the ModRM byte. */
1814 return insn
->modrm_offset
+ 1;
1822 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
1824 target_write_memory (*to
, buf
, len
);
1829 amd64_relocate_instruction (struct gdbarch
*gdbarch
,
1830 CORE_ADDR
*to
, CORE_ADDR oldloc
)
1832 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1833 int len
= gdbarch_max_insn_length (gdbarch
);
1834 /* Extra space for sentinels. */
1835 int fixup_sentinel_space
= len
;
1836 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
+ fixup_sentinel_space
);
1837 struct amd64_insn insn_details
;
1839 LONGEST rel32
, newrel
;
1843 read_memory (oldloc
, buf
, len
);
1845 /* Set up the sentinel space so we don't have to worry about running
1846 off the end of the buffer. An excessive number of leading prefixes
1847 could otherwise cause this. */
1848 memset (buf
+ len
, 0, fixup_sentinel_space
);
1851 amd64_get_insn_details (insn
, &insn_details
);
1853 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
, len
, oldloc
);
1855 /* Skip legacy instruction prefixes. */
1856 insn
= amd64_skip_prefixes (insn
);
1858 /* Adjust calls with 32-bit relative addresses as push/jump, with
1859 the address pushed being the location where the original call in
1860 the user program would return to. */
1861 if (insn
[0] == 0xe8)
1863 gdb_byte push_buf
[32];
1867 /* Where "ret" in the original code will return to. */
1868 ret_addr
= oldloc
+ insn_length
;
1870 /* If pushing an address higher than or equal to 0x80000000,
1871 avoid 'pushq', as that sign extends its 32-bit operand, which
1872 would be incorrect. */
1873 if (ret_addr
<= 0x7fffffff)
1875 push_buf
[0] = 0x68; /* pushq $... */
1876 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
1881 push_buf
[i
++] = 0x48; /* sub $0x8,%rsp */
1882 push_buf
[i
++] = 0x83;
1883 push_buf
[i
++] = 0xec;
1884 push_buf
[i
++] = 0x08;
1886 push_buf
[i
++] = 0xc7; /* movl $imm,(%rsp) */
1887 push_buf
[i
++] = 0x04;
1888 push_buf
[i
++] = 0x24;
1889 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1890 ret_addr
& 0xffffffff);
1893 push_buf
[i
++] = 0xc7; /* movl $imm,4(%rsp) */
1894 push_buf
[i
++] = 0x44;
1895 push_buf
[i
++] = 0x24;
1896 push_buf
[i
++] = 0x04;
1897 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1901 gdb_assert (i
<= sizeof (push_buf
));
1902 /* Push the push. */
1903 append_insns (to
, i
, push_buf
);
1905 /* Convert the relative call to a relative jump. */
1908 /* Adjust the destination offset. */
1909 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1910 newrel
= (oldloc
- *to
) + rel32
;
1911 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1913 if (debug_displaced
)
1914 fprintf_unfiltered (gdb_stdlog
,
1915 "Adjusted insn rel32=%s at %s to"
1916 " rel32=%s at %s\n",
1917 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1918 hex_string (newrel
), paddress (gdbarch
, *to
));
1920 /* Write the adjusted jump into its displaced location. */
1921 append_insns (to
, 5, insn
);
1925 offset
= rip_relative_offset (&insn_details
);
1928 /* Adjust jumps with 32-bit relative addresses. Calls are
1929 already handled above. */
1930 if (insn
[0] == 0xe9)
1932 /* Adjust conditional jumps. */
1933 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1939 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1940 newrel
= (oldloc
- *to
) + rel32
;
1941 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1942 if (debug_displaced
)
1943 fprintf_unfiltered (gdb_stdlog
,
1944 "Adjusted insn rel32=%s at %s to"
1945 " rel32=%s at %s\n",
1946 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1947 hex_string (newrel
), paddress (gdbarch
, *to
));
1950 /* Write the adjusted instruction into its displaced location. */
1951 append_insns (to
, insn_length
, buf
);
1955 /* The maximum number of saved registers. This should include %rip. */
1956 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1958 struct amd64_frame_cache
1963 CORE_ADDR sp_offset
;
1966 /* Saved registers. */
1967 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
1971 /* Do we have a frame? */
1975 /* Initialize a frame cache. */
1978 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
1985 cache
->sp_offset
= -8;
1988 /* Saved registers. We initialize these to -1 since zero is a valid
1989 offset (that's where %rbp is supposed to be stored).
1990 The values start out as being offsets, and are later converted to
1991 addresses (at which point -1 is interpreted as an address, still meaning
1993 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1994 cache
->saved_regs
[i
] = -1;
1995 cache
->saved_sp
= 0;
1996 cache
->saved_sp_reg
= -1;
1998 /* Frameless until proven otherwise. */
1999 cache
->frameless_p
= 1;
2002 /* Allocate and initialize a frame cache. */
2004 static struct amd64_frame_cache
*
2005 amd64_alloc_frame_cache (void)
2007 struct amd64_frame_cache
*cache
;
2009 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
2010 amd64_init_frame_cache (cache
);
2014 /* GCC 4.4 and later, can put code in the prologue to realign the
2015 stack pointer. Check whether PC points to such code, and update
2016 CACHE accordingly. Return the first instruction after the code
2017 sequence or CURRENT_PC, whichever is smaller. If we don't
2018 recognize the code, return PC. */
2021 amd64_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
2022 struct amd64_frame_cache
*cache
)
2024 /* There are 2 code sequences to re-align stack before the frame
2027 1. Use a caller-saved saved register:
2033 2. Use a callee-saved saved register:
2040 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2042 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2043 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2048 int offset
, offset_and
;
2050 if (target_read_code (pc
, buf
, sizeof buf
))
2053 /* Check caller-saved saved register. The first instruction has
2054 to be "leaq 8(%rsp), %reg". */
2055 if ((buf
[0] & 0xfb) == 0x48
2060 /* MOD must be binary 10 and R/M must be binary 100. */
2061 if ((buf
[2] & 0xc7) != 0x44)
2064 /* REG has register number. */
2065 reg
= (buf
[2] >> 3) & 7;
2067 /* Check the REX.R bit. */
2075 /* Check callee-saved saved register. The first instruction
2076 has to be "pushq %reg". */
2078 if ((buf
[0] & 0xf8) == 0x50)
2080 else if ((buf
[0] & 0xf6) == 0x40
2081 && (buf
[1] & 0xf8) == 0x50)
2083 /* Check the REX.B bit. */
2084 if ((buf
[0] & 1) != 0)
2093 reg
+= buf
[offset
] & 0x7;
2097 /* The next instruction has to be "leaq 16(%rsp), %reg". */
2098 if ((buf
[offset
] & 0xfb) != 0x48
2099 || buf
[offset
+ 1] != 0x8d
2100 || buf
[offset
+ 3] != 0x24
2101 || buf
[offset
+ 4] != 0x10)
2104 /* MOD must be binary 10 and R/M must be binary 100. */
2105 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2108 /* REG has register number. */
2109 r
= (buf
[offset
+ 2] >> 3) & 7;
2111 /* Check the REX.R bit. */
2112 if (buf
[offset
] == 0x4c)
2115 /* Registers in pushq and leaq have to be the same. */
2122 /* Rigister can't be %rsp nor %rbp. */
2123 if (reg
== 4 || reg
== 5)
2126 /* The next instruction has to be "andq $-XXX, %rsp". */
2127 if (buf
[offset
] != 0x48
2128 || buf
[offset
+ 2] != 0xe4
2129 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2132 offset_and
= offset
;
2133 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2135 /* The next instruction has to be "pushq -8(%reg)". */
2137 if (buf
[offset
] == 0xff)
2139 else if ((buf
[offset
] & 0xf6) == 0x40
2140 && buf
[offset
+ 1] == 0xff)
2142 /* Check the REX.B bit. */
2143 if ((buf
[offset
] & 0x1) != 0)
2150 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2152 if (buf
[offset
+ 1] != 0xf8
2153 || (buf
[offset
] & 0xf8) != 0x70)
2156 /* R/M has register. */
2157 r
+= buf
[offset
] & 7;
2159 /* Registers in leaq and pushq have to be the same. */
2163 if (current_pc
> pc
+ offset_and
)
2164 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2166 return std::min (pc
+ offset
+ 2, current_pc
);
2169 /* Similar to amd64_analyze_stack_align for x32. */
2172 amd64_x32_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
2173 struct amd64_frame_cache
*cache
)
2175 /* There are 2 code sequences to re-align stack before the frame
2178 1. Use a caller-saved saved register:
2186 [addr32] leal 8(%rsp), %reg
2188 [addr32] pushq -8(%reg)
2190 2. Use a callee-saved saved register:
2200 [addr32] leal 16(%rsp), %reg
2202 [addr32] pushq -8(%reg)
2204 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2206 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2207 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2209 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2211 0x83 0xe4 0xf0 andl $-16, %esp
2212 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2217 int offset
, offset_and
;
2219 if (target_read_memory (pc
, buf
, sizeof buf
))
2222 /* Skip optional addr32 prefix. */
2223 offset
= buf
[0] == 0x67 ? 1 : 0;
2225 /* Check caller-saved saved register. The first instruction has
2226 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2227 if (((buf
[offset
] & 0xfb) == 0x48 || (buf
[offset
] & 0xfb) == 0x40)
2228 && buf
[offset
+ 1] == 0x8d
2229 && buf
[offset
+ 3] == 0x24
2230 && buf
[offset
+ 4] == 0x8)
2232 /* MOD must be binary 10 and R/M must be binary 100. */
2233 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2236 /* REG has register number. */
2237 reg
= (buf
[offset
+ 2] >> 3) & 7;
2239 /* Check the REX.R bit. */
2240 if ((buf
[offset
] & 0x4) != 0)
2247 /* Check callee-saved saved register. The first instruction
2248 has to be "pushq %reg". */
2250 if ((buf
[offset
] & 0xf6) == 0x40
2251 && (buf
[offset
+ 1] & 0xf8) == 0x50)
2253 /* Check the REX.B bit. */
2254 if ((buf
[offset
] & 1) != 0)
2259 else if ((buf
[offset
] & 0xf8) != 0x50)
2263 reg
+= buf
[offset
] & 0x7;
2267 /* Skip optional addr32 prefix. */
2268 if (buf
[offset
] == 0x67)
2271 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2272 "leal 16(%rsp), %reg". */
2273 if (((buf
[offset
] & 0xfb) != 0x48 && (buf
[offset
] & 0xfb) != 0x40)
2274 || buf
[offset
+ 1] != 0x8d
2275 || buf
[offset
+ 3] != 0x24
2276 || buf
[offset
+ 4] != 0x10)
2279 /* MOD must be binary 10 and R/M must be binary 100. */
2280 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2283 /* REG has register number. */
2284 r
= (buf
[offset
+ 2] >> 3) & 7;
2286 /* Check the REX.R bit. */
2287 if ((buf
[offset
] & 0x4) != 0)
2290 /* Registers in pushq and leaq have to be the same. */
2297 /* Rigister can't be %rsp nor %rbp. */
2298 if (reg
== 4 || reg
== 5)
2301 /* The next instruction may be "andq $-XXX, %rsp" or
2302 "andl $-XXX, %esp". */
2303 if (buf
[offset
] != 0x48)
2306 if (buf
[offset
+ 2] != 0xe4
2307 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2310 offset_and
= offset
;
2311 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2313 /* Skip optional addr32 prefix. */
2314 if (buf
[offset
] == 0x67)
2317 /* The next instruction has to be "pushq -8(%reg)". */
2319 if (buf
[offset
] == 0xff)
2321 else if ((buf
[offset
] & 0xf6) == 0x40
2322 && buf
[offset
+ 1] == 0xff)
2324 /* Check the REX.B bit. */
2325 if ((buf
[offset
] & 0x1) != 0)
2332 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2334 if (buf
[offset
+ 1] != 0xf8
2335 || (buf
[offset
] & 0xf8) != 0x70)
2338 /* R/M has register. */
2339 r
+= buf
[offset
] & 7;
2341 /* Registers in leaq and pushq have to be the same. */
2345 if (current_pc
> pc
+ offset_and
)
2346 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2348 return std::min (pc
+ offset
+ 2, current_pc
);
2351 /* Do a limited analysis of the prologue at PC and update CACHE
2352 accordingly. Bail out early if CURRENT_PC is reached. Return the
2353 address where the analysis stopped.
2355 We will handle only functions beginning with:
2358 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2360 or (for the X32 ABI):
2363 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2365 Any function that doesn't start with one of these sequences will be
2366 assumed to have no prologue and thus no valid frame pointer in
2370 amd64_analyze_prologue (struct gdbarch
*gdbarch
,
2371 CORE_ADDR pc
, CORE_ADDR current_pc
,
2372 struct amd64_frame_cache
*cache
)
2374 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2375 /* There are two variations of movq %rsp, %rbp. */
2376 static const gdb_byte mov_rsp_rbp_1
[3] = { 0x48, 0x89, 0xe5 };
2377 static const gdb_byte mov_rsp_rbp_2
[3] = { 0x48, 0x8b, 0xec };
2378 /* Ditto for movl %esp, %ebp. */
2379 static const gdb_byte mov_esp_ebp_1
[2] = { 0x89, 0xe5 };
2380 static const gdb_byte mov_esp_ebp_2
[2] = { 0x8b, 0xec };
2385 if (current_pc
<= pc
)
2388 if (gdbarch_ptr_bit (gdbarch
) == 32)
2389 pc
= amd64_x32_analyze_stack_align (pc
, current_pc
, cache
);
2391 pc
= amd64_analyze_stack_align (pc
, current_pc
, cache
);
2393 op
= read_code_unsigned_integer (pc
, 1, byte_order
);
2395 if (op
== 0x55) /* pushq %rbp */
2397 /* Take into account that we've executed the `pushq %rbp' that
2398 starts this instruction sequence. */
2399 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
2400 cache
->sp_offset
+= 8;
2402 /* If that's all, return now. */
2403 if (current_pc
<= pc
+ 1)
2406 read_code (pc
+ 1, buf
, 3);
2408 /* Check for `movq %rsp, %rbp'. */
2409 if (memcmp (buf
, mov_rsp_rbp_1
, 3) == 0
2410 || memcmp (buf
, mov_rsp_rbp_2
, 3) == 0)
2412 /* OK, we actually have a frame. */
2413 cache
->frameless_p
= 0;
2417 /* For X32, also check for `movq %esp, %ebp'. */
2418 if (gdbarch_ptr_bit (gdbarch
) == 32)
2420 if (memcmp (buf
, mov_esp_ebp_1
, 2) == 0
2421 || memcmp (buf
, mov_esp_ebp_2
, 2) == 0)
2423 /* OK, we actually have a frame. */
2424 cache
->frameless_p
= 0;
2435 /* Work around false termination of prologue - GCC PR debug/48827.
2437 START_PC is the first instruction of a function, PC is its minimal already
2438 determined advanced address. Function returns PC if it has nothing to do.
2442 <-- here is 0 lines advance - the false prologue end marker.
2443 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2444 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2445 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2446 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2447 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2448 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2449 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2450 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2454 amd64_skip_xmm_prologue (CORE_ADDR pc
, CORE_ADDR start_pc
)
2456 struct symtab_and_line start_pc_sal
, next_sal
;
2457 gdb_byte buf
[4 + 8 * 7];
2463 start_pc_sal
= find_pc_sect_line (start_pc
, NULL
, 0);
2464 if (start_pc_sal
.symtab
== NULL
2465 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2466 (SYMTAB_COMPUNIT (start_pc_sal
.symtab
))) < 6
2467 || start_pc_sal
.pc
!= start_pc
|| pc
>= start_pc_sal
.end
)
2470 next_sal
= find_pc_sect_line (start_pc_sal
.end
, NULL
, 0);
2471 if (next_sal
.line
!= start_pc_sal
.line
)
2474 /* START_PC can be from overlayed memory, ignored here. */
2475 if (target_read_code (next_sal
.pc
- 4, buf
, sizeof (buf
)) != 0)
2479 if (buf
[0] != 0x84 || buf
[1] != 0xc0)
2486 for (xmmreg
= 0; xmmreg
< 8; xmmreg
++)
2488 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2489 if (buf
[offset
] != 0x0f || buf
[offset
+ 1] != 0x29
2490 || (buf
[offset
+ 2] & 0x3f) != (xmmreg
<< 3 | 0x5))
2494 if ((buf
[offset
+ 2] & 0xc0) == 0x40)
2496 /* 8-bit displacement. */
2500 else if ((buf
[offset
+ 2] & 0xc0) == 0x80)
2502 /* 32-bit displacement. */
2510 if (offset
- 4 != buf
[3])
2513 return next_sal
.end
;
2516 /* Return PC of first real instruction. */
2519 amd64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2521 struct amd64_frame_cache cache
;
2523 CORE_ADDR func_addr
;
2525 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
2527 CORE_ADDR post_prologue_pc
2528 = skip_prologue_using_sal (gdbarch
, func_addr
);
2529 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
2531 /* Clang always emits a line note before the prologue and another
2532 one after. We trust clang to emit usable line notes. */
2533 if (post_prologue_pc
2535 && COMPUNIT_PRODUCER (cust
) != NULL
2536 && startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
2537 return std::max (start_pc
, post_prologue_pc
);
2540 amd64_init_frame_cache (&cache
);
2541 pc
= amd64_analyze_prologue (gdbarch
, start_pc
, 0xffffffffffffffffLL
,
2543 if (cache
.frameless_p
)
2546 return amd64_skip_xmm_prologue (pc
, start_pc
);
2550 /* Normal frames. */
2553 amd64_frame_cache_1 (struct frame_info
*this_frame
,
2554 struct amd64_frame_cache
*cache
)
2556 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2557 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2561 cache
->pc
= get_frame_func (this_frame
);
2563 amd64_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2566 if (cache
->frameless_p
)
2568 /* We didn't find a valid frame. If we're at the start of a
2569 function, or somewhere half-way its prologue, the function's
2570 frame probably hasn't been fully setup yet. Try to
2571 reconstruct the base address for the stack frame by looking
2572 at the stack pointer. For truly "frameless" functions this
2575 if (cache
->saved_sp_reg
!= -1)
2577 /* Stack pointer has been saved. */
2578 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2579 cache
->saved_sp
= extract_unsigned_integer (buf
, 8, byte_order
);
2581 /* We're halfway aligning the stack. */
2582 cache
->base
= ((cache
->saved_sp
- 8) & 0xfffffffffffffff0LL
) - 8;
2583 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->saved_sp
- 8;
2585 /* This will be added back below. */
2586 cache
->saved_regs
[AMD64_RIP_REGNUM
] -= cache
->base
;
2590 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2591 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
)
2597 get_frame_register (this_frame
, AMD64_RBP_REGNUM
, buf
);
2598 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
);
2601 /* Now that we have the base address for the stack frame we can
2602 calculate the value of %rsp in the calling frame. */
2603 cache
->saved_sp
= cache
->base
+ 16;
2605 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2606 frame we find it at the same offset from the reconstructed base
2607 address. If we're halfway aligning the stack, %rip is handled
2608 differently (see above). */
2609 if (!cache
->frameless_p
|| cache
->saved_sp_reg
== -1)
2610 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
2612 /* Adjust all the saved registers such that they contain addresses
2613 instead of offsets. */
2614 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
2615 if (cache
->saved_regs
[i
] != -1)
2616 cache
->saved_regs
[i
] += cache
->base
;
2621 static struct amd64_frame_cache
*
2622 amd64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2624 struct amd64_frame_cache
*cache
;
2627 return (struct amd64_frame_cache
*) *this_cache
;
2629 cache
= amd64_alloc_frame_cache ();
2630 *this_cache
= cache
;
2634 amd64_frame_cache_1 (this_frame
, cache
);
2636 catch (const gdb_exception_error
&ex
)
2638 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2645 static enum unwind_stop_reason
2646 amd64_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2649 struct amd64_frame_cache
*cache
=
2650 amd64_frame_cache (this_frame
, this_cache
);
2653 return UNWIND_UNAVAILABLE
;
2655 /* This marks the outermost frame. */
2656 if (cache
->base
== 0)
2657 return UNWIND_OUTERMOST
;
2659 return UNWIND_NO_REASON
;
2663 amd64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2664 struct frame_id
*this_id
)
2666 struct amd64_frame_cache
*cache
=
2667 amd64_frame_cache (this_frame
, this_cache
);
2670 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2671 else if (cache
->base
== 0)
2673 /* This marks the outermost frame. */
2677 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
2680 static struct value
*
2681 amd64_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2684 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2685 struct amd64_frame_cache
*cache
=
2686 amd64_frame_cache (this_frame
, this_cache
);
2688 gdb_assert (regnum
>= 0);
2690 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2691 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2693 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2694 return frame_unwind_got_memory (this_frame
, regnum
,
2695 cache
->saved_regs
[regnum
]);
2697 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2700 static const struct frame_unwind amd64_frame_unwind
=
2703 amd64_frame_unwind_stop_reason
,
2704 amd64_frame_this_id
,
2705 amd64_frame_prev_register
,
2707 default_frame_sniffer
2710 /* Generate a bytecode expression to get the value of the saved PC. */
2713 amd64_gen_return_address (struct gdbarch
*gdbarch
,
2714 struct agent_expr
*ax
, struct axs_value
*value
,
2717 /* The following sequence assumes the traditional use of the base
2719 ax_reg (ax
, AMD64_RBP_REGNUM
);
2721 ax_simple (ax
, aop_add
);
2722 value
->type
= register_type (gdbarch
, AMD64_RIP_REGNUM
);
2723 value
->kind
= axs_lvalue_memory
;
2727 /* Signal trampolines. */
2729 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2730 64-bit variants. This would require using identical frame caches
2731 on both platforms. */
2733 static struct amd64_frame_cache
*
2734 amd64_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2736 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2737 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2738 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2739 struct amd64_frame_cache
*cache
;
2745 return (struct amd64_frame_cache
*) *this_cache
;
2747 cache
= amd64_alloc_frame_cache ();
2751 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2752 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
) - 8;
2754 addr
= tdep
->sigcontext_addr (this_frame
);
2755 gdb_assert (tdep
->sc_reg_offset
);
2756 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
2757 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2758 if (tdep
->sc_reg_offset
[i
] != -1)
2759 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2763 catch (const gdb_exception_error
&ex
)
2765 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2769 *this_cache
= cache
;
2773 static enum unwind_stop_reason
2774 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2777 struct amd64_frame_cache
*cache
=
2778 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2781 return UNWIND_UNAVAILABLE
;
2783 return UNWIND_NO_REASON
;
2787 amd64_sigtramp_frame_this_id (struct frame_info
*this_frame
,
2788 void **this_cache
, struct frame_id
*this_id
)
2790 struct amd64_frame_cache
*cache
=
2791 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2794 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2795 else if (cache
->base
== 0)
2797 /* This marks the outermost frame. */
2801 (*this_id
) = frame_id_build (cache
->base
+ 16, get_frame_pc (this_frame
));
2804 static struct value
*
2805 amd64_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2806 void **this_cache
, int regnum
)
2808 /* Make sure we've initialized the cache. */
2809 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2811 return amd64_frame_prev_register (this_frame
, this_cache
, regnum
);
2815 amd64_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2816 struct frame_info
*this_frame
,
2819 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2821 /* We shouldn't even bother if we don't have a sigcontext_addr
2823 if (tdep
->sigcontext_addr
== NULL
)
2826 if (tdep
->sigtramp_p
!= NULL
)
2828 if (tdep
->sigtramp_p (this_frame
))
2832 if (tdep
->sigtramp_start
!= 0)
2834 CORE_ADDR pc
= get_frame_pc (this_frame
);
2836 gdb_assert (tdep
->sigtramp_end
!= 0);
2837 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2844 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
2847 amd64_sigtramp_frame_unwind_stop_reason
,
2848 amd64_sigtramp_frame_this_id
,
2849 amd64_sigtramp_frame_prev_register
,
2851 amd64_sigtramp_frame_sniffer
2856 amd64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2858 struct amd64_frame_cache
*cache
=
2859 amd64_frame_cache (this_frame
, this_cache
);
2864 static const struct frame_base amd64_frame_base
=
2866 &amd64_frame_unwind
,
2867 amd64_frame_base_address
,
2868 amd64_frame_base_address
,
2869 amd64_frame_base_address
2872 /* Normal frames, but in a function epilogue. */
2874 /* Implement the stack_frame_destroyed_p gdbarch method.
2876 The epilogue is defined here as the 'ret' instruction, which will
2877 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2878 the function's stack frame. */
2881 amd64_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2884 struct compunit_symtab
*cust
;
2886 cust
= find_pc_compunit_symtab (pc
);
2887 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2890 if (target_read_memory (pc
, &insn
, 1))
2891 return 0; /* Can't read memory at pc. */
2893 if (insn
!= 0xc3) /* 'ret' instruction. */
2900 amd64_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2901 struct frame_info
*this_frame
,
2902 void **this_prologue_cache
)
2904 if (frame_relative_level (this_frame
) == 0)
2905 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2906 get_frame_pc (this_frame
));
2911 static struct amd64_frame_cache
*
2912 amd64_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2914 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2915 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2916 struct amd64_frame_cache
*cache
;
2920 return (struct amd64_frame_cache
*) *this_cache
;
2922 cache
= amd64_alloc_frame_cache ();
2923 *this_cache
= cache
;
2927 /* Cache base will be %esp plus cache->sp_offset (-8). */
2928 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2929 cache
->base
= extract_unsigned_integer (buf
, 8,
2930 byte_order
) + cache
->sp_offset
;
2932 /* Cache pc will be the frame func. */
2933 cache
->pc
= get_frame_pc (this_frame
);
2935 /* The saved %esp will be at cache->base plus 16. */
2936 cache
->saved_sp
= cache
->base
+ 16;
2938 /* The saved %eip will be at cache->base plus 8. */
2939 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->base
+ 8;
2943 catch (const gdb_exception_error
&ex
)
2945 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2952 static enum unwind_stop_reason
2953 amd64_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2956 struct amd64_frame_cache
*cache
2957 = amd64_epilogue_frame_cache (this_frame
, this_cache
);
2960 return UNWIND_UNAVAILABLE
;
2962 return UNWIND_NO_REASON
;
2966 amd64_epilogue_frame_this_id (struct frame_info
*this_frame
,
2968 struct frame_id
*this_id
)
2970 struct amd64_frame_cache
*cache
= amd64_epilogue_frame_cache (this_frame
,
2974 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2976 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2979 static const struct frame_unwind amd64_epilogue_frame_unwind
=
2982 amd64_epilogue_frame_unwind_stop_reason
,
2983 amd64_epilogue_frame_this_id
,
2984 amd64_frame_prev_register
,
2986 amd64_epilogue_frame_sniffer
2989 static struct frame_id
2990 amd64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2994 fp
= get_frame_register_unsigned (this_frame
, AMD64_RBP_REGNUM
);
2996 return frame_id_build (fp
+ 16, get_frame_pc (this_frame
));
2999 /* 16 byte align the SP per frame requirements. */
3002 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3004 return sp
& -(CORE_ADDR
)16;
3008 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3009 in the floating-point register set REGSET to register cache
3010 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3013 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3014 int regnum
, const void *fpregs
, size_t len
)
3016 struct gdbarch
*gdbarch
= regcache
->arch ();
3017 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3019 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3020 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
3023 /* Collect register REGNUM from the register cache REGCACHE and store
3024 it in the buffer specified by FPREGS and LEN as described by the
3025 floating-point register set REGSET. If REGNUM is -1, do this for
3026 all registers in REGSET. */
3029 amd64_collect_fpregset (const struct regset
*regset
,
3030 const struct regcache
*regcache
,
3031 int regnum
, void *fpregs
, size_t len
)
3033 struct gdbarch
*gdbarch
= regcache
->arch ();
3034 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3036 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3037 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
3040 const struct regset amd64_fpregset
=
3042 NULL
, amd64_supply_fpregset
, amd64_collect_fpregset
3046 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
3047 %rdi. We expect its value to be a pointer to the jmp_buf structure
3048 from which we extract the address that we will land at. This
3049 address is copied into PC. This routine returns non-zero on
3053 amd64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
3057 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3058 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
3059 int len
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_func_ptr
);
3061 /* If JB_PC_OFFSET is -1, we have no way to find out where the
3062 longjmp will land. */
3063 if (jb_pc_offset
== -1)
3066 get_frame_register (frame
, AMD64_RDI_REGNUM
, buf
);
3067 jb_addr
= extract_typed_address
3068 (buf
, builtin_type (gdbarch
)->builtin_data_ptr
);
3069 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, len
))
3072 *pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
3077 static const int amd64_record_regmap
[] =
3079 AMD64_RAX_REGNUM
, AMD64_RCX_REGNUM
, AMD64_RDX_REGNUM
, AMD64_RBX_REGNUM
,
3080 AMD64_RSP_REGNUM
, AMD64_RBP_REGNUM
, AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
3081 AMD64_R8_REGNUM
, AMD64_R9_REGNUM
, AMD64_R10_REGNUM
, AMD64_R11_REGNUM
,
3082 AMD64_R12_REGNUM
, AMD64_R13_REGNUM
, AMD64_R14_REGNUM
, AMD64_R15_REGNUM
,
3083 AMD64_RIP_REGNUM
, AMD64_EFLAGS_REGNUM
, AMD64_CS_REGNUM
, AMD64_SS_REGNUM
,
3084 AMD64_DS_REGNUM
, AMD64_ES_REGNUM
, AMD64_FS_REGNUM
, AMD64_GS_REGNUM
3087 /* Implement the "in_indirect_branch_thunk" gdbarch function. */
3090 amd64_in_indirect_branch_thunk (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3092 return x86_in_indirect_branch_thunk (pc
, amd64_register_names
,
3098 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
,
3099 const target_desc
*default_tdesc
)
3101 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3102 const struct target_desc
*tdesc
= info
.target_desc
;
3103 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
3104 static const char *const stap_register_prefixes
[] = { "%", NULL
};
3105 static const char *const stap_register_indirection_prefixes
[] = { "(",
3107 static const char *const stap_register_indirection_suffixes
[] = { ")",
3110 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
3111 floating-point registers. */
3112 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
3113 tdep
->fpregset
= &amd64_fpregset
;
3115 if (! tdesc_has_registers (tdesc
))
3116 tdesc
= default_tdesc
;
3117 tdep
->tdesc
= tdesc
;
3119 tdep
->num_core_regs
= AMD64_NUM_GREGS
+ I387_NUM_REGS
;
3120 tdep
->register_names
= amd64_register_names
;
3122 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512") != NULL
)
3124 tdep
->zmmh_register_names
= amd64_zmmh_names
;
3125 tdep
->k_register_names
= amd64_k_names
;
3126 tdep
->xmm_avx512_register_names
= amd64_xmm_avx512_names
;
3127 tdep
->ymm16h_register_names
= amd64_ymmh_avx512_names
;
3129 tdep
->num_zmm_regs
= 32;
3130 tdep
->num_xmm_avx512_regs
= 16;
3131 tdep
->num_ymm_avx512_regs
= 16;
3133 tdep
->zmm0h_regnum
= AMD64_ZMM0H_REGNUM
;
3134 tdep
->k0_regnum
= AMD64_K0_REGNUM
;
3135 tdep
->xmm16_regnum
= AMD64_XMM16_REGNUM
;
3136 tdep
->ymm16h_regnum
= AMD64_YMM16H_REGNUM
;
3139 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx") != NULL
)
3141 tdep
->ymmh_register_names
= amd64_ymmh_names
;
3142 tdep
->num_ymm_regs
= 16;
3143 tdep
->ymm0h_regnum
= AMD64_YMM0H_REGNUM
;
3146 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
)
3148 tdep
->mpx_register_names
= amd64_mpx_names
;
3149 tdep
->bndcfgu_regnum
= AMD64_BNDCFGU_REGNUM
;
3150 tdep
->bnd0r_regnum
= AMD64_BND0R_REGNUM
;
3153 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.segments") != NULL
)
3155 tdep
->fsbase_regnum
= AMD64_FSBASE_REGNUM
;
3158 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.pkeys") != NULL
)
3160 tdep
->pkeys_register_names
= amd64_pkeys_names
;
3161 tdep
->pkru_regnum
= AMD64_PKRU_REGNUM
;
3162 tdep
->num_pkeys_regs
= 1;
3165 tdep
->num_byte_regs
= 20;
3166 tdep
->num_word_regs
= 16;
3167 tdep
->num_dword_regs
= 16;
3168 /* Avoid wiring in the MMX registers for now. */
3169 tdep
->num_mmx_regs
= 0;
3171 set_gdbarch_pseudo_register_read_value (gdbarch
,
3172 amd64_pseudo_register_read_value
);
3173 set_gdbarch_pseudo_register_write (gdbarch
,
3174 amd64_pseudo_register_write
);
3175 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
3176 amd64_ax_pseudo_register_collect
);
3178 set_tdesc_pseudo_register_name (gdbarch
, amd64_pseudo_register_name
);
3180 /* AMD64 has an FPU and 16 SSE registers. */
3181 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
3182 tdep
->num_xmm_regs
= 16;
3184 /* This is what all the fuss is about. */
3185 set_gdbarch_long_bit (gdbarch
, 64);
3186 set_gdbarch_long_long_bit (gdbarch
, 64);
3187 set_gdbarch_ptr_bit (gdbarch
, 64);
3189 /* In contrast to the i386, on AMD64 a `long double' actually takes
3190 up 128 bits, even though it's still based on the i387 extended
3191 floating-point format which has only 80 significant bits. */
3192 set_gdbarch_long_double_bit (gdbarch
, 128);
3194 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
3196 /* Register numbers of various important registers. */
3197 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
3198 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
3199 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
3200 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
3202 /* The "default" register numbering scheme for AMD64 is referred to
3203 as the "DWARF Register Number Mapping" in the System V psABI.
3204 The preferred debugging format for all known AMD64 targets is
3205 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3206 DWARF-1), but we provide the same mapping just in case. This
3207 mapping is also used for stabs, which GCC does support. */
3208 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3209 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3211 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
3212 be in use on any of the supported AMD64 targets. */
3214 /* Call dummy code. */
3215 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
3216 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
3217 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
3219 set_gdbarch_convert_register_p (gdbarch
, i387_convert_register_p
);
3220 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
3221 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
3223 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
3225 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
3227 tdep
->record_regmap
= amd64_record_regmap
;
3229 set_gdbarch_dummy_id (gdbarch
, amd64_dummy_id
);
3231 /* Hook the function epilogue frame unwinder. This unwinder is
3232 appended to the list first, so that it supercedes the other
3233 unwinders in function epilogues. */
3234 frame_unwind_prepend_unwinder (gdbarch
, &amd64_epilogue_frame_unwind
);
3236 /* Hook the prologue-based frame unwinders. */
3237 frame_unwind_append_unwinder (gdbarch
, &amd64_sigtramp_frame_unwind
);
3238 frame_unwind_append_unwinder (gdbarch
, &amd64_frame_unwind
);
3239 frame_base_set_default (gdbarch
, &amd64_frame_base
);
3241 set_gdbarch_get_longjmp_target (gdbarch
, amd64_get_longjmp_target
);
3243 set_gdbarch_relocate_instruction (gdbarch
, amd64_relocate_instruction
);
3245 set_gdbarch_gen_return_address (gdbarch
, amd64_gen_return_address
);
3247 /* SystemTap variables and functions. */
3248 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
3249 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
3250 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
3251 stap_register_indirection_prefixes
);
3252 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
3253 stap_register_indirection_suffixes
);
3254 set_gdbarch_stap_is_single_operand (gdbarch
,
3255 i386_stap_is_single_operand
);
3256 set_gdbarch_stap_parse_special_token (gdbarch
,
3257 i386_stap_parse_special_token
);
3258 set_gdbarch_insn_is_call (gdbarch
, amd64_insn_is_call
);
3259 set_gdbarch_insn_is_ret (gdbarch
, amd64_insn_is_ret
);
3260 set_gdbarch_insn_is_jump (gdbarch
, amd64_insn_is_jump
);
3262 set_gdbarch_in_indirect_branch_thunk (gdbarch
,
3263 amd64_in_indirect_branch_thunk
);
3266 /* Initialize ARCH for x86-64, no osabi. */
3269 amd64_none_init_abi (gdbarch_info info
, gdbarch
*arch
)
3271 amd64_init_abi (info
, arch
, amd64_target_description (X86_XSTATE_SSE_MASK
,
3275 static struct type
*
3276 amd64_x32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3278 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3280 switch (regnum
- tdep
->eax_regnum
)
3282 case AMD64_RBP_REGNUM
: /* %ebp */
3283 case AMD64_RSP_REGNUM
: /* %esp */
3284 return builtin_type (gdbarch
)->builtin_data_ptr
;
3285 case AMD64_RIP_REGNUM
: /* %eip */
3286 return builtin_type (gdbarch
)->builtin_func_ptr
;
3289 return i386_pseudo_register_type (gdbarch
, regnum
);
3293 amd64_x32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
,
3294 const target_desc
*default_tdesc
)
3296 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3298 amd64_init_abi (info
, gdbarch
, default_tdesc
);
3300 tdep
->num_dword_regs
= 17;
3301 set_tdesc_pseudo_register_type (gdbarch
, amd64_x32_pseudo_register_type
);
3303 set_gdbarch_long_bit (gdbarch
, 32);
3304 set_gdbarch_ptr_bit (gdbarch
, 32);
3307 /* Initialize ARCH for x64-32, no osabi. */
3310 amd64_x32_none_init_abi (gdbarch_info info
, gdbarch
*arch
)
3312 amd64_x32_init_abi (info
, arch
,
3313 amd64_target_description (X86_XSTATE_SSE_MASK
, true));
3316 /* Return the target description for a specified XSAVE feature mask. */
3318 const struct target_desc
*
3319 amd64_target_description (uint64_t xcr0
, bool segments
)
3321 static target_desc
*amd64_tdescs \
3322 [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {};
3323 target_desc
**tdesc
;
3325 tdesc
= &amd64_tdescs
[(xcr0
& X86_XSTATE_AVX
) ? 1 : 0]
3326 [(xcr0
& X86_XSTATE_MPX
) ? 1 : 0]
3327 [(xcr0
& X86_XSTATE_AVX512
) ? 1 : 0]
3328 [(xcr0
& X86_XSTATE_PKRU
) ? 1 : 0]
3332 *tdesc
= amd64_create_target_description (xcr0
, false, false,
3338 void _initialize_amd64_tdep ();
3340 _initialize_amd64_tdep ()
3342 gdbarch_register_osabi (bfd_arch_i386
, bfd_mach_x86_64
, GDB_OSABI_NONE
,
3343 amd64_none_init_abi
);
3344 gdbarch_register_osabi (bfd_arch_i386
, bfd_mach_x64_32
, GDB_OSABI_NONE
,
3345 amd64_x32_none_init_abi
);
3349 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3350 sense that the instruction pointer and data pointer are simply
3351 64-bit offsets into the code segment and the data segment instead
3352 of a selector offset pair. The functions below store the upper 32
3353 bits of these pointers (instead of just the 16-bits of the segment
3356 /* Fill register REGNUM in REGCACHE with the appropriate
3357 floating-point or SSE register value from *FXSAVE. If REGNUM is
3358 -1, do this for all registers. This function masks off any of the
3359 reserved bits in *FXSAVE. */
3362 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
3365 struct gdbarch
*gdbarch
= regcache
->arch ();
3366 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3368 i387_supply_fxsave (regcache
, regnum
, fxsave
);
3371 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3373 const gdb_byte
*regs
= (const gdb_byte
*) fxsave
;
3375 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3376 regcache
->raw_supply (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3377 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3378 regcache
->raw_supply (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3382 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3385 amd64_supply_xsave (struct regcache
*regcache
, int regnum
,
3388 struct gdbarch
*gdbarch
= regcache
->arch ();
3389 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3391 i387_supply_xsave (regcache
, regnum
, xsave
);
3394 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3396 const gdb_byte
*regs
= (const gdb_byte
*) xsave
;
3399 clear_bv
= i387_xsave_get_clear_bv (gdbarch
, xsave
);
3401 /* If the FISEG and FOSEG registers have not been initialised yet
3402 (their CLEAR_BV bit is set) then their default values of zero will
3403 have already been setup by I387_SUPPLY_XSAVE. */
3404 if (!(clear_bv
& X86_XSTATE_X87
))
3406 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3407 regcache
->raw_supply (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3408 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3409 regcache
->raw_supply (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3414 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3415 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3416 all registers. This function doesn't touch any of the reserved
3420 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
3423 struct gdbarch
*gdbarch
= regcache
->arch ();
3424 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3425 gdb_byte
*regs
= (gdb_byte
*) fxsave
;
3427 i387_collect_fxsave (regcache
, regnum
, fxsave
);
3429 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3431 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3432 regcache
->raw_collect (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3433 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3434 regcache
->raw_collect (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3438 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3441 amd64_collect_xsave (const struct regcache
*regcache
, int regnum
,
3442 void *xsave
, int gcore
)
3444 struct gdbarch
*gdbarch
= regcache
->arch ();
3445 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3446 gdb_byte
*regs
= (gdb_byte
*) xsave
;
3448 i387_collect_xsave (regcache
, regnum
, xsave
, gcore
);
3450 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3452 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3453 regcache
->raw_collect (I387_FISEG_REGNUM (tdep
),
3455 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3456 regcache
->raw_collect (I387_FOSEG_REGNUM (tdep
),