1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2017 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
42 #include "x86-xstate.h"
44 #include "target-descriptions.h"
45 #include "arch/amd64.h"
49 /* Note that the AMD64 architecture was previously known as x86-64.
50 The latter is (forever) engraved into the canonical system name as
51 returned by config.guess, and used as the name for the AMD64 port
52 of GNU/Linux. The BSD's have renamed their ports to amd64; they
53 don't like to shout. For GDB we prefer the amd64_-prefix over the
54 x86_64_-prefix since it's so much easier to type. */
56 /* Register information. */
58 static const char *amd64_register_names
[] =
60 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
62 /* %r8 is indeed register number 8. */
63 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
64 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
66 /* %st0 is register number 24. */
67 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
68 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
70 /* %xmm0 is register number 40. */
71 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
72 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
76 static const char *amd64_ymm_names
[] =
78 "ymm0", "ymm1", "ymm2", "ymm3",
79 "ymm4", "ymm5", "ymm6", "ymm7",
80 "ymm8", "ymm9", "ymm10", "ymm11",
81 "ymm12", "ymm13", "ymm14", "ymm15"
84 static const char *amd64_ymm_avx512_names
[] =
86 "ymm16", "ymm17", "ymm18", "ymm19",
87 "ymm20", "ymm21", "ymm22", "ymm23",
88 "ymm24", "ymm25", "ymm26", "ymm27",
89 "ymm28", "ymm29", "ymm30", "ymm31"
92 static const char *amd64_ymmh_names
[] =
94 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
95 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
96 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
97 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
100 static const char *amd64_ymmh_avx512_names
[] =
102 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
103 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
104 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
105 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
108 static const char *amd64_mpx_names
[] =
110 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
113 static const char *amd64_k_names
[] =
115 "k0", "k1", "k2", "k3",
116 "k4", "k5", "k6", "k7"
119 static const char *amd64_zmmh_names
[] =
121 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
122 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
123 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
124 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
125 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
126 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
127 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
128 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
131 static const char *amd64_zmm_names
[] =
133 "zmm0", "zmm1", "zmm2", "zmm3",
134 "zmm4", "zmm5", "zmm6", "zmm7",
135 "zmm8", "zmm9", "zmm10", "zmm11",
136 "zmm12", "zmm13", "zmm14", "zmm15",
137 "zmm16", "zmm17", "zmm18", "zmm19",
138 "zmm20", "zmm21", "zmm22", "zmm23",
139 "zmm24", "zmm25", "zmm26", "zmm27",
140 "zmm28", "zmm29", "zmm30", "zmm31"
143 static const char *amd64_xmm_avx512_names
[] = {
144 "xmm16", "xmm17", "xmm18", "xmm19",
145 "xmm20", "xmm21", "xmm22", "xmm23",
146 "xmm24", "xmm25", "xmm26", "xmm27",
147 "xmm28", "xmm29", "xmm30", "xmm31"
150 static const char *amd64_pkeys_names
[] = {
154 /* DWARF Register Number Mapping as defined in the System V psABI,
157 static int amd64_dwarf_regmap
[] =
159 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
160 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
161 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
162 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
164 /* Frame Pointer Register RBP. */
167 /* Stack Pointer Register RSP. */
170 /* Extended Integer Registers 8 - 15. */
171 AMD64_R8_REGNUM
, /* %r8 */
172 AMD64_R9_REGNUM
, /* %r9 */
173 AMD64_R10_REGNUM
, /* %r10 */
174 AMD64_R11_REGNUM
, /* %r11 */
175 AMD64_R12_REGNUM
, /* %r12 */
176 AMD64_R13_REGNUM
, /* %r13 */
177 AMD64_R14_REGNUM
, /* %r14 */
178 AMD64_R15_REGNUM
, /* %r15 */
180 /* Return Address RA. Mapped to RIP. */
183 /* SSE Registers 0 - 7. */
184 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
185 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
186 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
187 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
189 /* Extended SSE Registers 8 - 15. */
190 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
191 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
192 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
193 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
195 /* Floating Point Registers 0-7. */
196 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
197 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
198 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
199 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
201 /* MMX Registers 0 - 7.
202 We have to handle those registers specifically, as their register
203 number within GDB depends on the target (or they may even not be
204 available at all). */
205 -1, -1, -1, -1, -1, -1, -1, -1,
207 /* Control and Status Flags Register. */
210 /* Selector Registers. */
220 /* Segment Base Address Registers. */
226 /* Special Selector Registers. */
230 /* Floating Point Control Registers. */
236 static const int amd64_dwarf_regmap_len
=
237 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
239 /* Convert DWARF register number REG to the appropriate register
240 number used by GDB. */
243 amd64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
245 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
246 int ymm0_regnum
= tdep
->ymm0_regnum
;
249 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
250 regnum
= amd64_dwarf_regmap
[reg
];
253 && i386_xmm_regnum_p (gdbarch
, regnum
))
254 regnum
+= ymm0_regnum
- I387_XMM0_REGNUM (tdep
);
259 /* Map architectural register numbers to gdb register numbers. */
261 static const int amd64_arch_regmap
[16] =
263 AMD64_RAX_REGNUM
, /* %rax */
264 AMD64_RCX_REGNUM
, /* %rcx */
265 AMD64_RDX_REGNUM
, /* %rdx */
266 AMD64_RBX_REGNUM
, /* %rbx */
267 AMD64_RSP_REGNUM
, /* %rsp */
268 AMD64_RBP_REGNUM
, /* %rbp */
269 AMD64_RSI_REGNUM
, /* %rsi */
270 AMD64_RDI_REGNUM
, /* %rdi */
271 AMD64_R8_REGNUM
, /* %r8 */
272 AMD64_R9_REGNUM
, /* %r9 */
273 AMD64_R10_REGNUM
, /* %r10 */
274 AMD64_R11_REGNUM
, /* %r11 */
275 AMD64_R12_REGNUM
, /* %r12 */
276 AMD64_R13_REGNUM
, /* %r13 */
277 AMD64_R14_REGNUM
, /* %r14 */
278 AMD64_R15_REGNUM
/* %r15 */
281 static const int amd64_arch_regmap_len
=
282 (sizeof (amd64_arch_regmap
) / sizeof (amd64_arch_regmap
[0]));
284 /* Convert architectural register number REG to the appropriate register
285 number used by GDB. */
288 amd64_arch_reg_to_regnum (int reg
)
290 gdb_assert (reg
>= 0 && reg
< amd64_arch_regmap_len
);
292 return amd64_arch_regmap
[reg
];
295 /* Register names for byte pseudo-registers. */
297 static const char *amd64_byte_names
[] =
299 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
300 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
301 "ah", "bh", "ch", "dh"
304 /* Number of lower byte registers. */
305 #define AMD64_NUM_LOWER_BYTE_REGS 16
307 /* Register names for word pseudo-registers. */
309 static const char *amd64_word_names
[] =
311 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
312 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
315 /* Register names for dword pseudo-registers. */
317 static const char *amd64_dword_names
[] =
319 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
320 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
324 /* Return the name of register REGNUM. */
327 amd64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
329 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
330 if (i386_byte_regnum_p (gdbarch
, regnum
))
331 return amd64_byte_names
[regnum
- tdep
->al_regnum
];
332 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
333 return amd64_zmm_names
[regnum
- tdep
->zmm0_regnum
];
334 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
335 return amd64_ymm_names
[regnum
- tdep
->ymm0_regnum
];
336 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
337 return amd64_ymm_avx512_names
[regnum
- tdep
->ymm16_regnum
];
338 else if (i386_word_regnum_p (gdbarch
, regnum
))
339 return amd64_word_names
[regnum
- tdep
->ax_regnum
];
340 else if (i386_dword_regnum_p (gdbarch
, regnum
))
341 return amd64_dword_names
[regnum
- tdep
->eax_regnum
];
343 return i386_pseudo_register_name (gdbarch
, regnum
);
346 static struct value
*
347 amd64_pseudo_register_read_value (struct gdbarch
*gdbarch
,
348 struct regcache
*regcache
,
351 gdb_byte
*raw_buf
= (gdb_byte
*) alloca (register_size (gdbarch
, regnum
));
352 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
353 enum register_status status
;
354 struct value
*result_value
;
357 result_value
= allocate_value (register_type (gdbarch
, regnum
));
358 VALUE_LVAL (result_value
) = lval_register
;
359 VALUE_REGNUM (result_value
) = regnum
;
360 buf
= value_contents_raw (result_value
);
362 if (i386_byte_regnum_p (gdbarch
, regnum
))
364 int gpnum
= regnum
- tdep
->al_regnum
;
366 /* Extract (always little endian). */
367 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
369 /* Special handling for AH, BH, CH, DH. */
370 status
= regcache_raw_read (regcache
,
371 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
,
373 if (status
== REG_VALID
)
374 memcpy (buf
, raw_buf
+ 1, 1);
376 mark_value_bytes_unavailable (result_value
, 0,
377 TYPE_LENGTH (value_type (result_value
)));
381 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
382 if (status
== REG_VALID
)
383 memcpy (buf
, raw_buf
, 1);
385 mark_value_bytes_unavailable (result_value
, 0,
386 TYPE_LENGTH (value_type (result_value
)));
389 else if (i386_dword_regnum_p (gdbarch
, regnum
))
391 int gpnum
= regnum
- tdep
->eax_regnum
;
392 /* Extract (always little endian). */
393 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
394 if (status
== REG_VALID
)
395 memcpy (buf
, raw_buf
, 4);
397 mark_value_bytes_unavailable (result_value
, 0,
398 TYPE_LENGTH (value_type (result_value
)));
401 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
,
408 amd64_pseudo_register_write (struct gdbarch
*gdbarch
,
409 struct regcache
*regcache
,
410 int regnum
, const gdb_byte
*buf
)
412 gdb_byte
*raw_buf
= (gdb_byte
*) alloca (register_size (gdbarch
, regnum
));
413 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
415 if (i386_byte_regnum_p (gdbarch
, regnum
))
417 int gpnum
= regnum
- tdep
->al_regnum
;
419 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
421 /* Read ... AH, BH, CH, DH. */
422 regcache_raw_read (regcache
,
423 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
424 /* ... Modify ... (always little endian). */
425 memcpy (raw_buf
+ 1, buf
, 1);
427 regcache_raw_write (regcache
,
428 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
433 regcache_raw_read (regcache
, gpnum
, raw_buf
);
434 /* ... Modify ... (always little endian). */
435 memcpy (raw_buf
, buf
, 1);
437 regcache_raw_write (regcache
, gpnum
, raw_buf
);
440 else if (i386_dword_regnum_p (gdbarch
, regnum
))
442 int gpnum
= regnum
- tdep
->eax_regnum
;
445 regcache_raw_read (regcache
, gpnum
, raw_buf
);
446 /* ... Modify ... (always little endian). */
447 memcpy (raw_buf
, buf
, 4);
449 regcache_raw_write (regcache
, gpnum
, raw_buf
);
452 i386_pseudo_register_write (gdbarch
, regcache
, regnum
, buf
);
455 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
458 amd64_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
459 struct agent_expr
*ax
, int regnum
)
461 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
463 if (i386_byte_regnum_p (gdbarch
, regnum
))
465 int gpnum
= regnum
- tdep
->al_regnum
;
467 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
468 ax_reg_mask (ax
, gpnum
- AMD64_NUM_LOWER_BYTE_REGS
);
470 ax_reg_mask (ax
, gpnum
);
473 else if (i386_dword_regnum_p (gdbarch
, regnum
))
475 int gpnum
= regnum
- tdep
->eax_regnum
;
477 ax_reg_mask (ax
, gpnum
);
481 return i386_ax_pseudo_register_collect (gdbarch
, ax
, regnum
);
486 /* Register classes as defined in the psABI. */
500 /* Return the union class of CLASS1 and CLASS2. See the psABI for
503 static enum amd64_reg_class
504 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
506 /* Rule (a): If both classes are equal, this is the resulting class. */
507 if (class1
== class2
)
510 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
511 is the other class. */
512 if (class1
== AMD64_NO_CLASS
)
514 if (class2
== AMD64_NO_CLASS
)
517 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
518 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
521 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
522 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
523 return AMD64_INTEGER
;
525 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
526 MEMORY is used as class. */
527 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
528 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
529 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
532 /* Rule (f): Otherwise class SSE is used. */
536 static void amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2]);
538 /* Return non-zero if TYPE is a non-POD structure or union type. */
541 amd64_non_pod_p (struct type
*type
)
543 /* ??? A class with a base class certainly isn't POD, but does this
544 catch all non-POD structure types? */
545 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
&& TYPE_N_BASECLASSES (type
) > 0)
551 /* Classify TYPE according to the rules for aggregate (structures and
552 arrays) and union types, and store the result in CLASS. */
555 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class theclass
[2])
557 /* 1. If the size of an object is larger than two eightbytes, or in
558 C++, is a non-POD structure or union type, or contains
559 unaligned fields, it has class memory. */
560 if (TYPE_LENGTH (type
) > 16 || amd64_non_pod_p (type
))
562 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
566 /* 2. Both eightbytes get initialized to class NO_CLASS. */
567 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
569 /* 3. Each field of an object is classified recursively so that
570 always two fields are considered. The resulting class is
571 calculated according to the classes of the fields in the
574 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
576 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
578 /* All fields in an array have the same type. */
579 amd64_classify (subtype
, theclass
);
580 if (TYPE_LENGTH (type
) > 8 && theclass
[1] == AMD64_NO_CLASS
)
581 theclass
[1] = theclass
[0];
587 /* Structure or union. */
588 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
589 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
591 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
593 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
594 int pos
= TYPE_FIELD_BITPOS (type
, i
) / 64;
595 enum amd64_reg_class subclass
[2];
596 int bitsize
= TYPE_FIELD_BITSIZE (type
, i
);
600 bitsize
= TYPE_LENGTH (subtype
) * 8;
601 endpos
= (TYPE_FIELD_BITPOS (type
, i
) + bitsize
- 1) / 64;
603 /* Ignore static fields. */
604 if (field_is_static (&TYPE_FIELD (type
, i
)))
607 gdb_assert (pos
== 0 || pos
== 1);
609 amd64_classify (subtype
, subclass
);
610 theclass
[pos
] = amd64_merge_classes (theclass
[pos
], subclass
[0]);
611 if (bitsize
<= 64 && pos
== 0 && endpos
== 1)
612 /* This is a bit of an odd case: We have a field that would
613 normally fit in one of the two eightbytes, except that
614 it is placed in a way that this field straddles them.
615 This has been seen with a structure containing an array.
617 The ABI is a bit unclear in this case, but we assume that
618 this field's class (stored in subclass[0]) must also be merged
619 into class[1]. In other words, our field has a piece stored
620 in the second eight-byte, and thus its class applies to
621 the second eight-byte as well.
623 In the case where the field length exceeds 8 bytes,
624 it should not be necessary to merge the field class
625 into class[1]. As LEN > 8, subclass[1] is necessarily
626 different from AMD64_NO_CLASS. If subclass[1] is equal
627 to subclass[0], then the normal class[1]/subclass[1]
628 merging will take care of everything. For subclass[1]
629 to be different from subclass[0], I can only see the case
630 where we have a SSE/SSEUP or X87/X87UP pair, which both
631 use up all 16 bytes of the aggregate, and are already
632 handled just fine (because each portion sits on its own
634 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[0]);
636 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[1]);
640 /* 4. Then a post merger cleanup is done: */
642 /* Rule (a): If one of the classes is MEMORY, the whole argument is
644 if (theclass
[0] == AMD64_MEMORY
|| theclass
[1] == AMD64_MEMORY
)
645 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
647 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
649 if (theclass
[0] == AMD64_SSEUP
)
650 theclass
[0] = AMD64_SSE
;
651 if (theclass
[1] == AMD64_SSEUP
&& theclass
[0] != AMD64_SSE
)
652 theclass
[1] = AMD64_SSE
;
655 /* Classify TYPE, and store the result in CLASS. */
658 amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2])
660 enum type_code code
= TYPE_CODE (type
);
661 int len
= TYPE_LENGTH (type
);
663 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
665 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
666 long, long long, and pointers are in the INTEGER class. Similarly,
667 range types, used by languages such as Ada, are also in the INTEGER
669 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
670 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
671 || code
== TYPE_CODE_CHAR
672 || code
== TYPE_CODE_PTR
|| TYPE_IS_REFERENCE (type
))
673 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
674 theclass
[0] = AMD64_INTEGER
;
676 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
678 else if ((code
== TYPE_CODE_FLT
|| code
== TYPE_CODE_DECFLOAT
)
679 && (len
== 4 || len
== 8))
681 theclass
[0] = AMD64_SSE
;
683 /* Arguments of types __float128, _Decimal128 and __m128 are split into
684 two halves. The least significant ones belong to class SSE, the most
685 significant one to class SSEUP. */
686 else if (code
== TYPE_CODE_DECFLOAT
&& len
== 16)
687 /* FIXME: __float128, __m128. */
688 theclass
[0] = AMD64_SSE
, theclass
[1] = AMD64_SSEUP
;
690 /* The 64-bit mantissa of arguments of type long double belongs to
691 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
693 else if (code
== TYPE_CODE_FLT
&& len
== 16)
694 /* Class X87 and X87UP. */
695 theclass
[0] = AMD64_X87
, theclass
[1] = AMD64_X87UP
;
697 /* Arguments of complex T where T is one of the types float or
698 double get treated as if they are implemented as:
706 else if (code
== TYPE_CODE_COMPLEX
&& len
== 8)
707 theclass
[0] = AMD64_SSE
;
708 else if (code
== TYPE_CODE_COMPLEX
&& len
== 16)
709 theclass
[0] = theclass
[1] = AMD64_SSE
;
711 /* A variable of type complex long double is classified as type
713 else if (code
== TYPE_CODE_COMPLEX
&& len
== 32)
714 theclass
[0] = AMD64_COMPLEX_X87
;
717 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
718 || code
== TYPE_CODE_UNION
)
719 amd64_classify_aggregate (type
, theclass
);
722 static enum return_value_convention
723 amd64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
724 struct type
*type
, struct regcache
*regcache
,
725 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
727 enum amd64_reg_class theclass
[2];
728 int len
= TYPE_LENGTH (type
);
729 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
730 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
735 gdb_assert (!(readbuf
&& writebuf
));
737 /* 1. Classify the return type with the classification algorithm. */
738 amd64_classify (type
, theclass
);
740 /* 2. If the type has class MEMORY, then the caller provides space
741 for the return value and passes the address of this storage in
742 %rdi as if it were the first argument to the function. In effect,
743 this address becomes a hidden first argument.
745 On return %rax will contain the address that has been passed in
746 by the caller in %rdi. */
747 if (theclass
[0] == AMD64_MEMORY
)
749 /* As indicated by the comment above, the ABI guarantees that we
750 can always find the return value just after the function has
757 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
758 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
761 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
764 /* 8. If the class is COMPLEX_X87, the real part of the value is
765 returned in %st0 and the imaginary part in %st1. */
766 if (theclass
[0] == AMD64_COMPLEX_X87
)
770 regcache_raw_read (regcache
, AMD64_ST0_REGNUM
, readbuf
);
771 regcache_raw_read (regcache
, AMD64_ST1_REGNUM
, readbuf
+ 16);
776 i387_return_value (gdbarch
, regcache
);
777 regcache_raw_write (regcache
, AMD64_ST0_REGNUM
, writebuf
);
778 regcache_raw_write (regcache
, AMD64_ST1_REGNUM
, writebuf
+ 16);
780 /* Fix up the tag word such that both %st(0) and %st(1) are
782 regcache_raw_write_unsigned (regcache
, AMD64_FTAG_REGNUM
, 0xfff);
785 return RETURN_VALUE_REGISTER_CONVENTION
;
788 gdb_assert (theclass
[1] != AMD64_MEMORY
);
789 gdb_assert (len
<= 16);
791 for (i
= 0; len
> 0; i
++, len
-= 8)
799 /* 3. If the class is INTEGER, the next available register
800 of the sequence %rax, %rdx is used. */
801 regnum
= integer_regnum
[integer_reg
++];
805 /* 4. If the class is SSE, the next available SSE register
806 of the sequence %xmm0, %xmm1 is used. */
807 regnum
= sse_regnum
[sse_reg
++];
811 /* 5. If the class is SSEUP, the eightbyte is passed in the
812 upper half of the last used SSE register. */
813 gdb_assert (sse_reg
> 0);
814 regnum
= sse_regnum
[sse_reg
- 1];
819 /* 6. If the class is X87, the value is returned on the X87
820 stack in %st0 as 80-bit x87 number. */
821 regnum
= AMD64_ST0_REGNUM
;
823 i387_return_value (gdbarch
, regcache
);
827 /* 7. If the class is X87UP, the value is returned together
828 with the previous X87 value in %st0. */
829 gdb_assert (i
> 0 && theclass
[0] == AMD64_X87
);
830 regnum
= AMD64_ST0_REGNUM
;
839 gdb_assert (!"Unexpected register class.");
842 gdb_assert (regnum
!= -1);
845 regcache_raw_read_part (regcache
, regnum
, offset
, std::min (len
, 8),
848 regcache_raw_write_part (regcache
, regnum
, offset
, std::min (len
, 8),
852 return RETURN_VALUE_REGISTER_CONVENTION
;
857 amd64_push_arguments (struct regcache
*regcache
, int nargs
,
858 struct value
**args
, CORE_ADDR sp
, int struct_return
)
860 static int integer_regnum
[] =
862 AMD64_RDI_REGNUM
, /* %rdi */
863 AMD64_RSI_REGNUM
, /* %rsi */
864 AMD64_RDX_REGNUM
, /* %rdx */
865 AMD64_RCX_REGNUM
, /* %rcx */
866 AMD64_R8_REGNUM
, /* %r8 */
867 AMD64_R9_REGNUM
/* %r9 */
869 static int sse_regnum
[] =
871 /* %xmm0 ... %xmm7 */
872 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
873 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
874 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
875 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
877 struct value
**stack_args
= XALLOCAVEC (struct value
*, nargs
);
878 int num_stack_args
= 0;
879 int num_elements
= 0;
885 /* Reserve a register for the "hidden" argument. */
889 for (i
= 0; i
< nargs
; i
++)
891 struct type
*type
= value_type (args
[i
]);
892 int len
= TYPE_LENGTH (type
);
893 enum amd64_reg_class theclass
[2];
894 int needed_integer_regs
= 0;
895 int needed_sse_regs
= 0;
898 /* Classify argument. */
899 amd64_classify (type
, theclass
);
901 /* Calculate the number of integer and SSE registers needed for
903 for (j
= 0; j
< 2; j
++)
905 if (theclass
[j
] == AMD64_INTEGER
)
906 needed_integer_regs
++;
907 else if (theclass
[j
] == AMD64_SSE
)
911 /* Check whether enough registers are available, and if the
912 argument should be passed in registers at all. */
913 if (integer_reg
+ needed_integer_regs
> ARRAY_SIZE (integer_regnum
)
914 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
915 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
917 /* The argument will be passed on the stack. */
918 num_elements
+= ((len
+ 7) / 8);
919 stack_args
[num_stack_args
++] = args
[i
];
923 /* The argument will be passed in registers. */
924 const gdb_byte
*valbuf
= value_contents (args
[i
]);
927 gdb_assert (len
<= 16);
929 for (j
= 0; len
> 0; j
++, len
-= 8)
937 regnum
= integer_regnum
[integer_reg
++];
941 regnum
= sse_regnum
[sse_reg
++];
945 gdb_assert (sse_reg
> 0);
946 regnum
= sse_regnum
[sse_reg
- 1];
951 gdb_assert (!"Unexpected register class.");
954 gdb_assert (regnum
!= -1);
955 memset (buf
, 0, sizeof buf
);
956 memcpy (buf
, valbuf
+ j
* 8, std::min (len
, 8));
957 regcache_raw_write_part (regcache
, regnum
, offset
, 8, buf
);
962 /* Allocate space for the arguments on the stack. */
963 sp
-= num_elements
* 8;
965 /* The psABI says that "The end of the input argument area shall be
966 aligned on a 16 byte boundary." */
969 /* Write out the arguments to the stack. */
970 for (i
= 0; i
< num_stack_args
; i
++)
972 struct type
*type
= value_type (stack_args
[i
]);
973 const gdb_byte
*valbuf
= value_contents (stack_args
[i
]);
974 int len
= TYPE_LENGTH (type
);
976 write_memory (sp
+ element
* 8, valbuf
, len
);
977 element
+= ((len
+ 7) / 8);
980 /* The psABI says that "For calls that may call functions that use
981 varargs or stdargs (prototype-less calls or calls to functions
982 containing ellipsis (...) in the declaration) %al is used as
983 hidden argument to specify the number of SSE registers used. */
984 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
989 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
990 struct regcache
*regcache
, CORE_ADDR bp_addr
,
991 int nargs
, struct value
**args
, CORE_ADDR sp
,
992 int struct_return
, CORE_ADDR struct_addr
)
994 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
997 /* BND registers can be in arbitrary values at the moment of the
998 inferior call. This can cause boundary violations that are not
999 due to a real bug or even desired by the user. The best to be done
1000 is set the BND registers to allow access to the whole memory, INIT
1001 state, before pushing the inferior call. */
1002 i387_reset_bnd_regs (gdbarch
, regcache
);
1004 /* Pass arguments. */
1005 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, struct_return
);
1007 /* Pass "hidden" argument". */
1010 store_unsigned_integer (buf
, 8, byte_order
, struct_addr
);
1011 regcache_cooked_write (regcache
, AMD64_RDI_REGNUM
, buf
);
1014 /* Store return address. */
1016 store_unsigned_integer (buf
, 8, byte_order
, bp_addr
);
1017 write_memory (sp
, buf
, 8);
1019 /* Finally, update the stack pointer... */
1020 store_unsigned_integer (buf
, 8, byte_order
, sp
);
1021 regcache_cooked_write (regcache
, AMD64_RSP_REGNUM
, buf
);
1023 /* ...and fake a frame pointer. */
1024 regcache_cooked_write (regcache
, AMD64_RBP_REGNUM
, buf
);
1029 /* Displaced instruction handling. */
1031 /* A partially decoded instruction.
1032 This contains enough details for displaced stepping purposes. */
1036 /* The number of opcode bytes. */
1038 /* The offset of the rex prefix or -1 if not present. */
1040 /* The offset to the first opcode byte. */
1042 /* The offset to the modrm byte or -1 if not present. */
1045 /* The raw instruction. */
1049 struct displaced_step_closure
1051 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1056 /* Details of the instruction. */
1057 struct amd64_insn insn_details
;
1059 /* Amount of space allocated to insn_buf. */
1062 /* The possibly modified insn.
1063 This is a variable-length field. */
1064 gdb_byte insn_buf
[1];
1067 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1068 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1069 at which point delete these in favor of libopcodes' versions). */
1071 static const unsigned char onebyte_has_modrm
[256] = {
1072 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1073 /* ------------------------------- */
1074 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1075 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1076 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1077 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1078 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1079 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1080 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1081 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1082 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1083 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1084 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1085 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1086 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1087 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1088 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1089 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1090 /* ------------------------------- */
1091 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1094 static const unsigned char twobyte_has_modrm
[256] = {
1095 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1096 /* ------------------------------- */
1097 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1098 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1099 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1100 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1101 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1102 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1103 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1104 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1105 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1106 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1107 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1108 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1109 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1110 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1111 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1112 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1113 /* ------------------------------- */
1114 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1117 static int amd64_syscall_p (const struct amd64_insn
*insn
, int *lengthp
);
1120 rex_prefix_p (gdb_byte pfx
)
1122 return REX_PREFIX_P (pfx
);
1125 /* Skip the legacy instruction prefixes in INSN.
1126 We assume INSN is properly sentineled so we don't have to worry
1127 about falling off the end of the buffer. */
1130 amd64_skip_prefixes (gdb_byte
*insn
)
1136 case DATA_PREFIX_OPCODE
:
1137 case ADDR_PREFIX_OPCODE
:
1138 case CS_PREFIX_OPCODE
:
1139 case DS_PREFIX_OPCODE
:
1140 case ES_PREFIX_OPCODE
:
1141 case FS_PREFIX_OPCODE
:
1142 case GS_PREFIX_OPCODE
:
1143 case SS_PREFIX_OPCODE
:
1144 case LOCK_PREFIX_OPCODE
:
1145 case REPE_PREFIX_OPCODE
:
1146 case REPNE_PREFIX_OPCODE
:
1158 /* Return an integer register (other than RSP) that is unused as an input
1160 In order to not require adding a rex prefix if the insn doesn't already
1161 have one, the result is restricted to RAX ... RDI, sans RSP.
1162 The register numbering of the result follows architecture ordering,
1166 amd64_get_unused_input_int_reg (const struct amd64_insn
*details
)
1168 /* 1 bit for each reg */
1169 int used_regs_mask
= 0;
1171 /* There can be at most 3 int regs used as inputs in an insn, and we have
1172 7 to choose from (RAX ... RDI, sans RSP).
1173 This allows us to take a conservative approach and keep things simple.
1174 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1175 that implicitly specify RAX. */
1178 used_regs_mask
|= 1 << EAX_REG_NUM
;
1179 /* Similarily avoid RDX, implicit operand in divides. */
1180 used_regs_mask
|= 1 << EDX_REG_NUM
;
1182 used_regs_mask
|= 1 << ESP_REG_NUM
;
1184 /* If the opcode is one byte long and there's no ModRM byte,
1185 assume the opcode specifies a register. */
1186 if (details
->opcode_len
== 1 && details
->modrm_offset
== -1)
1187 used_regs_mask
|= 1 << (details
->raw_insn
[details
->opcode_offset
] & 7);
1189 /* Mark used regs in the modrm/sib bytes. */
1190 if (details
->modrm_offset
!= -1)
1192 int modrm
= details
->raw_insn
[details
->modrm_offset
];
1193 int mod
= MODRM_MOD_FIELD (modrm
);
1194 int reg
= MODRM_REG_FIELD (modrm
);
1195 int rm
= MODRM_RM_FIELD (modrm
);
1196 int have_sib
= mod
!= 3 && rm
== 4;
1198 /* Assume the reg field of the modrm byte specifies a register. */
1199 used_regs_mask
|= 1 << reg
;
1203 int base
= SIB_BASE_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1204 int idx
= SIB_INDEX_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1205 used_regs_mask
|= 1 << base
;
1206 used_regs_mask
|= 1 << idx
;
1210 used_regs_mask
|= 1 << rm
;
1214 gdb_assert (used_regs_mask
< 256);
1215 gdb_assert (used_regs_mask
!= 255);
1217 /* Finally, find a free reg. */
1221 for (i
= 0; i
< 8; ++i
)
1223 if (! (used_regs_mask
& (1 << i
)))
1227 /* We shouldn't get here. */
1228 internal_error (__FILE__
, __LINE__
, _("unable to find free reg"));
1232 /* Extract the details of INSN that we need. */
1235 amd64_get_insn_details (gdb_byte
*insn
, struct amd64_insn
*details
)
1237 gdb_byte
*start
= insn
;
1240 details
->raw_insn
= insn
;
1242 details
->opcode_len
= -1;
1243 details
->rex_offset
= -1;
1244 details
->opcode_offset
= -1;
1245 details
->modrm_offset
= -1;
1247 /* Skip legacy instruction prefixes. */
1248 insn
= amd64_skip_prefixes (insn
);
1250 /* Skip REX instruction prefix. */
1251 if (rex_prefix_p (*insn
))
1253 details
->rex_offset
= insn
- start
;
1257 details
->opcode_offset
= insn
- start
;
1259 if (*insn
== TWO_BYTE_OPCODE_ESCAPE
)
1261 /* Two or three-byte opcode. */
1263 need_modrm
= twobyte_has_modrm
[*insn
];
1265 /* Check for three-byte opcode. */
1275 details
->opcode_len
= 3;
1278 details
->opcode_len
= 2;
1284 /* One-byte opcode. */
1285 need_modrm
= onebyte_has_modrm
[*insn
];
1286 details
->opcode_len
= 1;
1292 details
->modrm_offset
= insn
- start
;
1296 /* Update %rip-relative addressing in INSN.
1298 %rip-relative addressing only uses a 32-bit displacement.
1299 32 bits is not enough to be guaranteed to cover the distance between where
1300 the real instruction is and where its copy is.
1301 Convert the insn to use base+disp addressing.
1302 We set base = pc + insn_length so we can leave disp unchanged. */
1305 fixup_riprel (struct gdbarch
*gdbarch
, struct displaced_step_closure
*dsc
,
1306 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1308 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1309 int modrm_offset
= insn_details
->modrm_offset
;
1310 gdb_byte
*insn
= insn_details
->raw_insn
+ modrm_offset
;
1313 int arch_tmp_regno
, tmp_regno
;
1314 ULONGEST orig_value
;
1316 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1319 /* Compute the rip-relative address. */
1320 insn_length
= gdb_buffered_insn_length (gdbarch
, dsc
->insn_buf
,
1321 dsc
->max_len
, from
);
1322 rip_base
= from
+ insn_length
;
1324 /* We need a register to hold the address.
1325 Pick one not used in the insn.
1326 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1327 arch_tmp_regno
= amd64_get_unused_input_int_reg (insn_details
);
1328 tmp_regno
= amd64_arch_reg_to_regnum (arch_tmp_regno
);
1330 /* REX.B should be unset as we were using rip-relative addressing,
1331 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1332 if (insn_details
->rex_offset
!= -1)
1333 dsc
->insn_buf
[insn_details
->rex_offset
] &= ~REX_B
;
1335 regcache_cooked_read_unsigned (regs
, tmp_regno
, &orig_value
);
1336 dsc
->tmp_regno
= tmp_regno
;
1337 dsc
->tmp_save
= orig_value
;
1340 /* Convert the ModRM field to be base+disp. */
1341 dsc
->insn_buf
[modrm_offset
] &= ~0xc7;
1342 dsc
->insn_buf
[modrm_offset
] |= 0x80 + arch_tmp_regno
;
1344 regcache_cooked_write_unsigned (regs
, tmp_regno
, rip_base
);
1346 if (debug_displaced
)
1347 fprintf_unfiltered (gdb_stdlog
, "displaced: %%rip-relative addressing used.\n"
1348 "displaced: using temp reg %d, old value %s, new value %s\n",
1349 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
),
1350 paddress (gdbarch
, rip_base
));
1354 fixup_displaced_copy (struct gdbarch
*gdbarch
,
1355 struct displaced_step_closure
*dsc
,
1356 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1358 const struct amd64_insn
*details
= &dsc
->insn_details
;
1360 if (details
->modrm_offset
!= -1)
1362 gdb_byte modrm
= details
->raw_insn
[details
->modrm_offset
];
1364 if ((modrm
& 0xc7) == 0x05)
1366 /* The insn uses rip-relative addressing.
1368 fixup_riprel (gdbarch
, dsc
, from
, to
, regs
);
1373 struct displaced_step_closure
*
1374 amd64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1375 CORE_ADDR from
, CORE_ADDR to
,
1376 struct regcache
*regs
)
1378 int len
= gdbarch_max_insn_length (gdbarch
);
1379 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1380 continually watch for running off the end of the buffer. */
1381 int fixup_sentinel_space
= len
;
1382 struct displaced_step_closure
*dsc
1383 = ((struct displaced_step_closure
*)
1384 xmalloc (sizeof (*dsc
) + len
+ fixup_sentinel_space
));
1385 gdb_byte
*buf
= &dsc
->insn_buf
[0];
1386 struct amd64_insn
*details
= &dsc
->insn_details
;
1389 dsc
->max_len
= len
+ fixup_sentinel_space
;
1391 read_memory (from
, buf
, len
);
1393 /* Set up the sentinel space so we don't have to worry about running
1394 off the end of the buffer. An excessive number of leading prefixes
1395 could otherwise cause this. */
1396 memset (buf
+ len
, 0, fixup_sentinel_space
);
1398 amd64_get_insn_details (buf
, details
);
1400 /* GDB may get control back after the insn after the syscall.
1401 Presumably this is a kernel bug.
1402 If this is a syscall, make sure there's a nop afterwards. */
1406 if (amd64_syscall_p (details
, &syscall_length
))
1407 buf
[details
->opcode_offset
+ syscall_length
] = NOP_OPCODE
;
1410 /* Modify the insn to cope with the address where it will be executed from.
1411 In particular, handle any rip-relative addressing. */
1412 fixup_displaced_copy (gdbarch
, dsc
, from
, to
, regs
);
1414 write_memory (to
, buf
, len
);
1416 if (debug_displaced
)
1418 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1419 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1420 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1427 amd64_absolute_jmp_p (const struct amd64_insn
*details
)
1429 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1431 if (insn
[0] == 0xff)
1433 /* jump near, absolute indirect (/4) */
1434 if ((insn
[1] & 0x38) == 0x20)
1437 /* jump far, absolute indirect (/5) */
1438 if ((insn
[1] & 0x38) == 0x28)
1445 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1448 amd64_jmp_p (const struct amd64_insn
*details
)
1450 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1452 /* jump short, relative. */
1453 if (insn
[0] == 0xeb)
1456 /* jump near, relative. */
1457 if (insn
[0] == 0xe9)
1460 return amd64_absolute_jmp_p (details
);
1464 amd64_absolute_call_p (const struct amd64_insn
*details
)
1466 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1468 if (insn
[0] == 0xff)
1470 /* Call near, absolute indirect (/2) */
1471 if ((insn
[1] & 0x38) == 0x10)
1474 /* Call far, absolute indirect (/3) */
1475 if ((insn
[1] & 0x38) == 0x18)
1483 amd64_ret_p (const struct amd64_insn
*details
)
1485 /* NOTE: gcc can emit "repz ; ret". */
1486 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1490 case 0xc2: /* ret near, pop N bytes */
1491 case 0xc3: /* ret near */
1492 case 0xca: /* ret far, pop N bytes */
1493 case 0xcb: /* ret far */
1494 case 0xcf: /* iret */
1503 amd64_call_p (const struct amd64_insn
*details
)
1505 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1507 if (amd64_absolute_call_p (details
))
1510 /* call near, relative */
1511 if (insn
[0] == 0xe8)
1517 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1518 length in bytes. Otherwise, return zero. */
1521 amd64_syscall_p (const struct amd64_insn
*details
, int *lengthp
)
1523 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1525 if (insn
[0] == 0x0f && insn
[1] == 0x05)
1534 /* Classify the instruction at ADDR using PRED.
1535 Throw an error if the memory can't be read. */
1538 amd64_classify_insn_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
1539 int (*pred
) (const struct amd64_insn
*))
1541 struct amd64_insn details
;
1543 int len
, classification
;
1545 len
= gdbarch_max_insn_length (gdbarch
);
1546 buf
= (gdb_byte
*) alloca (len
);
1548 read_code (addr
, buf
, len
);
1549 amd64_get_insn_details (buf
, &details
);
1551 classification
= pred (&details
);
1553 return classification
;
1556 /* The gdbarch insn_is_call method. */
1559 amd64_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1561 return amd64_classify_insn_at (gdbarch
, addr
, amd64_call_p
);
1564 /* The gdbarch insn_is_ret method. */
1567 amd64_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1569 return amd64_classify_insn_at (gdbarch
, addr
, amd64_ret_p
);
1572 /* The gdbarch insn_is_jump method. */
1575 amd64_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1577 return amd64_classify_insn_at (gdbarch
, addr
, amd64_jmp_p
);
1580 /* Fix up the state of registers and memory after having single-stepped
1581 a displaced instruction. */
1584 amd64_displaced_step_fixup (struct gdbarch
*gdbarch
,
1585 struct displaced_step_closure
*dsc
,
1586 CORE_ADDR from
, CORE_ADDR to
,
1587 struct regcache
*regs
)
1589 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1590 /* The offset we applied to the instruction's address. */
1591 ULONGEST insn_offset
= to
- from
;
1592 gdb_byte
*insn
= dsc
->insn_buf
;
1593 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1595 if (debug_displaced
)
1596 fprintf_unfiltered (gdb_stdlog
,
1597 "displaced: fixup (%s, %s), "
1598 "insn = 0x%02x 0x%02x ...\n",
1599 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1602 /* If we used a tmp reg, restore it. */
1606 if (debug_displaced
)
1607 fprintf_unfiltered (gdb_stdlog
, "displaced: restoring reg %d to %s\n",
1608 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
));
1609 regcache_cooked_write_unsigned (regs
, dsc
->tmp_regno
, dsc
->tmp_save
);
1612 /* The list of issues to contend with here is taken from
1613 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1614 Yay for Free Software! */
1616 /* Relocate the %rip back to the program's instruction stream,
1619 /* Except in the case of absolute or indirect jump or call
1620 instructions, or a return instruction, the new rip is relative to
1621 the displaced instruction; make it relative to the original insn.
1622 Well, signal handler returns don't need relocation either, but we use the
1623 value of %rip to recognize those; see below. */
1624 if (! amd64_absolute_jmp_p (insn_details
)
1625 && ! amd64_absolute_call_p (insn_details
)
1626 && ! amd64_ret_p (insn_details
))
1631 regcache_cooked_read_unsigned (regs
, AMD64_RIP_REGNUM
, &orig_rip
);
1633 /* A signal trampoline system call changes the %rip, resuming
1634 execution of the main program after the signal handler has
1635 returned. That makes them like 'return' instructions; we
1636 shouldn't relocate %rip.
1638 But most system calls don't, and we do need to relocate %rip.
1640 Our heuristic for distinguishing these cases: if stepping
1641 over the system call instruction left control directly after
1642 the instruction, the we relocate --- control almost certainly
1643 doesn't belong in the displaced copy. Otherwise, we assume
1644 the instruction has put control where it belongs, and leave
1645 it unrelocated. Goodness help us if there are PC-relative
1647 if (amd64_syscall_p (insn_details
, &insn_len
)
1648 && orig_rip
!= to
+ insn_len
1649 /* GDB can get control back after the insn after the syscall.
1650 Presumably this is a kernel bug.
1651 Fixup ensures its a nop, we add one to the length for it. */
1652 && orig_rip
!= to
+ insn_len
+ 1)
1654 if (debug_displaced
)
1655 fprintf_unfiltered (gdb_stdlog
,
1656 "displaced: syscall changed %%rip; "
1657 "not relocating\n");
1661 ULONGEST rip
= orig_rip
- insn_offset
;
1663 /* If we just stepped over a breakpoint insn, we don't backup
1664 the pc on purpose; this is to match behaviour without
1667 regcache_cooked_write_unsigned (regs
, AMD64_RIP_REGNUM
, rip
);
1669 if (debug_displaced
)
1670 fprintf_unfiltered (gdb_stdlog
,
1672 "relocated %%rip from %s to %s\n",
1673 paddress (gdbarch
, orig_rip
),
1674 paddress (gdbarch
, rip
));
1678 /* If the instruction was PUSHFL, then the TF bit will be set in the
1679 pushed value, and should be cleared. We'll leave this for later,
1680 since GDB already messes up the TF flag when stepping over a
1683 /* If the instruction was a call, the return address now atop the
1684 stack is the address following the copied instruction. We need
1685 to make it the address following the original instruction. */
1686 if (amd64_call_p (insn_details
))
1690 const ULONGEST retaddr_len
= 8;
1692 regcache_cooked_read_unsigned (regs
, AMD64_RSP_REGNUM
, &rsp
);
1693 retaddr
= read_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
);
1694 retaddr
= (retaddr
- insn_offset
) & 0xffffffffffffffffULL
;
1695 write_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
, retaddr
);
1697 if (debug_displaced
)
1698 fprintf_unfiltered (gdb_stdlog
,
1699 "displaced: relocated return addr at %s "
1701 paddress (gdbarch
, rsp
),
1702 paddress (gdbarch
, retaddr
));
1706 /* If the instruction INSN uses RIP-relative addressing, return the
1707 offset into the raw INSN where the displacement to be adjusted is
1708 found. Returns 0 if the instruction doesn't use RIP-relative
1712 rip_relative_offset (struct amd64_insn
*insn
)
1714 if (insn
->modrm_offset
!= -1)
1716 gdb_byte modrm
= insn
->raw_insn
[insn
->modrm_offset
];
1718 if ((modrm
& 0xc7) == 0x05)
1720 /* The displacement is found right after the ModRM byte. */
1721 return insn
->modrm_offset
+ 1;
1729 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
1731 target_write_memory (*to
, buf
, len
);
1736 amd64_relocate_instruction (struct gdbarch
*gdbarch
,
1737 CORE_ADDR
*to
, CORE_ADDR oldloc
)
1739 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1740 int len
= gdbarch_max_insn_length (gdbarch
);
1741 /* Extra space for sentinels. */
1742 int fixup_sentinel_space
= len
;
1743 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
+ fixup_sentinel_space
);
1744 struct amd64_insn insn_details
;
1746 LONGEST rel32
, newrel
;
1750 read_memory (oldloc
, buf
, len
);
1752 /* Set up the sentinel space so we don't have to worry about running
1753 off the end of the buffer. An excessive number of leading prefixes
1754 could otherwise cause this. */
1755 memset (buf
+ len
, 0, fixup_sentinel_space
);
1758 amd64_get_insn_details (insn
, &insn_details
);
1760 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
, len
, oldloc
);
1762 /* Skip legacy instruction prefixes. */
1763 insn
= amd64_skip_prefixes (insn
);
1765 /* Adjust calls with 32-bit relative addresses as push/jump, with
1766 the address pushed being the location where the original call in
1767 the user program would return to. */
1768 if (insn
[0] == 0xe8)
1770 gdb_byte push_buf
[32];
1774 /* Where "ret" in the original code will return to. */
1775 ret_addr
= oldloc
+ insn_length
;
1777 /* If pushing an address higher than or equal to 0x80000000,
1778 avoid 'pushq', as that sign extends its 32-bit operand, which
1779 would be incorrect. */
1780 if (ret_addr
<= 0x7fffffff)
1782 push_buf
[0] = 0x68; /* pushq $... */
1783 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
1788 push_buf
[i
++] = 0x48; /* sub $0x8,%rsp */
1789 push_buf
[i
++] = 0x83;
1790 push_buf
[i
++] = 0xec;
1791 push_buf
[i
++] = 0x08;
1793 push_buf
[i
++] = 0xc7; /* movl $imm,(%rsp) */
1794 push_buf
[i
++] = 0x04;
1795 push_buf
[i
++] = 0x24;
1796 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1797 ret_addr
& 0xffffffff);
1800 push_buf
[i
++] = 0xc7; /* movl $imm,4(%rsp) */
1801 push_buf
[i
++] = 0x44;
1802 push_buf
[i
++] = 0x24;
1803 push_buf
[i
++] = 0x04;
1804 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1808 gdb_assert (i
<= sizeof (push_buf
));
1809 /* Push the push. */
1810 append_insns (to
, i
, push_buf
);
1812 /* Convert the relative call to a relative jump. */
1815 /* Adjust the destination offset. */
1816 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1817 newrel
= (oldloc
- *to
) + rel32
;
1818 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1820 if (debug_displaced
)
1821 fprintf_unfiltered (gdb_stdlog
,
1822 "Adjusted insn rel32=%s at %s to"
1823 " rel32=%s at %s\n",
1824 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1825 hex_string (newrel
), paddress (gdbarch
, *to
));
1827 /* Write the adjusted jump into its displaced location. */
1828 append_insns (to
, 5, insn
);
1832 offset
= rip_relative_offset (&insn_details
);
1835 /* Adjust jumps with 32-bit relative addresses. Calls are
1836 already handled above. */
1837 if (insn
[0] == 0xe9)
1839 /* Adjust conditional jumps. */
1840 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1846 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1847 newrel
= (oldloc
- *to
) + rel32
;
1848 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1849 if (debug_displaced
)
1850 fprintf_unfiltered (gdb_stdlog
,
1851 "Adjusted insn rel32=%s at %s to"
1852 " rel32=%s at %s\n",
1853 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1854 hex_string (newrel
), paddress (gdbarch
, *to
));
1857 /* Write the adjusted instruction into its displaced location. */
1858 append_insns (to
, insn_length
, buf
);
1862 /* The maximum number of saved registers. This should include %rip. */
1863 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1865 struct amd64_frame_cache
1870 CORE_ADDR sp_offset
;
1873 /* Saved registers. */
1874 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
1878 /* Do we have a frame? */
1882 /* Initialize a frame cache. */
1885 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
1892 cache
->sp_offset
= -8;
1895 /* Saved registers. We initialize these to -1 since zero is a valid
1896 offset (that's where %rbp is supposed to be stored).
1897 The values start out as being offsets, and are later converted to
1898 addresses (at which point -1 is interpreted as an address, still meaning
1900 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1901 cache
->saved_regs
[i
] = -1;
1902 cache
->saved_sp
= 0;
1903 cache
->saved_sp_reg
= -1;
1905 /* Frameless until proven otherwise. */
1906 cache
->frameless_p
= 1;
1909 /* Allocate and initialize a frame cache. */
1911 static struct amd64_frame_cache
*
1912 amd64_alloc_frame_cache (void)
1914 struct amd64_frame_cache
*cache
;
1916 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
1917 amd64_init_frame_cache (cache
);
1921 /* GCC 4.4 and later, can put code in the prologue to realign the
1922 stack pointer. Check whether PC points to such code, and update
1923 CACHE accordingly. Return the first instruction after the code
1924 sequence or CURRENT_PC, whichever is smaller. If we don't
1925 recognize the code, return PC. */
1928 amd64_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1929 struct amd64_frame_cache
*cache
)
1931 /* There are 2 code sequences to re-align stack before the frame
1934 1. Use a caller-saved saved register:
1940 2. Use a callee-saved saved register:
1947 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1949 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1950 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1955 int offset
, offset_and
;
1957 if (target_read_code (pc
, buf
, sizeof buf
))
1960 /* Check caller-saved saved register. The first instruction has
1961 to be "leaq 8(%rsp), %reg". */
1962 if ((buf
[0] & 0xfb) == 0x48
1967 /* MOD must be binary 10 and R/M must be binary 100. */
1968 if ((buf
[2] & 0xc7) != 0x44)
1971 /* REG has register number. */
1972 reg
= (buf
[2] >> 3) & 7;
1974 /* Check the REX.R bit. */
1982 /* Check callee-saved saved register. The first instruction
1983 has to be "pushq %reg". */
1985 if ((buf
[0] & 0xf8) == 0x50)
1987 else if ((buf
[0] & 0xf6) == 0x40
1988 && (buf
[1] & 0xf8) == 0x50)
1990 /* Check the REX.B bit. */
1991 if ((buf
[0] & 1) != 0)
2000 reg
+= buf
[offset
] & 0x7;
2004 /* The next instruction has to be "leaq 16(%rsp), %reg". */
2005 if ((buf
[offset
] & 0xfb) != 0x48
2006 || buf
[offset
+ 1] != 0x8d
2007 || buf
[offset
+ 3] != 0x24
2008 || buf
[offset
+ 4] != 0x10)
2011 /* MOD must be binary 10 and R/M must be binary 100. */
2012 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2015 /* REG has register number. */
2016 r
= (buf
[offset
+ 2] >> 3) & 7;
2018 /* Check the REX.R bit. */
2019 if (buf
[offset
] == 0x4c)
2022 /* Registers in pushq and leaq have to be the same. */
2029 /* Rigister can't be %rsp nor %rbp. */
2030 if (reg
== 4 || reg
== 5)
2033 /* The next instruction has to be "andq $-XXX, %rsp". */
2034 if (buf
[offset
] != 0x48
2035 || buf
[offset
+ 2] != 0xe4
2036 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2039 offset_and
= offset
;
2040 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2042 /* The next instruction has to be "pushq -8(%reg)". */
2044 if (buf
[offset
] == 0xff)
2046 else if ((buf
[offset
] & 0xf6) == 0x40
2047 && buf
[offset
+ 1] == 0xff)
2049 /* Check the REX.B bit. */
2050 if ((buf
[offset
] & 0x1) != 0)
2057 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2059 if (buf
[offset
+ 1] != 0xf8
2060 || (buf
[offset
] & 0xf8) != 0x70)
2063 /* R/M has register. */
2064 r
+= buf
[offset
] & 7;
2066 /* Registers in leaq and pushq have to be the same. */
2070 if (current_pc
> pc
+ offset_and
)
2071 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2073 return std::min (pc
+ offset
+ 2, current_pc
);
2076 /* Similar to amd64_analyze_stack_align for x32. */
2079 amd64_x32_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
2080 struct amd64_frame_cache
*cache
)
2082 /* There are 2 code sequences to re-align stack before the frame
2085 1. Use a caller-saved saved register:
2093 [addr32] leal 8(%rsp), %reg
2095 [addr32] pushq -8(%reg)
2097 2. Use a callee-saved saved register:
2107 [addr32] leal 16(%rsp), %reg
2109 [addr32] pushq -8(%reg)
2111 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2113 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2114 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2116 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2118 0x83 0xe4 0xf0 andl $-16, %esp
2119 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2124 int offset
, offset_and
;
2126 if (target_read_memory (pc
, buf
, sizeof buf
))
2129 /* Skip optional addr32 prefix. */
2130 offset
= buf
[0] == 0x67 ? 1 : 0;
2132 /* Check caller-saved saved register. The first instruction has
2133 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2134 if (((buf
[offset
] & 0xfb) == 0x48 || (buf
[offset
] & 0xfb) == 0x40)
2135 && buf
[offset
+ 1] == 0x8d
2136 && buf
[offset
+ 3] == 0x24
2137 && buf
[offset
+ 4] == 0x8)
2139 /* MOD must be binary 10 and R/M must be binary 100. */
2140 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2143 /* REG has register number. */
2144 reg
= (buf
[offset
+ 2] >> 3) & 7;
2146 /* Check the REX.R bit. */
2147 if ((buf
[offset
] & 0x4) != 0)
2154 /* Check callee-saved saved register. The first instruction
2155 has to be "pushq %reg". */
2157 if ((buf
[offset
] & 0xf6) == 0x40
2158 && (buf
[offset
+ 1] & 0xf8) == 0x50)
2160 /* Check the REX.B bit. */
2161 if ((buf
[offset
] & 1) != 0)
2166 else if ((buf
[offset
] & 0xf8) != 0x50)
2170 reg
+= buf
[offset
] & 0x7;
2174 /* Skip optional addr32 prefix. */
2175 if (buf
[offset
] == 0x67)
2178 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2179 "leal 16(%rsp), %reg". */
2180 if (((buf
[offset
] & 0xfb) != 0x48 && (buf
[offset
] & 0xfb) != 0x40)
2181 || buf
[offset
+ 1] != 0x8d
2182 || buf
[offset
+ 3] != 0x24
2183 || buf
[offset
+ 4] != 0x10)
2186 /* MOD must be binary 10 and R/M must be binary 100. */
2187 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2190 /* REG has register number. */
2191 r
= (buf
[offset
+ 2] >> 3) & 7;
2193 /* Check the REX.R bit. */
2194 if ((buf
[offset
] & 0x4) != 0)
2197 /* Registers in pushq and leaq have to be the same. */
2204 /* Rigister can't be %rsp nor %rbp. */
2205 if (reg
== 4 || reg
== 5)
2208 /* The next instruction may be "andq $-XXX, %rsp" or
2209 "andl $-XXX, %esp". */
2210 if (buf
[offset
] != 0x48)
2213 if (buf
[offset
+ 2] != 0xe4
2214 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2217 offset_and
= offset
;
2218 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2220 /* Skip optional addr32 prefix. */
2221 if (buf
[offset
] == 0x67)
2224 /* The next instruction has to be "pushq -8(%reg)". */
2226 if (buf
[offset
] == 0xff)
2228 else if ((buf
[offset
] & 0xf6) == 0x40
2229 && buf
[offset
+ 1] == 0xff)
2231 /* Check the REX.B bit. */
2232 if ((buf
[offset
] & 0x1) != 0)
2239 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2241 if (buf
[offset
+ 1] != 0xf8
2242 || (buf
[offset
] & 0xf8) != 0x70)
2245 /* R/M has register. */
2246 r
+= buf
[offset
] & 7;
2248 /* Registers in leaq and pushq have to be the same. */
2252 if (current_pc
> pc
+ offset_and
)
2253 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2255 return std::min (pc
+ offset
+ 2, current_pc
);
2258 /* Do a limited analysis of the prologue at PC and update CACHE
2259 accordingly. Bail out early if CURRENT_PC is reached. Return the
2260 address where the analysis stopped.
2262 We will handle only functions beginning with:
2265 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2267 or (for the X32 ABI):
2270 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2272 Any function that doesn't start with one of these sequences will be
2273 assumed to have no prologue and thus no valid frame pointer in
2277 amd64_analyze_prologue (struct gdbarch
*gdbarch
,
2278 CORE_ADDR pc
, CORE_ADDR current_pc
,
2279 struct amd64_frame_cache
*cache
)
2281 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2282 /* There are two variations of movq %rsp, %rbp. */
2283 static const gdb_byte mov_rsp_rbp_1
[3] = { 0x48, 0x89, 0xe5 };
2284 static const gdb_byte mov_rsp_rbp_2
[3] = { 0x48, 0x8b, 0xec };
2285 /* Ditto for movl %esp, %ebp. */
2286 static const gdb_byte mov_esp_ebp_1
[2] = { 0x89, 0xe5 };
2287 static const gdb_byte mov_esp_ebp_2
[2] = { 0x8b, 0xec };
2292 if (current_pc
<= pc
)
2295 if (gdbarch_ptr_bit (gdbarch
) == 32)
2296 pc
= amd64_x32_analyze_stack_align (pc
, current_pc
, cache
);
2298 pc
= amd64_analyze_stack_align (pc
, current_pc
, cache
);
2300 op
= read_code_unsigned_integer (pc
, 1, byte_order
);
2302 if (op
== 0x55) /* pushq %rbp */
2304 /* Take into account that we've executed the `pushq %rbp' that
2305 starts this instruction sequence. */
2306 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
2307 cache
->sp_offset
+= 8;
2309 /* If that's all, return now. */
2310 if (current_pc
<= pc
+ 1)
2313 read_code (pc
+ 1, buf
, 3);
2315 /* Check for `movq %rsp, %rbp'. */
2316 if (memcmp (buf
, mov_rsp_rbp_1
, 3) == 0
2317 || memcmp (buf
, mov_rsp_rbp_2
, 3) == 0)
2319 /* OK, we actually have a frame. */
2320 cache
->frameless_p
= 0;
2324 /* For X32, also check for `movq %esp, %ebp'. */
2325 if (gdbarch_ptr_bit (gdbarch
) == 32)
2327 if (memcmp (buf
, mov_esp_ebp_1
, 2) == 0
2328 || memcmp (buf
, mov_esp_ebp_2
, 2) == 0)
2330 /* OK, we actually have a frame. */
2331 cache
->frameless_p
= 0;
2342 /* Work around false termination of prologue - GCC PR debug/48827.
2344 START_PC is the first instruction of a function, PC is its minimal already
2345 determined advanced address. Function returns PC if it has nothing to do.
2349 <-- here is 0 lines advance - the false prologue end marker.
2350 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2351 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2352 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2353 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2354 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2355 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2356 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2357 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2361 amd64_skip_xmm_prologue (CORE_ADDR pc
, CORE_ADDR start_pc
)
2363 struct symtab_and_line start_pc_sal
, next_sal
;
2364 gdb_byte buf
[4 + 8 * 7];
2370 start_pc_sal
= find_pc_sect_line (start_pc
, NULL
, 0);
2371 if (start_pc_sal
.symtab
== NULL
2372 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2373 (SYMTAB_COMPUNIT (start_pc_sal
.symtab
))) < 6
2374 || start_pc_sal
.pc
!= start_pc
|| pc
>= start_pc_sal
.end
)
2377 next_sal
= find_pc_sect_line (start_pc_sal
.end
, NULL
, 0);
2378 if (next_sal
.line
!= start_pc_sal
.line
)
2381 /* START_PC can be from overlayed memory, ignored here. */
2382 if (target_read_code (next_sal
.pc
- 4, buf
, sizeof (buf
)) != 0)
2386 if (buf
[0] != 0x84 || buf
[1] != 0xc0)
2393 for (xmmreg
= 0; xmmreg
< 8; xmmreg
++)
2395 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2396 if (buf
[offset
] != 0x0f || buf
[offset
+ 1] != 0x29
2397 || (buf
[offset
+ 2] & 0x3f) != (xmmreg
<< 3 | 0x5))
2401 if ((buf
[offset
+ 2] & 0xc0) == 0x40)
2403 /* 8-bit displacement. */
2407 else if ((buf
[offset
+ 2] & 0xc0) == 0x80)
2409 /* 32-bit displacement. */
2417 if (offset
- 4 != buf
[3])
2420 return next_sal
.end
;
2423 /* Return PC of first real instruction. */
2426 amd64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2428 struct amd64_frame_cache cache
;
2430 CORE_ADDR func_addr
;
2432 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
2434 CORE_ADDR post_prologue_pc
2435 = skip_prologue_using_sal (gdbarch
, func_addr
);
2436 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
2438 /* Clang always emits a line note before the prologue and another
2439 one after. We trust clang to emit usable line notes. */
2440 if (post_prologue_pc
2442 && COMPUNIT_PRODUCER (cust
) != NULL
2443 && startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
2444 return std::max (start_pc
, post_prologue_pc
);
2447 amd64_init_frame_cache (&cache
);
2448 pc
= amd64_analyze_prologue (gdbarch
, start_pc
, 0xffffffffffffffffLL
,
2450 if (cache
.frameless_p
)
2453 return amd64_skip_xmm_prologue (pc
, start_pc
);
2457 /* Normal frames. */
2460 amd64_frame_cache_1 (struct frame_info
*this_frame
,
2461 struct amd64_frame_cache
*cache
)
2463 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2464 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2468 cache
->pc
= get_frame_func (this_frame
);
2470 amd64_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2473 if (cache
->frameless_p
)
2475 /* We didn't find a valid frame. If we're at the start of a
2476 function, or somewhere half-way its prologue, the function's
2477 frame probably hasn't been fully setup yet. Try to
2478 reconstruct the base address for the stack frame by looking
2479 at the stack pointer. For truly "frameless" functions this
2482 if (cache
->saved_sp_reg
!= -1)
2484 /* Stack pointer has been saved. */
2485 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2486 cache
->saved_sp
= extract_unsigned_integer (buf
, 8, byte_order
);
2488 /* We're halfway aligning the stack. */
2489 cache
->base
= ((cache
->saved_sp
- 8) & 0xfffffffffffffff0LL
) - 8;
2490 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->saved_sp
- 8;
2492 /* This will be added back below. */
2493 cache
->saved_regs
[AMD64_RIP_REGNUM
] -= cache
->base
;
2497 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2498 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
)
2504 get_frame_register (this_frame
, AMD64_RBP_REGNUM
, buf
);
2505 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
);
2508 /* Now that we have the base address for the stack frame we can
2509 calculate the value of %rsp in the calling frame. */
2510 cache
->saved_sp
= cache
->base
+ 16;
2512 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2513 frame we find it at the same offset from the reconstructed base
2514 address. If we're halfway aligning the stack, %rip is handled
2515 differently (see above). */
2516 if (!cache
->frameless_p
|| cache
->saved_sp_reg
== -1)
2517 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
2519 /* Adjust all the saved registers such that they contain addresses
2520 instead of offsets. */
2521 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
2522 if (cache
->saved_regs
[i
] != -1)
2523 cache
->saved_regs
[i
] += cache
->base
;
2528 static struct amd64_frame_cache
*
2529 amd64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2531 struct amd64_frame_cache
*cache
;
2534 return (struct amd64_frame_cache
*) *this_cache
;
2536 cache
= amd64_alloc_frame_cache ();
2537 *this_cache
= cache
;
2541 amd64_frame_cache_1 (this_frame
, cache
);
2543 CATCH (ex
, RETURN_MASK_ERROR
)
2545 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2546 throw_exception (ex
);
2553 static enum unwind_stop_reason
2554 amd64_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2557 struct amd64_frame_cache
*cache
=
2558 amd64_frame_cache (this_frame
, this_cache
);
2561 return UNWIND_UNAVAILABLE
;
2563 /* This marks the outermost frame. */
2564 if (cache
->base
== 0)
2565 return UNWIND_OUTERMOST
;
2567 return UNWIND_NO_REASON
;
2571 amd64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2572 struct frame_id
*this_id
)
2574 struct amd64_frame_cache
*cache
=
2575 amd64_frame_cache (this_frame
, this_cache
);
2578 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2579 else if (cache
->base
== 0)
2581 /* This marks the outermost frame. */
2585 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
2588 static struct value
*
2589 amd64_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2592 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2593 struct amd64_frame_cache
*cache
=
2594 amd64_frame_cache (this_frame
, this_cache
);
2596 gdb_assert (regnum
>= 0);
2598 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2599 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2601 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2602 return frame_unwind_got_memory (this_frame
, regnum
,
2603 cache
->saved_regs
[regnum
]);
2605 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2608 static const struct frame_unwind amd64_frame_unwind
=
2611 amd64_frame_unwind_stop_reason
,
2612 amd64_frame_this_id
,
2613 amd64_frame_prev_register
,
2615 default_frame_sniffer
2618 /* Generate a bytecode expression to get the value of the saved PC. */
2621 amd64_gen_return_address (struct gdbarch
*gdbarch
,
2622 struct agent_expr
*ax
, struct axs_value
*value
,
2625 /* The following sequence assumes the traditional use of the base
2627 ax_reg (ax
, AMD64_RBP_REGNUM
);
2629 ax_simple (ax
, aop_add
);
2630 value
->type
= register_type (gdbarch
, AMD64_RIP_REGNUM
);
2631 value
->kind
= axs_lvalue_memory
;
2635 /* Signal trampolines. */
2637 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2638 64-bit variants. This would require using identical frame caches
2639 on both platforms. */
2641 static struct amd64_frame_cache
*
2642 amd64_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2644 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2645 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2646 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2647 struct amd64_frame_cache
*cache
;
2653 return (struct amd64_frame_cache
*) *this_cache
;
2655 cache
= amd64_alloc_frame_cache ();
2659 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2660 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
) - 8;
2662 addr
= tdep
->sigcontext_addr (this_frame
);
2663 gdb_assert (tdep
->sc_reg_offset
);
2664 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
2665 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2666 if (tdep
->sc_reg_offset
[i
] != -1)
2667 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2671 CATCH (ex
, RETURN_MASK_ERROR
)
2673 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2674 throw_exception (ex
);
2678 *this_cache
= cache
;
2682 static enum unwind_stop_reason
2683 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2686 struct amd64_frame_cache
*cache
=
2687 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2690 return UNWIND_UNAVAILABLE
;
2692 return UNWIND_NO_REASON
;
2696 amd64_sigtramp_frame_this_id (struct frame_info
*this_frame
,
2697 void **this_cache
, struct frame_id
*this_id
)
2699 struct amd64_frame_cache
*cache
=
2700 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2703 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2704 else if (cache
->base
== 0)
2706 /* This marks the outermost frame. */
2710 (*this_id
) = frame_id_build (cache
->base
+ 16, get_frame_pc (this_frame
));
2713 static struct value
*
2714 amd64_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2715 void **this_cache
, int regnum
)
2717 /* Make sure we've initialized the cache. */
2718 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2720 return amd64_frame_prev_register (this_frame
, this_cache
, regnum
);
2724 amd64_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2725 struct frame_info
*this_frame
,
2728 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2730 /* We shouldn't even bother if we don't have a sigcontext_addr
2732 if (tdep
->sigcontext_addr
== NULL
)
2735 if (tdep
->sigtramp_p
!= NULL
)
2737 if (tdep
->sigtramp_p (this_frame
))
2741 if (tdep
->sigtramp_start
!= 0)
2743 CORE_ADDR pc
= get_frame_pc (this_frame
);
2745 gdb_assert (tdep
->sigtramp_end
!= 0);
2746 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2753 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
2756 amd64_sigtramp_frame_unwind_stop_reason
,
2757 amd64_sigtramp_frame_this_id
,
2758 amd64_sigtramp_frame_prev_register
,
2760 amd64_sigtramp_frame_sniffer
2765 amd64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2767 struct amd64_frame_cache
*cache
=
2768 amd64_frame_cache (this_frame
, this_cache
);
2773 static const struct frame_base amd64_frame_base
=
2775 &amd64_frame_unwind
,
2776 amd64_frame_base_address
,
2777 amd64_frame_base_address
,
2778 amd64_frame_base_address
2781 /* Normal frames, but in a function epilogue. */
2783 /* Implement the stack_frame_destroyed_p gdbarch method.
2785 The epilogue is defined here as the 'ret' instruction, which will
2786 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2787 the function's stack frame. */
2790 amd64_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2793 struct compunit_symtab
*cust
;
2795 cust
= find_pc_compunit_symtab (pc
);
2796 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2799 if (target_read_memory (pc
, &insn
, 1))
2800 return 0; /* Can't read memory at pc. */
2802 if (insn
!= 0xc3) /* 'ret' instruction. */
2809 amd64_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2810 struct frame_info
*this_frame
,
2811 void **this_prologue_cache
)
2813 if (frame_relative_level (this_frame
) == 0)
2814 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2815 get_frame_pc (this_frame
));
2820 static struct amd64_frame_cache
*
2821 amd64_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2823 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2824 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2825 struct amd64_frame_cache
*cache
;
2829 return (struct amd64_frame_cache
*) *this_cache
;
2831 cache
= amd64_alloc_frame_cache ();
2832 *this_cache
= cache
;
2836 /* Cache base will be %esp plus cache->sp_offset (-8). */
2837 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2838 cache
->base
= extract_unsigned_integer (buf
, 8,
2839 byte_order
) + cache
->sp_offset
;
2841 /* Cache pc will be the frame func. */
2842 cache
->pc
= get_frame_pc (this_frame
);
2844 /* The saved %esp will be at cache->base plus 16. */
2845 cache
->saved_sp
= cache
->base
+ 16;
2847 /* The saved %eip will be at cache->base plus 8. */
2848 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->base
+ 8;
2852 CATCH (ex
, RETURN_MASK_ERROR
)
2854 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2855 throw_exception (ex
);
2862 static enum unwind_stop_reason
2863 amd64_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2866 struct amd64_frame_cache
*cache
2867 = amd64_epilogue_frame_cache (this_frame
, this_cache
);
2870 return UNWIND_UNAVAILABLE
;
2872 return UNWIND_NO_REASON
;
2876 amd64_epilogue_frame_this_id (struct frame_info
*this_frame
,
2878 struct frame_id
*this_id
)
2880 struct amd64_frame_cache
*cache
= amd64_epilogue_frame_cache (this_frame
,
2884 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2886 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2889 static const struct frame_unwind amd64_epilogue_frame_unwind
=
2892 amd64_epilogue_frame_unwind_stop_reason
,
2893 amd64_epilogue_frame_this_id
,
2894 amd64_frame_prev_register
,
2896 amd64_epilogue_frame_sniffer
2899 static struct frame_id
2900 amd64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2904 fp
= get_frame_register_unsigned (this_frame
, AMD64_RBP_REGNUM
);
2906 return frame_id_build (fp
+ 16, get_frame_pc (this_frame
));
2909 /* 16 byte align the SP per frame requirements. */
2912 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2914 return sp
& -(CORE_ADDR
)16;
2918 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2919 in the floating-point register set REGSET to register cache
2920 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2923 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2924 int regnum
, const void *fpregs
, size_t len
)
2926 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2927 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2929 gdb_assert (len
>= tdep
->sizeof_fpregset
);
2930 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
2933 /* Collect register REGNUM from the register cache REGCACHE and store
2934 it in the buffer specified by FPREGS and LEN as described by the
2935 floating-point register set REGSET. If REGNUM is -1, do this for
2936 all registers in REGSET. */
2939 amd64_collect_fpregset (const struct regset
*regset
,
2940 const struct regcache
*regcache
,
2941 int regnum
, void *fpregs
, size_t len
)
2943 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2944 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2946 gdb_assert (len
>= tdep
->sizeof_fpregset
);
2947 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
2950 const struct regset amd64_fpregset
=
2952 NULL
, amd64_supply_fpregset
, amd64_collect_fpregset
2956 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2957 %rdi. We expect its value to be a pointer to the jmp_buf structure
2958 from which we extract the address that we will land at. This
2959 address is copied into PC. This routine returns non-zero on
2963 amd64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2967 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2968 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2969 int len
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_func_ptr
);
2971 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2972 longjmp will land. */
2973 if (jb_pc_offset
== -1)
2976 get_frame_register (frame
, AMD64_RDI_REGNUM
, buf
);
2977 jb_addr
= extract_typed_address
2978 (buf
, builtin_type (gdbarch
)->builtin_data_ptr
);
2979 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, len
))
2982 *pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
2987 static const int amd64_record_regmap
[] =
2989 AMD64_RAX_REGNUM
, AMD64_RCX_REGNUM
, AMD64_RDX_REGNUM
, AMD64_RBX_REGNUM
,
2990 AMD64_RSP_REGNUM
, AMD64_RBP_REGNUM
, AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
2991 AMD64_R8_REGNUM
, AMD64_R9_REGNUM
, AMD64_R10_REGNUM
, AMD64_R11_REGNUM
,
2992 AMD64_R12_REGNUM
, AMD64_R13_REGNUM
, AMD64_R14_REGNUM
, AMD64_R15_REGNUM
,
2993 AMD64_RIP_REGNUM
, AMD64_EFLAGS_REGNUM
, AMD64_CS_REGNUM
, AMD64_SS_REGNUM
,
2994 AMD64_DS_REGNUM
, AMD64_ES_REGNUM
, AMD64_FS_REGNUM
, AMD64_GS_REGNUM
2998 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
,
2999 const target_desc
*default_tdesc
)
3001 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3002 const struct target_desc
*tdesc
= info
.target_desc
;
3003 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
3004 static const char *const stap_register_prefixes
[] = { "%", NULL
};
3005 static const char *const stap_register_indirection_prefixes
[] = { "(",
3007 static const char *const stap_register_indirection_suffixes
[] = { ")",
3010 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
3011 floating-point registers. */
3012 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
3013 tdep
->fpregset
= &amd64_fpregset
;
3015 if (! tdesc_has_registers (tdesc
))
3016 tdesc
= default_tdesc
;
3017 tdep
->tdesc
= tdesc
;
3019 tdep
->num_core_regs
= AMD64_NUM_GREGS
+ I387_NUM_REGS
;
3020 tdep
->register_names
= amd64_register_names
;
3022 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512") != NULL
)
3024 tdep
->zmmh_register_names
= amd64_zmmh_names
;
3025 tdep
->k_register_names
= amd64_k_names
;
3026 tdep
->xmm_avx512_register_names
= amd64_xmm_avx512_names
;
3027 tdep
->ymm16h_register_names
= amd64_ymmh_avx512_names
;
3029 tdep
->num_zmm_regs
= 32;
3030 tdep
->num_xmm_avx512_regs
= 16;
3031 tdep
->num_ymm_avx512_regs
= 16;
3033 tdep
->zmm0h_regnum
= AMD64_ZMM0H_REGNUM
;
3034 tdep
->k0_regnum
= AMD64_K0_REGNUM
;
3035 tdep
->xmm16_regnum
= AMD64_XMM16_REGNUM
;
3036 tdep
->ymm16h_regnum
= AMD64_YMM16H_REGNUM
;
3039 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx") != NULL
)
3041 tdep
->ymmh_register_names
= amd64_ymmh_names
;
3042 tdep
->num_ymm_regs
= 16;
3043 tdep
->ymm0h_regnum
= AMD64_YMM0H_REGNUM
;
3046 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
)
3048 tdep
->mpx_register_names
= amd64_mpx_names
;
3049 tdep
->bndcfgu_regnum
= AMD64_BNDCFGU_REGNUM
;
3050 tdep
->bnd0r_regnum
= AMD64_BND0R_REGNUM
;
3053 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.segments") != NULL
)
3055 const struct tdesc_feature
*feature
=
3056 tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.segments");
3057 struct tdesc_arch_data
*tdesc_data_segments
=
3058 (struct tdesc_arch_data
*) info
.tdep_info
;
3060 tdesc_numbered_register (feature
, tdesc_data_segments
,
3061 AMD64_FSBASE_REGNUM
, "fs_base");
3062 tdesc_numbered_register (feature
, tdesc_data_segments
,
3063 AMD64_GSBASE_REGNUM
, "gs_base");
3066 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.pkeys") != NULL
)
3068 tdep
->pkeys_register_names
= amd64_pkeys_names
;
3069 tdep
->pkru_regnum
= AMD64_PKRU_REGNUM
;
3070 tdep
->num_pkeys_regs
= 1;
3073 tdep
->num_byte_regs
= 20;
3074 tdep
->num_word_regs
= 16;
3075 tdep
->num_dword_regs
= 16;
3076 /* Avoid wiring in the MMX registers for now. */
3077 tdep
->num_mmx_regs
= 0;
3079 set_gdbarch_pseudo_register_read_value (gdbarch
,
3080 amd64_pseudo_register_read_value
);
3081 set_gdbarch_pseudo_register_write (gdbarch
,
3082 amd64_pseudo_register_write
);
3083 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
3084 amd64_ax_pseudo_register_collect
);
3086 set_tdesc_pseudo_register_name (gdbarch
, amd64_pseudo_register_name
);
3088 /* AMD64 has an FPU and 16 SSE registers. */
3089 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
3090 tdep
->num_xmm_regs
= 16;
3092 /* This is what all the fuss is about. */
3093 set_gdbarch_long_bit (gdbarch
, 64);
3094 set_gdbarch_long_long_bit (gdbarch
, 64);
3095 set_gdbarch_ptr_bit (gdbarch
, 64);
3097 /* In contrast to the i386, on AMD64 a `long double' actually takes
3098 up 128 bits, even though it's still based on the i387 extended
3099 floating-point format which has only 80 significant bits. */
3100 set_gdbarch_long_double_bit (gdbarch
, 128);
3102 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
3104 /* Register numbers of various important registers. */
3105 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
3106 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
3107 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
3108 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
3110 /* The "default" register numbering scheme for AMD64 is referred to
3111 as the "DWARF Register Number Mapping" in the System V psABI.
3112 The preferred debugging format for all known AMD64 targets is
3113 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3114 DWARF-1), but we provide the same mapping just in case. This
3115 mapping is also used for stabs, which GCC does support. */
3116 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3117 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3119 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
3120 be in use on any of the supported AMD64 targets. */
3122 /* Call dummy code. */
3123 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
3124 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
3125 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
3127 set_gdbarch_convert_register_p (gdbarch
, i387_convert_register_p
);
3128 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
3129 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
3131 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
3133 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
3135 tdep
->record_regmap
= amd64_record_regmap
;
3137 set_gdbarch_dummy_id (gdbarch
, amd64_dummy_id
);
3139 /* Hook the function epilogue frame unwinder. This unwinder is
3140 appended to the list first, so that it supercedes the other
3141 unwinders in function epilogues. */
3142 frame_unwind_prepend_unwinder (gdbarch
, &amd64_epilogue_frame_unwind
);
3144 /* Hook the prologue-based frame unwinders. */
3145 frame_unwind_append_unwinder (gdbarch
, &amd64_sigtramp_frame_unwind
);
3146 frame_unwind_append_unwinder (gdbarch
, &amd64_frame_unwind
);
3147 frame_base_set_default (gdbarch
, &amd64_frame_base
);
3149 set_gdbarch_get_longjmp_target (gdbarch
, amd64_get_longjmp_target
);
3151 set_gdbarch_relocate_instruction (gdbarch
, amd64_relocate_instruction
);
3153 set_gdbarch_gen_return_address (gdbarch
, amd64_gen_return_address
);
3155 /* SystemTap variables and functions. */
3156 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
3157 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
3158 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
3159 stap_register_indirection_prefixes
);
3160 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
3161 stap_register_indirection_suffixes
);
3162 set_gdbarch_stap_is_single_operand (gdbarch
,
3163 i386_stap_is_single_operand
);
3164 set_gdbarch_stap_parse_special_token (gdbarch
,
3165 i386_stap_parse_special_token
);
3166 set_gdbarch_insn_is_call (gdbarch
, amd64_insn_is_call
);
3167 set_gdbarch_insn_is_ret (gdbarch
, amd64_insn_is_ret
);
3168 set_gdbarch_insn_is_jump (gdbarch
, amd64_insn_is_jump
);
3172 static struct type
*
3173 amd64_x32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3175 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3177 switch (regnum
- tdep
->eax_regnum
)
3179 case AMD64_RBP_REGNUM
: /* %ebp */
3180 case AMD64_RSP_REGNUM
: /* %esp */
3181 return builtin_type (gdbarch
)->builtin_data_ptr
;
3182 case AMD64_RIP_REGNUM
: /* %eip */
3183 return builtin_type (gdbarch
)->builtin_func_ptr
;
3186 return i386_pseudo_register_type (gdbarch
, regnum
);
3190 amd64_x32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
,
3191 const target_desc
*default_tdesc
)
3193 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3195 amd64_init_abi (info
, gdbarch
, default_tdesc
);
3197 tdep
->num_dword_regs
= 17;
3198 set_tdesc_pseudo_register_type (gdbarch
, amd64_x32_pseudo_register_type
);
3200 set_gdbarch_long_bit (gdbarch
, 32);
3201 set_gdbarch_ptr_bit (gdbarch
, 32);
3204 /* Return the target description for a specified XSAVE feature mask. */
3206 const struct target_desc
*
3207 amd64_target_description (uint64_t xcr0
)
3209 static target_desc
*amd64_tdescs \
3210 [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/] = {};
3211 target_desc
**tdesc
;
3213 tdesc
= &amd64_tdescs
[(xcr0
& X86_XSTATE_AVX
) ? 1 : 0]
3214 [(xcr0
& X86_XSTATE_MPX
) ? 1 : 0]
3215 [(xcr0
& X86_XSTATE_AVX512
) ? 1 : 0]
3216 [(xcr0
& X86_XSTATE_PKRU
) ? 1 : 0];
3219 *tdesc
= amd64_create_target_description (xcr0
, false, false);
3224 /* Provide a prototype to silence -Wmissing-prototypes. */
3225 void _initialize_amd64_tdep (void);
3228 _initialize_amd64_tdep (void)
3236 { "i386/amd64.xml", X86_XSTATE_SSE_MASK
},
3237 { "i386/amd64-avx.xml", X86_XSTATE_AVX_MASK
},
3238 { "i386/amd64-mpx.xml", X86_XSTATE_MPX_MASK
},
3239 { "i386/amd64-avx-mpx.xml", X86_XSTATE_AVX_MPX_MASK
},
3240 { "i386/amd64-avx-avx512.xml", X86_XSTATE_AVX_AVX512_MASK
},
3241 { "i386/amd64-avx-mpx-avx512-pku.xml",
3242 X86_XSTATE_AVX_MPX_AVX512_PKU_MASK
},
3245 for (auto &a
: xml_masks
)
3247 auto tdesc
= amd64_target_description (a
.mask
);
3249 selftests::record_xml_tdesc (a
.xml
, tdesc
);
3251 #endif /* GDB_SELF_TEST */
3255 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3256 sense that the instruction pointer and data pointer are simply
3257 64-bit offsets into the code segment and the data segment instead
3258 of a selector offset pair. The functions below store the upper 32
3259 bits of these pointers (instead of just the 16-bits of the segment
3262 /* Fill register REGNUM in REGCACHE with the appropriate
3263 floating-point or SSE register value from *FXSAVE. If REGNUM is
3264 -1, do this for all registers. This function masks off any of the
3265 reserved bits in *FXSAVE. */
3268 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
3271 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3272 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3274 i387_supply_fxsave (regcache
, regnum
, fxsave
);
3277 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3279 const gdb_byte
*regs
= (const gdb_byte
*) fxsave
;
3281 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3282 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
3283 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3284 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3288 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3291 amd64_supply_xsave (struct regcache
*regcache
, int regnum
,
3294 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3295 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3297 i387_supply_xsave (regcache
, regnum
, xsave
);
3300 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3302 const gdb_byte
*regs
= (const gdb_byte
*) xsave
;
3304 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3305 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
),
3307 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3308 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
),
3313 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3314 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3315 all registers. This function doesn't touch any of the reserved
3319 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
3322 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3323 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3324 gdb_byte
*regs
= (gdb_byte
*) fxsave
;
3326 i387_collect_fxsave (regcache
, regnum
, fxsave
);
3328 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3330 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3331 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
3332 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3333 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3337 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3340 amd64_collect_xsave (const struct regcache
*regcache
, int regnum
,
3341 void *xsave
, int gcore
)
3343 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3344 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3345 gdb_byte
*regs
= (gdb_byte
*) xsave
;
3347 i387_collect_xsave (regcache
, regnum
, xsave
, gcore
);
3349 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3351 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3352 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
),
3354 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3355 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
),