1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2015 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
42 #include "x86-xstate.h"
44 #include "features/i386/amd64.c"
45 #include "features/i386/amd64-avx.c"
46 #include "features/i386/amd64-mpx.c"
47 #include "features/i386/amd64-avx512.c"
49 #include "features/i386/x32.c"
50 #include "features/i386/x32-avx.c"
51 #include "features/i386/x32-avx512.c"
56 /* Note that the AMD64 architecture was previously known as x86-64.
57 The latter is (forever) engraved into the canonical system name as
58 returned by config.guess, and used as the name for the AMD64 port
59 of GNU/Linux. The BSD's have renamed their ports to amd64; they
60 don't like to shout. For GDB we prefer the amd64_-prefix over the
61 x86_64_-prefix since it's so much easier to type. */
63 /* Register information. */
65 static const char *amd64_register_names
[] =
67 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
69 /* %r8 is indeed register number 8. */
70 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
71 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
73 /* %st0 is register number 24. */
74 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
75 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
77 /* %xmm0 is register number 40. */
78 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
79 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
83 static const char *amd64_ymm_names
[] =
85 "ymm0", "ymm1", "ymm2", "ymm3",
86 "ymm4", "ymm5", "ymm6", "ymm7",
87 "ymm8", "ymm9", "ymm10", "ymm11",
88 "ymm12", "ymm13", "ymm14", "ymm15"
91 static const char *amd64_ymm_avx512_names
[] =
93 "ymm16", "ymm17", "ymm18", "ymm19",
94 "ymm20", "ymm21", "ymm22", "ymm23",
95 "ymm24", "ymm25", "ymm26", "ymm27",
96 "ymm28", "ymm29", "ymm30", "ymm31"
99 static const char *amd64_ymmh_names
[] =
101 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
102 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
103 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
104 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
107 static const char *amd64_ymmh_avx512_names
[] =
109 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
110 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
111 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
112 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
115 static const char *amd64_mpx_names
[] =
117 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
120 static const char *amd64_k_names
[] =
122 "k0", "k1", "k2", "k3",
123 "k4", "k5", "k6", "k7"
126 static const char *amd64_zmmh_names
[] =
128 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
129 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
130 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
131 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
132 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
133 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
134 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
135 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
138 static const char *amd64_zmm_names
[] =
140 "zmm0", "zmm1", "zmm2", "zmm3",
141 "zmm4", "zmm5", "zmm6", "zmm7",
142 "zmm8", "zmm9", "zmm10", "zmm11",
143 "zmm12", "zmm13", "zmm14", "zmm15",
144 "zmm16", "zmm17", "zmm18", "zmm19",
145 "zmm20", "zmm21", "zmm22", "zmm23",
146 "zmm24", "zmm25", "zmm26", "zmm27",
147 "zmm28", "zmm29", "zmm30", "zmm31"
150 static const char *amd64_xmm_avx512_names
[] = {
151 "xmm16", "xmm17", "xmm18", "xmm19",
152 "xmm20", "xmm21", "xmm22", "xmm23",
153 "xmm24", "xmm25", "xmm26", "xmm27",
154 "xmm28", "xmm29", "xmm30", "xmm31"
157 /* DWARF Register Number Mapping as defined in the System V psABI,
160 static int amd64_dwarf_regmap
[] =
162 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
163 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
164 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
165 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
167 /* Frame Pointer Register RBP. */
170 /* Stack Pointer Register RSP. */
173 /* Extended Integer Registers 8 - 15. */
174 AMD64_R8_REGNUM
, /* %r8 */
175 AMD64_R9_REGNUM
, /* %r9 */
176 AMD64_R10_REGNUM
, /* %r10 */
177 AMD64_R11_REGNUM
, /* %r11 */
178 AMD64_R12_REGNUM
, /* %r12 */
179 AMD64_R13_REGNUM
, /* %r13 */
180 AMD64_R14_REGNUM
, /* %r14 */
181 AMD64_R15_REGNUM
, /* %r15 */
183 /* Return Address RA. Mapped to RIP. */
186 /* SSE Registers 0 - 7. */
187 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
188 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
189 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
190 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
192 /* Extended SSE Registers 8 - 15. */
193 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
194 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
195 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
196 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
198 /* Floating Point Registers 0-7. */
199 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
200 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
201 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
202 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
204 /* MMX Registers 0 - 7.
205 We have to handle those registers specifically, as their register
206 number within GDB depends on the target (or they may even not be
207 available at all). */
208 -1, -1, -1, -1, -1, -1, -1, -1,
210 /* Control and Status Flags Register. */
213 /* Selector Registers. */
223 /* Segment Base Address Registers. */
229 /* Special Selector Registers. */
233 /* Floating Point Control Registers. */
239 static const int amd64_dwarf_regmap_len
=
240 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
242 /* Convert DWARF register number REG to the appropriate register
243 number used by GDB. */
246 amd64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
248 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
249 int ymm0_regnum
= tdep
->ymm0_regnum
;
252 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
253 regnum
= amd64_dwarf_regmap
[reg
];
256 warning (_("Unmapped DWARF Register #%d encountered."), reg
);
257 else if (ymm0_regnum
>= 0
258 && i386_xmm_regnum_p (gdbarch
, regnum
))
259 regnum
+= ymm0_regnum
- I387_XMM0_REGNUM (tdep
);
264 /* Map architectural register numbers to gdb register numbers. */
266 static const int amd64_arch_regmap
[16] =
268 AMD64_RAX_REGNUM
, /* %rax */
269 AMD64_RCX_REGNUM
, /* %rcx */
270 AMD64_RDX_REGNUM
, /* %rdx */
271 AMD64_RBX_REGNUM
, /* %rbx */
272 AMD64_RSP_REGNUM
, /* %rsp */
273 AMD64_RBP_REGNUM
, /* %rbp */
274 AMD64_RSI_REGNUM
, /* %rsi */
275 AMD64_RDI_REGNUM
, /* %rdi */
276 AMD64_R8_REGNUM
, /* %r8 */
277 AMD64_R9_REGNUM
, /* %r9 */
278 AMD64_R10_REGNUM
, /* %r10 */
279 AMD64_R11_REGNUM
, /* %r11 */
280 AMD64_R12_REGNUM
, /* %r12 */
281 AMD64_R13_REGNUM
, /* %r13 */
282 AMD64_R14_REGNUM
, /* %r14 */
283 AMD64_R15_REGNUM
/* %r15 */
286 static const int amd64_arch_regmap_len
=
287 (sizeof (amd64_arch_regmap
) / sizeof (amd64_arch_regmap
[0]));
289 /* Convert architectural register number REG to the appropriate register
290 number used by GDB. */
293 amd64_arch_reg_to_regnum (int reg
)
295 gdb_assert (reg
>= 0 && reg
< amd64_arch_regmap_len
);
297 return amd64_arch_regmap
[reg
];
300 /* Register names for byte pseudo-registers. */
302 static const char *amd64_byte_names
[] =
304 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
305 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
306 "ah", "bh", "ch", "dh"
309 /* Number of lower byte registers. */
310 #define AMD64_NUM_LOWER_BYTE_REGS 16
312 /* Register names for word pseudo-registers. */
314 static const char *amd64_word_names
[] =
316 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
317 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
320 /* Register names for dword pseudo-registers. */
322 static const char *amd64_dword_names
[] =
324 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
325 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
329 /* Return the name of register REGNUM. */
332 amd64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
334 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
335 if (i386_byte_regnum_p (gdbarch
, regnum
))
336 return amd64_byte_names
[regnum
- tdep
->al_regnum
];
337 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
338 return amd64_zmm_names
[regnum
- tdep
->zmm0_regnum
];
339 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
340 return amd64_ymm_names
[regnum
- tdep
->ymm0_regnum
];
341 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
342 return amd64_ymm_avx512_names
[regnum
- tdep
->ymm16_regnum
];
343 else if (i386_word_regnum_p (gdbarch
, regnum
))
344 return amd64_word_names
[regnum
- tdep
->ax_regnum
];
345 else if (i386_dword_regnum_p (gdbarch
, regnum
))
346 return amd64_dword_names
[regnum
- tdep
->eax_regnum
];
348 return i386_pseudo_register_name (gdbarch
, regnum
);
351 static struct value
*
352 amd64_pseudo_register_read_value (struct gdbarch
*gdbarch
,
353 struct regcache
*regcache
,
356 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
357 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
358 enum register_status status
;
359 struct value
*result_value
;
362 result_value
= allocate_value (register_type (gdbarch
, regnum
));
363 VALUE_LVAL (result_value
) = lval_register
;
364 VALUE_REGNUM (result_value
) = regnum
;
365 buf
= value_contents_raw (result_value
);
367 if (i386_byte_regnum_p (gdbarch
, regnum
))
369 int gpnum
= regnum
- tdep
->al_regnum
;
371 /* Extract (always little endian). */
372 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
374 /* Special handling for AH, BH, CH, DH. */
375 status
= regcache_raw_read (regcache
,
376 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
,
378 if (status
== REG_VALID
)
379 memcpy (buf
, raw_buf
+ 1, 1);
381 mark_value_bytes_unavailable (result_value
, 0,
382 TYPE_LENGTH (value_type (result_value
)));
386 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
387 if (status
== REG_VALID
)
388 memcpy (buf
, raw_buf
, 1);
390 mark_value_bytes_unavailable (result_value
, 0,
391 TYPE_LENGTH (value_type (result_value
)));
394 else if (i386_dword_regnum_p (gdbarch
, regnum
))
396 int gpnum
= regnum
- tdep
->eax_regnum
;
397 /* Extract (always little endian). */
398 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
399 if (status
== REG_VALID
)
400 memcpy (buf
, raw_buf
, 4);
402 mark_value_bytes_unavailable (result_value
, 0,
403 TYPE_LENGTH (value_type (result_value
)));
406 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
,
413 amd64_pseudo_register_write (struct gdbarch
*gdbarch
,
414 struct regcache
*regcache
,
415 int regnum
, const gdb_byte
*buf
)
417 gdb_byte raw_buf
[MAX_REGISTER_SIZE
];
418 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
420 if (i386_byte_regnum_p (gdbarch
, regnum
))
422 int gpnum
= regnum
- tdep
->al_regnum
;
424 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
426 /* Read ... AH, BH, CH, DH. */
427 regcache_raw_read (regcache
,
428 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
429 /* ... Modify ... (always little endian). */
430 memcpy (raw_buf
+ 1, buf
, 1);
432 regcache_raw_write (regcache
,
433 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
438 regcache_raw_read (regcache
, gpnum
, raw_buf
);
439 /* ... Modify ... (always little endian). */
440 memcpy (raw_buf
, buf
, 1);
442 regcache_raw_write (regcache
, gpnum
, raw_buf
);
445 else if (i386_dword_regnum_p (gdbarch
, regnum
))
447 int gpnum
= regnum
- tdep
->eax_regnum
;
450 regcache_raw_read (regcache
, gpnum
, raw_buf
);
451 /* ... Modify ... (always little endian). */
452 memcpy (raw_buf
, buf
, 4);
454 regcache_raw_write (regcache
, gpnum
, raw_buf
);
457 i386_pseudo_register_write (gdbarch
, regcache
, regnum
, buf
);
462 /* Register classes as defined in the psABI. */
476 /* Return the union class of CLASS1 and CLASS2. See the psABI for
479 static enum amd64_reg_class
480 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
482 /* Rule (a): If both classes are equal, this is the resulting class. */
483 if (class1
== class2
)
486 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
487 is the other class. */
488 if (class1
== AMD64_NO_CLASS
)
490 if (class2
== AMD64_NO_CLASS
)
493 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
494 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
497 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
498 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
499 return AMD64_INTEGER
;
501 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
502 MEMORY is used as class. */
503 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
504 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
505 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
508 /* Rule (f): Otherwise class SSE is used. */
512 static void amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2]);
514 /* Return non-zero if TYPE is a non-POD structure or union type. */
517 amd64_non_pod_p (struct type
*type
)
519 /* ??? A class with a base class certainly isn't POD, but does this
520 catch all non-POD structure types? */
521 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
&& TYPE_N_BASECLASSES (type
) > 0)
527 /* Classify TYPE according to the rules for aggregate (structures and
528 arrays) and union types, and store the result in CLASS. */
531 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class theclass
[2])
533 /* 1. If the size of an object is larger than two eightbytes, or in
534 C++, is a non-POD structure or union type, or contains
535 unaligned fields, it has class memory. */
536 if (TYPE_LENGTH (type
) > 16 || amd64_non_pod_p (type
))
538 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
542 /* 2. Both eightbytes get initialized to class NO_CLASS. */
543 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
545 /* 3. Each field of an object is classified recursively so that
546 always two fields are considered. The resulting class is
547 calculated according to the classes of the fields in the
550 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
552 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
554 /* All fields in an array have the same type. */
555 amd64_classify (subtype
, theclass
);
556 if (TYPE_LENGTH (type
) > 8 && theclass
[1] == AMD64_NO_CLASS
)
557 theclass
[1] = theclass
[0];
563 /* Structure or union. */
564 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
565 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
567 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
569 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
570 int pos
= TYPE_FIELD_BITPOS (type
, i
) / 64;
571 enum amd64_reg_class subclass
[2];
572 int bitsize
= TYPE_FIELD_BITSIZE (type
, i
);
576 bitsize
= TYPE_LENGTH (subtype
) * 8;
577 endpos
= (TYPE_FIELD_BITPOS (type
, i
) + bitsize
- 1) / 64;
579 /* Ignore static fields. */
580 if (field_is_static (&TYPE_FIELD (type
, i
)))
583 gdb_assert (pos
== 0 || pos
== 1);
585 amd64_classify (subtype
, subclass
);
586 theclass
[pos
] = amd64_merge_classes (theclass
[pos
], subclass
[0]);
587 if (bitsize
<= 64 && pos
== 0 && endpos
== 1)
588 /* This is a bit of an odd case: We have a field that would
589 normally fit in one of the two eightbytes, except that
590 it is placed in a way that this field straddles them.
591 This has been seen with a structure containing an array.
593 The ABI is a bit unclear in this case, but we assume that
594 this field's class (stored in subclass[0]) must also be merged
595 into class[1]. In other words, our field has a piece stored
596 in the second eight-byte, and thus its class applies to
597 the second eight-byte as well.
599 In the case where the field length exceeds 8 bytes,
600 it should not be necessary to merge the field class
601 into class[1]. As LEN > 8, subclass[1] is necessarily
602 different from AMD64_NO_CLASS. If subclass[1] is equal
603 to subclass[0], then the normal class[1]/subclass[1]
604 merging will take care of everything. For subclass[1]
605 to be different from subclass[0], I can only see the case
606 where we have a SSE/SSEUP or X87/X87UP pair, which both
607 use up all 16 bytes of the aggregate, and are already
608 handled just fine (because each portion sits on its own
610 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[0]);
612 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[1]);
616 /* 4. Then a post merger cleanup is done: */
618 /* Rule (a): If one of the classes is MEMORY, the whole argument is
620 if (theclass
[0] == AMD64_MEMORY
|| theclass
[1] == AMD64_MEMORY
)
621 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
623 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
625 if (theclass
[0] == AMD64_SSEUP
)
626 theclass
[0] = AMD64_SSE
;
627 if (theclass
[1] == AMD64_SSEUP
&& theclass
[0] != AMD64_SSE
)
628 theclass
[1] = AMD64_SSE
;
631 /* Classify TYPE, and store the result in CLASS. */
634 amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2])
636 enum type_code code
= TYPE_CODE (type
);
637 int len
= TYPE_LENGTH (type
);
639 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
641 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
642 long, long long, and pointers are in the INTEGER class. Similarly,
643 range types, used by languages such as Ada, are also in the INTEGER
645 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
646 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
647 || code
== TYPE_CODE_CHAR
648 || code
== TYPE_CODE_PTR
|| code
== TYPE_CODE_REF
)
649 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
650 theclass
[0] = AMD64_INTEGER
;
652 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
654 else if ((code
== TYPE_CODE_FLT
|| code
== TYPE_CODE_DECFLOAT
)
655 && (len
== 4 || len
== 8))
657 theclass
[0] = AMD64_SSE
;
659 /* Arguments of types __float128, _Decimal128 and __m128 are split into
660 two halves. The least significant ones belong to class SSE, the most
661 significant one to class SSEUP. */
662 else if (code
== TYPE_CODE_DECFLOAT
&& len
== 16)
663 /* FIXME: __float128, __m128. */
664 theclass
[0] = AMD64_SSE
, theclass
[1] = AMD64_SSEUP
;
666 /* The 64-bit mantissa of arguments of type long double belongs to
667 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
669 else if (code
== TYPE_CODE_FLT
&& len
== 16)
670 /* Class X87 and X87UP. */
671 theclass
[0] = AMD64_X87
, theclass
[1] = AMD64_X87UP
;
673 /* Arguments of complex T where T is one of the types float or
674 double get treated as if they are implemented as:
682 else if (code
== TYPE_CODE_COMPLEX
&& len
== 8)
683 theclass
[0] = AMD64_SSE
;
684 else if (code
== TYPE_CODE_COMPLEX
&& len
== 16)
685 theclass
[0] = theclass
[1] = AMD64_SSE
;
687 /* A variable of type complex long double is classified as type
689 else if (code
== TYPE_CODE_COMPLEX
&& len
== 32)
690 theclass
[0] = AMD64_COMPLEX_X87
;
693 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
694 || code
== TYPE_CODE_UNION
)
695 amd64_classify_aggregate (type
, theclass
);
698 static enum return_value_convention
699 amd64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
700 struct type
*type
, struct regcache
*regcache
,
701 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
703 enum amd64_reg_class theclass
[2];
704 int len
= TYPE_LENGTH (type
);
705 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
706 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
711 gdb_assert (!(readbuf
&& writebuf
));
713 /* 1. Classify the return type with the classification algorithm. */
714 amd64_classify (type
, theclass
);
716 /* 2. If the type has class MEMORY, then the caller provides space
717 for the return value and passes the address of this storage in
718 %rdi as if it were the first argument to the function. In effect,
719 this address becomes a hidden first argument.
721 On return %rax will contain the address that has been passed in
722 by the caller in %rdi. */
723 if (theclass
[0] == AMD64_MEMORY
)
725 /* As indicated by the comment above, the ABI guarantees that we
726 can always find the return value just after the function has
733 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
734 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
737 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
740 /* 8. If the class is COMPLEX_X87, the real part of the value is
741 returned in %st0 and the imaginary part in %st1. */
742 if (theclass
[0] == AMD64_COMPLEX_X87
)
746 regcache_raw_read (regcache
, AMD64_ST0_REGNUM
, readbuf
);
747 regcache_raw_read (regcache
, AMD64_ST1_REGNUM
, readbuf
+ 16);
752 i387_return_value (gdbarch
, regcache
);
753 regcache_raw_write (regcache
, AMD64_ST0_REGNUM
, writebuf
);
754 regcache_raw_write (regcache
, AMD64_ST1_REGNUM
, writebuf
+ 16);
756 /* Fix up the tag word such that both %st(0) and %st(1) are
758 regcache_raw_write_unsigned (regcache
, AMD64_FTAG_REGNUM
, 0xfff);
761 return RETURN_VALUE_REGISTER_CONVENTION
;
764 gdb_assert (theclass
[1] != AMD64_MEMORY
);
765 gdb_assert (len
<= 16);
767 for (i
= 0; len
> 0; i
++, len
-= 8)
775 /* 3. If the class is INTEGER, the next available register
776 of the sequence %rax, %rdx is used. */
777 regnum
= integer_regnum
[integer_reg
++];
781 /* 4. If the class is SSE, the next available SSE register
782 of the sequence %xmm0, %xmm1 is used. */
783 regnum
= sse_regnum
[sse_reg
++];
787 /* 5. If the class is SSEUP, the eightbyte is passed in the
788 upper half of the last used SSE register. */
789 gdb_assert (sse_reg
> 0);
790 regnum
= sse_regnum
[sse_reg
- 1];
795 /* 6. If the class is X87, the value is returned on the X87
796 stack in %st0 as 80-bit x87 number. */
797 regnum
= AMD64_ST0_REGNUM
;
799 i387_return_value (gdbarch
, regcache
);
803 /* 7. If the class is X87UP, the value is returned together
804 with the previous X87 value in %st0. */
805 gdb_assert (i
> 0 && theclass
[0] == AMD64_X87
);
806 regnum
= AMD64_ST0_REGNUM
;
815 gdb_assert (!"Unexpected register class.");
818 gdb_assert (regnum
!= -1);
821 regcache_raw_read_part (regcache
, regnum
, offset
, min (len
, 8),
824 regcache_raw_write_part (regcache
, regnum
, offset
, min (len
, 8),
828 return RETURN_VALUE_REGISTER_CONVENTION
;
833 amd64_push_arguments (struct regcache
*regcache
, int nargs
,
834 struct value
**args
, CORE_ADDR sp
, int struct_return
)
836 static int integer_regnum
[] =
838 AMD64_RDI_REGNUM
, /* %rdi */
839 AMD64_RSI_REGNUM
, /* %rsi */
840 AMD64_RDX_REGNUM
, /* %rdx */
841 AMD64_RCX_REGNUM
, /* %rcx */
842 AMD64_R8_REGNUM
, /* %r8 */
843 AMD64_R9_REGNUM
/* %r9 */
845 static int sse_regnum
[] =
847 /* %xmm0 ... %xmm7 */
848 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
849 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
850 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
851 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
853 struct value
**stack_args
= XALLOCAVEC (struct value
*, nargs
);
854 int num_stack_args
= 0;
855 int num_elements
= 0;
861 /* Reserve a register for the "hidden" argument. */
865 for (i
= 0; i
< nargs
; i
++)
867 struct type
*type
= value_type (args
[i
]);
868 int len
= TYPE_LENGTH (type
);
869 enum amd64_reg_class theclass
[2];
870 int needed_integer_regs
= 0;
871 int needed_sse_regs
= 0;
874 /* Classify argument. */
875 amd64_classify (type
, theclass
);
877 /* Calculate the number of integer and SSE registers needed for
879 for (j
= 0; j
< 2; j
++)
881 if (theclass
[j
] == AMD64_INTEGER
)
882 needed_integer_regs
++;
883 else if (theclass
[j
] == AMD64_SSE
)
887 /* Check whether enough registers are available, and if the
888 argument should be passed in registers at all. */
889 if (integer_reg
+ needed_integer_regs
> ARRAY_SIZE (integer_regnum
)
890 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
891 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
893 /* The argument will be passed on the stack. */
894 num_elements
+= ((len
+ 7) / 8);
895 stack_args
[num_stack_args
++] = args
[i
];
899 /* The argument will be passed in registers. */
900 const gdb_byte
*valbuf
= value_contents (args
[i
]);
903 gdb_assert (len
<= 16);
905 for (j
= 0; len
> 0; j
++, len
-= 8)
913 regnum
= integer_regnum
[integer_reg
++];
917 regnum
= sse_regnum
[sse_reg
++];
921 gdb_assert (sse_reg
> 0);
922 regnum
= sse_regnum
[sse_reg
- 1];
927 gdb_assert (!"Unexpected register class.");
930 gdb_assert (regnum
!= -1);
931 memset (buf
, 0, sizeof buf
);
932 memcpy (buf
, valbuf
+ j
* 8, min (len
, 8));
933 regcache_raw_write_part (regcache
, regnum
, offset
, 8, buf
);
938 /* Allocate space for the arguments on the stack. */
939 sp
-= num_elements
* 8;
941 /* The psABI says that "The end of the input argument area shall be
942 aligned on a 16 byte boundary." */
945 /* Write out the arguments to the stack. */
946 for (i
= 0; i
< num_stack_args
; i
++)
948 struct type
*type
= value_type (stack_args
[i
]);
949 const gdb_byte
*valbuf
= value_contents (stack_args
[i
]);
950 int len
= TYPE_LENGTH (type
);
952 write_memory (sp
+ element
* 8, valbuf
, len
);
953 element
+= ((len
+ 7) / 8);
956 /* The psABI says that "For calls that may call functions that use
957 varargs or stdargs (prototype-less calls or calls to functions
958 containing ellipsis (...) in the declaration) %al is used as
959 hidden argument to specify the number of SSE registers used. */
960 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
965 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
966 struct regcache
*regcache
, CORE_ADDR bp_addr
,
967 int nargs
, struct value
**args
, CORE_ADDR sp
,
968 int struct_return
, CORE_ADDR struct_addr
)
970 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
973 /* Pass arguments. */
974 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, struct_return
);
976 /* Pass "hidden" argument". */
979 store_unsigned_integer (buf
, 8, byte_order
, struct_addr
);
980 regcache_cooked_write (regcache
, AMD64_RDI_REGNUM
, buf
);
983 /* Store return address. */
985 store_unsigned_integer (buf
, 8, byte_order
, bp_addr
);
986 write_memory (sp
, buf
, 8);
988 /* Finally, update the stack pointer... */
989 store_unsigned_integer (buf
, 8, byte_order
, sp
);
990 regcache_cooked_write (regcache
, AMD64_RSP_REGNUM
, buf
);
992 /* ...and fake a frame pointer. */
993 regcache_cooked_write (regcache
, AMD64_RBP_REGNUM
, buf
);
998 /* Displaced instruction handling. */
1000 /* A partially decoded instruction.
1001 This contains enough details for displaced stepping purposes. */
1005 /* The number of opcode bytes. */
1007 /* The offset of the rex prefix or -1 if not present. */
1009 /* The offset to the first opcode byte. */
1011 /* The offset to the modrm byte or -1 if not present. */
1014 /* The raw instruction. */
1018 struct displaced_step_closure
1020 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1025 /* Details of the instruction. */
1026 struct amd64_insn insn_details
;
1028 /* Amount of space allocated to insn_buf. */
1031 /* The possibly modified insn.
1032 This is a variable-length field. */
1033 gdb_byte insn_buf
[1];
1036 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1037 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1038 at which point delete these in favor of libopcodes' versions). */
1040 static const unsigned char onebyte_has_modrm
[256] = {
1041 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1042 /* ------------------------------- */
1043 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1044 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1045 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1046 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1047 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1048 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1049 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1050 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1051 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1052 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1053 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1054 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1055 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1056 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1057 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1058 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1059 /* ------------------------------- */
1060 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1063 static const unsigned char twobyte_has_modrm
[256] = {
1064 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1065 /* ------------------------------- */
1066 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1067 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1068 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1069 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1070 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1071 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1072 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1073 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1074 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1075 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1076 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1077 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1078 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1079 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1080 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1081 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1082 /* ------------------------------- */
1083 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1086 static int amd64_syscall_p (const struct amd64_insn
*insn
, int *lengthp
);
1089 rex_prefix_p (gdb_byte pfx
)
1091 return REX_PREFIX_P (pfx
);
1094 /* Skip the legacy instruction prefixes in INSN.
1095 We assume INSN is properly sentineled so we don't have to worry
1096 about falling off the end of the buffer. */
1099 amd64_skip_prefixes (gdb_byte
*insn
)
1105 case DATA_PREFIX_OPCODE
:
1106 case ADDR_PREFIX_OPCODE
:
1107 case CS_PREFIX_OPCODE
:
1108 case DS_PREFIX_OPCODE
:
1109 case ES_PREFIX_OPCODE
:
1110 case FS_PREFIX_OPCODE
:
1111 case GS_PREFIX_OPCODE
:
1112 case SS_PREFIX_OPCODE
:
1113 case LOCK_PREFIX_OPCODE
:
1114 case REPE_PREFIX_OPCODE
:
1115 case REPNE_PREFIX_OPCODE
:
1127 /* Return an integer register (other than RSP) that is unused as an input
1129 In order to not require adding a rex prefix if the insn doesn't already
1130 have one, the result is restricted to RAX ... RDI, sans RSP.
1131 The register numbering of the result follows architecture ordering,
1135 amd64_get_unused_input_int_reg (const struct amd64_insn
*details
)
1137 /* 1 bit for each reg */
1138 int used_regs_mask
= 0;
1140 /* There can be at most 3 int regs used as inputs in an insn, and we have
1141 7 to choose from (RAX ... RDI, sans RSP).
1142 This allows us to take a conservative approach and keep things simple.
1143 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1144 that implicitly specify RAX. */
1147 used_regs_mask
|= 1 << EAX_REG_NUM
;
1148 /* Similarily avoid RDX, implicit operand in divides. */
1149 used_regs_mask
|= 1 << EDX_REG_NUM
;
1151 used_regs_mask
|= 1 << ESP_REG_NUM
;
1153 /* If the opcode is one byte long and there's no ModRM byte,
1154 assume the opcode specifies a register. */
1155 if (details
->opcode_len
== 1 && details
->modrm_offset
== -1)
1156 used_regs_mask
|= 1 << (details
->raw_insn
[details
->opcode_offset
] & 7);
1158 /* Mark used regs in the modrm/sib bytes. */
1159 if (details
->modrm_offset
!= -1)
1161 int modrm
= details
->raw_insn
[details
->modrm_offset
];
1162 int mod
= MODRM_MOD_FIELD (modrm
);
1163 int reg
= MODRM_REG_FIELD (modrm
);
1164 int rm
= MODRM_RM_FIELD (modrm
);
1165 int have_sib
= mod
!= 3 && rm
== 4;
1167 /* Assume the reg field of the modrm byte specifies a register. */
1168 used_regs_mask
|= 1 << reg
;
1172 int base
= SIB_BASE_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1173 int idx
= SIB_INDEX_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1174 used_regs_mask
|= 1 << base
;
1175 used_regs_mask
|= 1 << idx
;
1179 used_regs_mask
|= 1 << rm
;
1183 gdb_assert (used_regs_mask
< 256);
1184 gdb_assert (used_regs_mask
!= 255);
1186 /* Finally, find a free reg. */
1190 for (i
= 0; i
< 8; ++i
)
1192 if (! (used_regs_mask
& (1 << i
)))
1196 /* We shouldn't get here. */
1197 internal_error (__FILE__
, __LINE__
, _("unable to find free reg"));
1201 /* Extract the details of INSN that we need. */
1204 amd64_get_insn_details (gdb_byte
*insn
, struct amd64_insn
*details
)
1206 gdb_byte
*start
= insn
;
1209 details
->raw_insn
= insn
;
1211 details
->opcode_len
= -1;
1212 details
->rex_offset
= -1;
1213 details
->opcode_offset
= -1;
1214 details
->modrm_offset
= -1;
1216 /* Skip legacy instruction prefixes. */
1217 insn
= amd64_skip_prefixes (insn
);
1219 /* Skip REX instruction prefix. */
1220 if (rex_prefix_p (*insn
))
1222 details
->rex_offset
= insn
- start
;
1226 details
->opcode_offset
= insn
- start
;
1228 if (*insn
== TWO_BYTE_OPCODE_ESCAPE
)
1230 /* Two or three-byte opcode. */
1232 need_modrm
= twobyte_has_modrm
[*insn
];
1234 /* Check for three-byte opcode. */
1244 details
->opcode_len
= 3;
1247 details
->opcode_len
= 2;
1253 /* One-byte opcode. */
1254 need_modrm
= onebyte_has_modrm
[*insn
];
1255 details
->opcode_len
= 1;
1261 details
->modrm_offset
= insn
- start
;
1265 /* Update %rip-relative addressing in INSN.
1267 %rip-relative addressing only uses a 32-bit displacement.
1268 32 bits is not enough to be guaranteed to cover the distance between where
1269 the real instruction is and where its copy is.
1270 Convert the insn to use base+disp addressing.
1271 We set base = pc + insn_length so we can leave disp unchanged. */
1274 fixup_riprel (struct gdbarch
*gdbarch
, struct displaced_step_closure
*dsc
,
1275 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1277 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1278 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1279 int modrm_offset
= insn_details
->modrm_offset
;
1280 gdb_byte
*insn
= insn_details
->raw_insn
+ modrm_offset
;
1284 int arch_tmp_regno
, tmp_regno
;
1285 ULONGEST orig_value
;
1287 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1290 /* Compute the rip-relative address. */
1291 disp
= extract_signed_integer (insn
, sizeof (int32_t), byte_order
);
1292 insn_length
= gdb_buffered_insn_length (gdbarch
, dsc
->insn_buf
,
1293 dsc
->max_len
, from
);
1294 rip_base
= from
+ insn_length
;
1296 /* We need a register to hold the address.
1297 Pick one not used in the insn.
1298 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1299 arch_tmp_regno
= amd64_get_unused_input_int_reg (insn_details
);
1300 tmp_regno
= amd64_arch_reg_to_regnum (arch_tmp_regno
);
1302 /* REX.B should be unset as we were using rip-relative addressing,
1303 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1304 if (insn_details
->rex_offset
!= -1)
1305 dsc
->insn_buf
[insn_details
->rex_offset
] &= ~REX_B
;
1307 regcache_cooked_read_unsigned (regs
, tmp_regno
, &orig_value
);
1308 dsc
->tmp_regno
= tmp_regno
;
1309 dsc
->tmp_save
= orig_value
;
1312 /* Convert the ModRM field to be base+disp. */
1313 dsc
->insn_buf
[modrm_offset
] &= ~0xc7;
1314 dsc
->insn_buf
[modrm_offset
] |= 0x80 + arch_tmp_regno
;
1316 regcache_cooked_write_unsigned (regs
, tmp_regno
, rip_base
);
1318 if (debug_displaced
)
1319 fprintf_unfiltered (gdb_stdlog
, "displaced: %%rip-relative addressing used.\n"
1320 "displaced: using temp reg %d, old value %s, new value %s\n",
1321 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
),
1322 paddress (gdbarch
, rip_base
));
1326 fixup_displaced_copy (struct gdbarch
*gdbarch
,
1327 struct displaced_step_closure
*dsc
,
1328 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1330 const struct amd64_insn
*details
= &dsc
->insn_details
;
1332 if (details
->modrm_offset
!= -1)
1334 gdb_byte modrm
= details
->raw_insn
[details
->modrm_offset
];
1336 if ((modrm
& 0xc7) == 0x05)
1338 /* The insn uses rip-relative addressing.
1340 fixup_riprel (gdbarch
, dsc
, from
, to
, regs
);
1345 struct displaced_step_closure
*
1346 amd64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1347 CORE_ADDR from
, CORE_ADDR to
,
1348 struct regcache
*regs
)
1350 int len
= gdbarch_max_insn_length (gdbarch
);
1351 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1352 continually watch for running off the end of the buffer. */
1353 int fixup_sentinel_space
= len
;
1354 struct displaced_step_closure
*dsc
1355 = ((struct displaced_step_closure
*)
1356 xmalloc (sizeof (*dsc
) + len
+ fixup_sentinel_space
));
1357 gdb_byte
*buf
= &dsc
->insn_buf
[0];
1358 struct amd64_insn
*details
= &dsc
->insn_details
;
1361 dsc
->max_len
= len
+ fixup_sentinel_space
;
1363 read_memory (from
, buf
, len
);
1365 /* Set up the sentinel space so we don't have to worry about running
1366 off the end of the buffer. An excessive number of leading prefixes
1367 could otherwise cause this. */
1368 memset (buf
+ len
, 0, fixup_sentinel_space
);
1370 amd64_get_insn_details (buf
, details
);
1372 /* GDB may get control back after the insn after the syscall.
1373 Presumably this is a kernel bug.
1374 If this is a syscall, make sure there's a nop afterwards. */
1378 if (amd64_syscall_p (details
, &syscall_length
))
1379 buf
[details
->opcode_offset
+ syscall_length
] = NOP_OPCODE
;
1382 /* Modify the insn to cope with the address where it will be executed from.
1383 In particular, handle any rip-relative addressing. */
1384 fixup_displaced_copy (gdbarch
, dsc
, from
, to
, regs
);
1386 write_memory (to
, buf
, len
);
1388 if (debug_displaced
)
1390 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1391 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1392 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1399 amd64_absolute_jmp_p (const struct amd64_insn
*details
)
1401 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1403 if (insn
[0] == 0xff)
1405 /* jump near, absolute indirect (/4) */
1406 if ((insn
[1] & 0x38) == 0x20)
1409 /* jump far, absolute indirect (/5) */
1410 if ((insn
[1] & 0x38) == 0x28)
1417 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1420 amd64_jmp_p (const struct amd64_insn
*details
)
1422 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1424 /* jump short, relative. */
1425 if (insn
[0] == 0xeb)
1428 /* jump near, relative. */
1429 if (insn
[0] == 0xe9)
1432 return amd64_absolute_jmp_p (details
);
1436 amd64_absolute_call_p (const struct amd64_insn
*details
)
1438 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1440 if (insn
[0] == 0xff)
1442 /* Call near, absolute indirect (/2) */
1443 if ((insn
[1] & 0x38) == 0x10)
1446 /* Call far, absolute indirect (/3) */
1447 if ((insn
[1] & 0x38) == 0x18)
1455 amd64_ret_p (const struct amd64_insn
*details
)
1457 /* NOTE: gcc can emit "repz ; ret". */
1458 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1462 case 0xc2: /* ret near, pop N bytes */
1463 case 0xc3: /* ret near */
1464 case 0xca: /* ret far, pop N bytes */
1465 case 0xcb: /* ret far */
1466 case 0xcf: /* iret */
1475 amd64_call_p (const struct amd64_insn
*details
)
1477 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1479 if (amd64_absolute_call_p (details
))
1482 /* call near, relative */
1483 if (insn
[0] == 0xe8)
1489 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1490 length in bytes. Otherwise, return zero. */
1493 amd64_syscall_p (const struct amd64_insn
*details
, int *lengthp
)
1495 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1497 if (insn
[0] == 0x0f && insn
[1] == 0x05)
1506 /* Classify the instruction at ADDR using PRED.
1507 Throw an error if the memory can't be read. */
1510 amd64_classify_insn_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
1511 int (*pred
) (const struct amd64_insn
*))
1513 struct amd64_insn details
;
1515 int len
, classification
;
1517 len
= gdbarch_max_insn_length (gdbarch
);
1518 buf
= (gdb_byte
*) alloca (len
);
1520 read_code (addr
, buf
, len
);
1521 amd64_get_insn_details (buf
, &details
);
1523 classification
= pred (&details
);
1525 return classification
;
1528 /* The gdbarch insn_is_call method. */
1531 amd64_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1533 return amd64_classify_insn_at (gdbarch
, addr
, amd64_call_p
);
1536 /* The gdbarch insn_is_ret method. */
1539 amd64_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1541 return amd64_classify_insn_at (gdbarch
, addr
, amd64_ret_p
);
1544 /* The gdbarch insn_is_jump method. */
1547 amd64_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1549 return amd64_classify_insn_at (gdbarch
, addr
, amd64_jmp_p
);
1552 /* Fix up the state of registers and memory after having single-stepped
1553 a displaced instruction. */
1556 amd64_displaced_step_fixup (struct gdbarch
*gdbarch
,
1557 struct displaced_step_closure
*dsc
,
1558 CORE_ADDR from
, CORE_ADDR to
,
1559 struct regcache
*regs
)
1561 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1562 /* The offset we applied to the instruction's address. */
1563 ULONGEST insn_offset
= to
- from
;
1564 gdb_byte
*insn
= dsc
->insn_buf
;
1565 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1567 if (debug_displaced
)
1568 fprintf_unfiltered (gdb_stdlog
,
1569 "displaced: fixup (%s, %s), "
1570 "insn = 0x%02x 0x%02x ...\n",
1571 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1574 /* If we used a tmp reg, restore it. */
1578 if (debug_displaced
)
1579 fprintf_unfiltered (gdb_stdlog
, "displaced: restoring reg %d to %s\n",
1580 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
));
1581 regcache_cooked_write_unsigned (regs
, dsc
->tmp_regno
, dsc
->tmp_save
);
1584 /* The list of issues to contend with here is taken from
1585 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1586 Yay for Free Software! */
1588 /* Relocate the %rip back to the program's instruction stream,
1591 /* Except in the case of absolute or indirect jump or call
1592 instructions, or a return instruction, the new rip is relative to
1593 the displaced instruction; make it relative to the original insn.
1594 Well, signal handler returns don't need relocation either, but we use the
1595 value of %rip to recognize those; see below. */
1596 if (! amd64_absolute_jmp_p (insn_details
)
1597 && ! amd64_absolute_call_p (insn_details
)
1598 && ! amd64_ret_p (insn_details
))
1603 regcache_cooked_read_unsigned (regs
, AMD64_RIP_REGNUM
, &orig_rip
);
1605 /* A signal trampoline system call changes the %rip, resuming
1606 execution of the main program after the signal handler has
1607 returned. That makes them like 'return' instructions; we
1608 shouldn't relocate %rip.
1610 But most system calls don't, and we do need to relocate %rip.
1612 Our heuristic for distinguishing these cases: if stepping
1613 over the system call instruction left control directly after
1614 the instruction, the we relocate --- control almost certainly
1615 doesn't belong in the displaced copy. Otherwise, we assume
1616 the instruction has put control where it belongs, and leave
1617 it unrelocated. Goodness help us if there are PC-relative
1619 if (amd64_syscall_p (insn_details
, &insn_len
)
1620 && orig_rip
!= to
+ insn_len
1621 /* GDB can get control back after the insn after the syscall.
1622 Presumably this is a kernel bug.
1623 Fixup ensures its a nop, we add one to the length for it. */
1624 && orig_rip
!= to
+ insn_len
+ 1)
1626 if (debug_displaced
)
1627 fprintf_unfiltered (gdb_stdlog
,
1628 "displaced: syscall changed %%rip; "
1629 "not relocating\n");
1633 ULONGEST rip
= orig_rip
- insn_offset
;
1635 /* If we just stepped over a breakpoint insn, we don't backup
1636 the pc on purpose; this is to match behaviour without
1639 regcache_cooked_write_unsigned (regs
, AMD64_RIP_REGNUM
, rip
);
1641 if (debug_displaced
)
1642 fprintf_unfiltered (gdb_stdlog
,
1644 "relocated %%rip from %s to %s\n",
1645 paddress (gdbarch
, orig_rip
),
1646 paddress (gdbarch
, rip
));
1650 /* If the instruction was PUSHFL, then the TF bit will be set in the
1651 pushed value, and should be cleared. We'll leave this for later,
1652 since GDB already messes up the TF flag when stepping over a
1655 /* If the instruction was a call, the return address now atop the
1656 stack is the address following the copied instruction. We need
1657 to make it the address following the original instruction. */
1658 if (amd64_call_p (insn_details
))
1662 const ULONGEST retaddr_len
= 8;
1664 regcache_cooked_read_unsigned (regs
, AMD64_RSP_REGNUM
, &rsp
);
1665 retaddr
= read_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
);
1666 retaddr
= (retaddr
- insn_offset
) & 0xffffffffffffffffULL
;
1667 write_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
, retaddr
);
1669 if (debug_displaced
)
1670 fprintf_unfiltered (gdb_stdlog
,
1671 "displaced: relocated return addr at %s "
1673 paddress (gdbarch
, rsp
),
1674 paddress (gdbarch
, retaddr
));
1678 /* If the instruction INSN uses RIP-relative addressing, return the
1679 offset into the raw INSN where the displacement to be adjusted is
1680 found. Returns 0 if the instruction doesn't use RIP-relative
1684 rip_relative_offset (struct amd64_insn
*insn
)
1686 if (insn
->modrm_offset
!= -1)
1688 gdb_byte modrm
= insn
->raw_insn
[insn
->modrm_offset
];
1690 if ((modrm
& 0xc7) == 0x05)
1692 /* The displacement is found right after the ModRM byte. */
1693 return insn
->modrm_offset
+ 1;
1701 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
1703 target_write_memory (*to
, buf
, len
);
1708 amd64_relocate_instruction (struct gdbarch
*gdbarch
,
1709 CORE_ADDR
*to
, CORE_ADDR oldloc
)
1711 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1712 int len
= gdbarch_max_insn_length (gdbarch
);
1713 /* Extra space for sentinels. */
1714 int fixup_sentinel_space
= len
;
1715 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
+ fixup_sentinel_space
);
1716 struct amd64_insn insn_details
;
1718 LONGEST rel32
, newrel
;
1722 read_memory (oldloc
, buf
, len
);
1724 /* Set up the sentinel space so we don't have to worry about running
1725 off the end of the buffer. An excessive number of leading prefixes
1726 could otherwise cause this. */
1727 memset (buf
+ len
, 0, fixup_sentinel_space
);
1730 amd64_get_insn_details (insn
, &insn_details
);
1732 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
, len
, oldloc
);
1734 /* Skip legacy instruction prefixes. */
1735 insn
= amd64_skip_prefixes (insn
);
1737 /* Adjust calls with 32-bit relative addresses as push/jump, with
1738 the address pushed being the location where the original call in
1739 the user program would return to. */
1740 if (insn
[0] == 0xe8)
1742 gdb_byte push_buf
[16];
1743 unsigned int ret_addr
;
1745 /* Where "ret" in the original code will return to. */
1746 ret_addr
= oldloc
+ insn_length
;
1747 push_buf
[0] = 0x68; /* pushq $... */
1748 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
1749 /* Push the push. */
1750 append_insns (to
, 5, push_buf
);
1752 /* Convert the relative call to a relative jump. */
1755 /* Adjust the destination offset. */
1756 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1757 newrel
= (oldloc
- *to
) + rel32
;
1758 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1760 if (debug_displaced
)
1761 fprintf_unfiltered (gdb_stdlog
,
1762 "Adjusted insn rel32=%s at %s to"
1763 " rel32=%s at %s\n",
1764 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1765 hex_string (newrel
), paddress (gdbarch
, *to
));
1767 /* Write the adjusted jump into its displaced location. */
1768 append_insns (to
, 5, insn
);
1772 offset
= rip_relative_offset (&insn_details
);
1775 /* Adjust jumps with 32-bit relative addresses. Calls are
1776 already handled above. */
1777 if (insn
[0] == 0xe9)
1779 /* Adjust conditional jumps. */
1780 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1786 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1787 newrel
= (oldloc
- *to
) + rel32
;
1788 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1789 if (debug_displaced
)
1790 fprintf_unfiltered (gdb_stdlog
,
1791 "Adjusted insn rel32=%s at %s to"
1792 " rel32=%s at %s\n",
1793 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1794 hex_string (newrel
), paddress (gdbarch
, *to
));
1797 /* Write the adjusted instruction into its displaced location. */
1798 append_insns (to
, insn_length
, buf
);
1802 /* The maximum number of saved registers. This should include %rip. */
1803 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1805 struct amd64_frame_cache
1810 CORE_ADDR sp_offset
;
1813 /* Saved registers. */
1814 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
1818 /* Do we have a frame? */
1822 /* Initialize a frame cache. */
1825 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
1832 cache
->sp_offset
= -8;
1835 /* Saved registers. We initialize these to -1 since zero is a valid
1836 offset (that's where %rbp is supposed to be stored).
1837 The values start out as being offsets, and are later converted to
1838 addresses (at which point -1 is interpreted as an address, still meaning
1840 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1841 cache
->saved_regs
[i
] = -1;
1842 cache
->saved_sp
= 0;
1843 cache
->saved_sp_reg
= -1;
1845 /* Frameless until proven otherwise. */
1846 cache
->frameless_p
= 1;
1849 /* Allocate and initialize a frame cache. */
1851 static struct amd64_frame_cache
*
1852 amd64_alloc_frame_cache (void)
1854 struct amd64_frame_cache
*cache
;
1856 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
1857 amd64_init_frame_cache (cache
);
1861 /* GCC 4.4 and later, can put code in the prologue to realign the
1862 stack pointer. Check whether PC points to such code, and update
1863 CACHE accordingly. Return the first instruction after the code
1864 sequence or CURRENT_PC, whichever is smaller. If we don't
1865 recognize the code, return PC. */
1868 amd64_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1869 struct amd64_frame_cache
*cache
)
1871 /* There are 2 code sequences to re-align stack before the frame
1874 1. Use a caller-saved saved register:
1880 2. Use a callee-saved saved register:
1887 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1889 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1890 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1895 int offset
, offset_and
;
1897 if (target_read_code (pc
, buf
, sizeof buf
))
1900 /* Check caller-saved saved register. The first instruction has
1901 to be "leaq 8(%rsp), %reg". */
1902 if ((buf
[0] & 0xfb) == 0x48
1907 /* MOD must be binary 10 and R/M must be binary 100. */
1908 if ((buf
[2] & 0xc7) != 0x44)
1911 /* REG has register number. */
1912 reg
= (buf
[2] >> 3) & 7;
1914 /* Check the REX.R bit. */
1922 /* Check callee-saved saved register. The first instruction
1923 has to be "pushq %reg". */
1925 if ((buf
[0] & 0xf8) == 0x50)
1927 else if ((buf
[0] & 0xf6) == 0x40
1928 && (buf
[1] & 0xf8) == 0x50)
1930 /* Check the REX.B bit. */
1931 if ((buf
[0] & 1) != 0)
1940 reg
+= buf
[offset
] & 0x7;
1944 /* The next instruction has to be "leaq 16(%rsp), %reg". */
1945 if ((buf
[offset
] & 0xfb) != 0x48
1946 || buf
[offset
+ 1] != 0x8d
1947 || buf
[offset
+ 3] != 0x24
1948 || buf
[offset
+ 4] != 0x10)
1951 /* MOD must be binary 10 and R/M must be binary 100. */
1952 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
1955 /* REG has register number. */
1956 r
= (buf
[offset
+ 2] >> 3) & 7;
1958 /* Check the REX.R bit. */
1959 if (buf
[offset
] == 0x4c)
1962 /* Registers in pushq and leaq have to be the same. */
1969 /* Rigister can't be %rsp nor %rbp. */
1970 if (reg
== 4 || reg
== 5)
1973 /* The next instruction has to be "andq $-XXX, %rsp". */
1974 if (buf
[offset
] != 0x48
1975 || buf
[offset
+ 2] != 0xe4
1976 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
1979 offset_and
= offset
;
1980 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
1982 /* The next instruction has to be "pushq -8(%reg)". */
1984 if (buf
[offset
] == 0xff)
1986 else if ((buf
[offset
] & 0xf6) == 0x40
1987 && buf
[offset
+ 1] == 0xff)
1989 /* Check the REX.B bit. */
1990 if ((buf
[offset
] & 0x1) != 0)
1997 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
1999 if (buf
[offset
+ 1] != 0xf8
2000 || (buf
[offset
] & 0xf8) != 0x70)
2003 /* R/M has register. */
2004 r
+= buf
[offset
] & 7;
2006 /* Registers in leaq and pushq have to be the same. */
2010 if (current_pc
> pc
+ offset_and
)
2011 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2013 return min (pc
+ offset
+ 2, current_pc
);
2016 /* Similar to amd64_analyze_stack_align for x32. */
2019 amd64_x32_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
2020 struct amd64_frame_cache
*cache
)
2022 /* There are 2 code sequences to re-align stack before the frame
2025 1. Use a caller-saved saved register:
2033 [addr32] leal 8(%rsp), %reg
2035 [addr32] pushq -8(%reg)
2037 2. Use a callee-saved saved register:
2047 [addr32] leal 16(%rsp), %reg
2049 [addr32] pushq -8(%reg)
2051 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2053 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2054 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2056 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2058 0x83 0xe4 0xf0 andl $-16, %esp
2059 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2064 int offset
, offset_and
;
2066 if (target_read_memory (pc
, buf
, sizeof buf
))
2069 /* Skip optional addr32 prefix. */
2070 offset
= buf
[0] == 0x67 ? 1 : 0;
2072 /* Check caller-saved saved register. The first instruction has
2073 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2074 if (((buf
[offset
] & 0xfb) == 0x48 || (buf
[offset
] & 0xfb) == 0x40)
2075 && buf
[offset
+ 1] == 0x8d
2076 && buf
[offset
+ 3] == 0x24
2077 && buf
[offset
+ 4] == 0x8)
2079 /* MOD must be binary 10 and R/M must be binary 100. */
2080 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2083 /* REG has register number. */
2084 reg
= (buf
[offset
+ 2] >> 3) & 7;
2086 /* Check the REX.R bit. */
2087 if ((buf
[offset
] & 0x4) != 0)
2094 /* Check callee-saved saved register. The first instruction
2095 has to be "pushq %reg". */
2097 if ((buf
[offset
] & 0xf6) == 0x40
2098 && (buf
[offset
+ 1] & 0xf8) == 0x50)
2100 /* Check the REX.B bit. */
2101 if ((buf
[offset
] & 1) != 0)
2106 else if ((buf
[offset
] & 0xf8) != 0x50)
2110 reg
+= buf
[offset
] & 0x7;
2114 /* Skip optional addr32 prefix. */
2115 if (buf
[offset
] == 0x67)
2118 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2119 "leal 16(%rsp), %reg". */
2120 if (((buf
[offset
] & 0xfb) != 0x48 && (buf
[offset
] & 0xfb) != 0x40)
2121 || buf
[offset
+ 1] != 0x8d
2122 || buf
[offset
+ 3] != 0x24
2123 || buf
[offset
+ 4] != 0x10)
2126 /* MOD must be binary 10 and R/M must be binary 100. */
2127 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2130 /* REG has register number. */
2131 r
= (buf
[offset
+ 2] >> 3) & 7;
2133 /* Check the REX.R bit. */
2134 if ((buf
[offset
] & 0x4) != 0)
2137 /* Registers in pushq and leaq have to be the same. */
2144 /* Rigister can't be %rsp nor %rbp. */
2145 if (reg
== 4 || reg
== 5)
2148 /* The next instruction may be "andq $-XXX, %rsp" or
2149 "andl $-XXX, %esp". */
2150 if (buf
[offset
] != 0x48)
2153 if (buf
[offset
+ 2] != 0xe4
2154 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2157 offset_and
= offset
;
2158 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2160 /* Skip optional addr32 prefix. */
2161 if (buf
[offset
] == 0x67)
2164 /* The next instruction has to be "pushq -8(%reg)". */
2166 if (buf
[offset
] == 0xff)
2168 else if ((buf
[offset
] & 0xf6) == 0x40
2169 && buf
[offset
+ 1] == 0xff)
2171 /* Check the REX.B bit. */
2172 if ((buf
[offset
] & 0x1) != 0)
2179 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2181 if (buf
[offset
+ 1] != 0xf8
2182 || (buf
[offset
] & 0xf8) != 0x70)
2185 /* R/M has register. */
2186 r
+= buf
[offset
] & 7;
2188 /* Registers in leaq and pushq have to be the same. */
2192 if (current_pc
> pc
+ offset_and
)
2193 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2195 return min (pc
+ offset
+ 2, current_pc
);
2198 /* Do a limited analysis of the prologue at PC and update CACHE
2199 accordingly. Bail out early if CURRENT_PC is reached. Return the
2200 address where the analysis stopped.
2202 We will handle only functions beginning with:
2205 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2207 or (for the X32 ABI):
2210 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2212 Any function that doesn't start with one of these sequences will be
2213 assumed to have no prologue and thus no valid frame pointer in
2217 amd64_analyze_prologue (struct gdbarch
*gdbarch
,
2218 CORE_ADDR pc
, CORE_ADDR current_pc
,
2219 struct amd64_frame_cache
*cache
)
2221 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2222 /* There are two variations of movq %rsp, %rbp. */
2223 static const gdb_byte mov_rsp_rbp_1
[3] = { 0x48, 0x89, 0xe5 };
2224 static const gdb_byte mov_rsp_rbp_2
[3] = { 0x48, 0x8b, 0xec };
2225 /* Ditto for movl %esp, %ebp. */
2226 static const gdb_byte mov_esp_ebp_1
[2] = { 0x89, 0xe5 };
2227 static const gdb_byte mov_esp_ebp_2
[2] = { 0x8b, 0xec };
2232 if (current_pc
<= pc
)
2235 if (gdbarch_ptr_bit (gdbarch
) == 32)
2236 pc
= amd64_x32_analyze_stack_align (pc
, current_pc
, cache
);
2238 pc
= amd64_analyze_stack_align (pc
, current_pc
, cache
);
2240 op
= read_code_unsigned_integer (pc
, 1, byte_order
);
2242 if (op
== 0x55) /* pushq %rbp */
2244 /* Take into account that we've executed the `pushq %rbp' that
2245 starts this instruction sequence. */
2246 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
2247 cache
->sp_offset
+= 8;
2249 /* If that's all, return now. */
2250 if (current_pc
<= pc
+ 1)
2253 read_code (pc
+ 1, buf
, 3);
2255 /* Check for `movq %rsp, %rbp'. */
2256 if (memcmp (buf
, mov_rsp_rbp_1
, 3) == 0
2257 || memcmp (buf
, mov_rsp_rbp_2
, 3) == 0)
2259 /* OK, we actually have a frame. */
2260 cache
->frameless_p
= 0;
2264 /* For X32, also check for `movq %esp, %ebp'. */
2265 if (gdbarch_ptr_bit (gdbarch
) == 32)
2267 if (memcmp (buf
, mov_esp_ebp_1
, 2) == 0
2268 || memcmp (buf
, mov_esp_ebp_2
, 2) == 0)
2270 /* OK, we actually have a frame. */
2271 cache
->frameless_p
= 0;
2282 /* Work around false termination of prologue - GCC PR debug/48827.
2284 START_PC is the first instruction of a function, PC is its minimal already
2285 determined advanced address. Function returns PC if it has nothing to do.
2289 <-- here is 0 lines advance - the false prologue end marker.
2290 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2291 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2292 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2293 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2294 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2295 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2296 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2297 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2301 amd64_skip_xmm_prologue (CORE_ADDR pc
, CORE_ADDR start_pc
)
2303 struct symtab_and_line start_pc_sal
, next_sal
;
2304 gdb_byte buf
[4 + 8 * 7];
2310 start_pc_sal
= find_pc_sect_line (start_pc
, NULL
, 0);
2311 if (start_pc_sal
.symtab
== NULL
2312 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2313 (SYMTAB_COMPUNIT (start_pc_sal
.symtab
))) < 6
2314 || start_pc_sal
.pc
!= start_pc
|| pc
>= start_pc_sal
.end
)
2317 next_sal
= find_pc_sect_line (start_pc_sal
.end
, NULL
, 0);
2318 if (next_sal
.line
!= start_pc_sal
.line
)
2321 /* START_PC can be from overlayed memory, ignored here. */
2322 if (target_read_code (next_sal
.pc
- 4, buf
, sizeof (buf
)) != 0)
2326 if (buf
[0] != 0x84 || buf
[1] != 0xc0)
2333 for (xmmreg
= 0; xmmreg
< 8; xmmreg
++)
2335 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2336 if (buf
[offset
] != 0x0f || buf
[offset
+ 1] != 0x29
2337 || (buf
[offset
+ 2] & 0x3f) != (xmmreg
<< 3 | 0x5))
2341 if ((buf
[offset
+ 2] & 0xc0) == 0x40)
2343 /* 8-bit displacement. */
2347 else if ((buf
[offset
+ 2] & 0xc0) == 0x80)
2349 /* 32-bit displacement. */
2357 if (offset
- 4 != buf
[3])
2360 return next_sal
.end
;
2363 /* Return PC of first real instruction. */
2366 amd64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2368 struct amd64_frame_cache cache
;
2370 CORE_ADDR func_addr
;
2372 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
2374 CORE_ADDR post_prologue_pc
2375 = skip_prologue_using_sal (gdbarch
, func_addr
);
2376 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
2378 /* Clang always emits a line note before the prologue and another
2379 one after. We trust clang to emit usable line notes. */
2380 if (post_prologue_pc
2382 && COMPUNIT_PRODUCER (cust
) != NULL
2383 && startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
2384 return max (start_pc
, post_prologue_pc
);
2387 amd64_init_frame_cache (&cache
);
2388 pc
= amd64_analyze_prologue (gdbarch
, start_pc
, 0xffffffffffffffffLL
,
2390 if (cache
.frameless_p
)
2393 return amd64_skip_xmm_prologue (pc
, start_pc
);
2397 /* Normal frames. */
2400 amd64_frame_cache_1 (struct frame_info
*this_frame
,
2401 struct amd64_frame_cache
*cache
)
2403 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2404 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2408 cache
->pc
= get_frame_func (this_frame
);
2410 amd64_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2413 if (cache
->frameless_p
)
2415 /* We didn't find a valid frame. If we're at the start of a
2416 function, or somewhere half-way its prologue, the function's
2417 frame probably hasn't been fully setup yet. Try to
2418 reconstruct the base address for the stack frame by looking
2419 at the stack pointer. For truly "frameless" functions this
2422 if (cache
->saved_sp_reg
!= -1)
2424 /* Stack pointer has been saved. */
2425 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2426 cache
->saved_sp
= extract_unsigned_integer (buf
, 8, byte_order
);
2428 /* We're halfway aligning the stack. */
2429 cache
->base
= ((cache
->saved_sp
- 8) & 0xfffffffffffffff0LL
) - 8;
2430 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->saved_sp
- 8;
2432 /* This will be added back below. */
2433 cache
->saved_regs
[AMD64_RIP_REGNUM
] -= cache
->base
;
2437 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2438 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
)
2444 get_frame_register (this_frame
, AMD64_RBP_REGNUM
, buf
);
2445 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
);
2448 /* Now that we have the base address for the stack frame we can
2449 calculate the value of %rsp in the calling frame. */
2450 cache
->saved_sp
= cache
->base
+ 16;
2452 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2453 frame we find it at the same offset from the reconstructed base
2454 address. If we're halfway aligning the stack, %rip is handled
2455 differently (see above). */
2456 if (!cache
->frameless_p
|| cache
->saved_sp_reg
== -1)
2457 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
2459 /* Adjust all the saved registers such that they contain addresses
2460 instead of offsets. */
2461 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
2462 if (cache
->saved_regs
[i
] != -1)
2463 cache
->saved_regs
[i
] += cache
->base
;
2468 static struct amd64_frame_cache
*
2469 amd64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2471 struct amd64_frame_cache
*cache
;
2474 return (struct amd64_frame_cache
*) *this_cache
;
2476 cache
= amd64_alloc_frame_cache ();
2477 *this_cache
= cache
;
2481 amd64_frame_cache_1 (this_frame
, cache
);
2483 CATCH (ex
, RETURN_MASK_ERROR
)
2485 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2486 throw_exception (ex
);
2493 static enum unwind_stop_reason
2494 amd64_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2497 struct amd64_frame_cache
*cache
=
2498 amd64_frame_cache (this_frame
, this_cache
);
2501 return UNWIND_UNAVAILABLE
;
2503 /* This marks the outermost frame. */
2504 if (cache
->base
== 0)
2505 return UNWIND_OUTERMOST
;
2507 return UNWIND_NO_REASON
;
2511 amd64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2512 struct frame_id
*this_id
)
2514 struct amd64_frame_cache
*cache
=
2515 amd64_frame_cache (this_frame
, this_cache
);
2518 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2519 else if (cache
->base
== 0)
2521 /* This marks the outermost frame. */
2525 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
2528 static struct value
*
2529 amd64_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2532 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2533 struct amd64_frame_cache
*cache
=
2534 amd64_frame_cache (this_frame
, this_cache
);
2536 gdb_assert (regnum
>= 0);
2538 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2539 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2541 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2542 return frame_unwind_got_memory (this_frame
, regnum
,
2543 cache
->saved_regs
[regnum
]);
2545 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2548 static const struct frame_unwind amd64_frame_unwind
=
2551 amd64_frame_unwind_stop_reason
,
2552 amd64_frame_this_id
,
2553 amd64_frame_prev_register
,
2555 default_frame_sniffer
2558 /* Generate a bytecode expression to get the value of the saved PC. */
2561 amd64_gen_return_address (struct gdbarch
*gdbarch
,
2562 struct agent_expr
*ax
, struct axs_value
*value
,
2565 /* The following sequence assumes the traditional use of the base
2567 ax_reg (ax
, AMD64_RBP_REGNUM
);
2569 ax_simple (ax
, aop_add
);
2570 value
->type
= register_type (gdbarch
, AMD64_RIP_REGNUM
);
2571 value
->kind
= axs_lvalue_memory
;
2575 /* Signal trampolines. */
2577 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2578 64-bit variants. This would require using identical frame caches
2579 on both platforms. */
2581 static struct amd64_frame_cache
*
2582 amd64_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2584 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2585 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2586 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2587 struct amd64_frame_cache
*cache
;
2593 return (struct amd64_frame_cache
*) *this_cache
;
2595 cache
= amd64_alloc_frame_cache ();
2599 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2600 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
) - 8;
2602 addr
= tdep
->sigcontext_addr (this_frame
);
2603 gdb_assert (tdep
->sc_reg_offset
);
2604 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
2605 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2606 if (tdep
->sc_reg_offset
[i
] != -1)
2607 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2611 CATCH (ex
, RETURN_MASK_ERROR
)
2613 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2614 throw_exception (ex
);
2618 *this_cache
= cache
;
2622 static enum unwind_stop_reason
2623 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2626 struct amd64_frame_cache
*cache
=
2627 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2630 return UNWIND_UNAVAILABLE
;
2632 return UNWIND_NO_REASON
;
2636 amd64_sigtramp_frame_this_id (struct frame_info
*this_frame
,
2637 void **this_cache
, struct frame_id
*this_id
)
2639 struct amd64_frame_cache
*cache
=
2640 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2643 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2644 else if (cache
->base
== 0)
2646 /* This marks the outermost frame. */
2650 (*this_id
) = frame_id_build (cache
->base
+ 16, get_frame_pc (this_frame
));
2653 static struct value
*
2654 amd64_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2655 void **this_cache
, int regnum
)
2657 /* Make sure we've initialized the cache. */
2658 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2660 return amd64_frame_prev_register (this_frame
, this_cache
, regnum
);
2664 amd64_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2665 struct frame_info
*this_frame
,
2668 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2670 /* We shouldn't even bother if we don't have a sigcontext_addr
2672 if (tdep
->sigcontext_addr
== NULL
)
2675 if (tdep
->sigtramp_p
!= NULL
)
2677 if (tdep
->sigtramp_p (this_frame
))
2681 if (tdep
->sigtramp_start
!= 0)
2683 CORE_ADDR pc
= get_frame_pc (this_frame
);
2685 gdb_assert (tdep
->sigtramp_end
!= 0);
2686 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2693 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
2696 amd64_sigtramp_frame_unwind_stop_reason
,
2697 amd64_sigtramp_frame_this_id
,
2698 amd64_sigtramp_frame_prev_register
,
2700 amd64_sigtramp_frame_sniffer
2705 amd64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2707 struct amd64_frame_cache
*cache
=
2708 amd64_frame_cache (this_frame
, this_cache
);
2713 static const struct frame_base amd64_frame_base
=
2715 &amd64_frame_unwind
,
2716 amd64_frame_base_address
,
2717 amd64_frame_base_address
,
2718 amd64_frame_base_address
2721 /* Normal frames, but in a function epilogue. */
2723 /* Implement the stack_frame_destroyed_p gdbarch method.
2725 The epilogue is defined here as the 'ret' instruction, which will
2726 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2727 the function's stack frame. */
2730 amd64_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2733 struct compunit_symtab
*cust
;
2735 cust
= find_pc_compunit_symtab (pc
);
2736 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2739 if (target_read_memory (pc
, &insn
, 1))
2740 return 0; /* Can't read memory at pc. */
2742 if (insn
!= 0xc3) /* 'ret' instruction. */
2749 amd64_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2750 struct frame_info
*this_frame
,
2751 void **this_prologue_cache
)
2753 if (frame_relative_level (this_frame
) == 0)
2754 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2755 get_frame_pc (this_frame
));
2760 static struct amd64_frame_cache
*
2761 amd64_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2763 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2764 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2765 struct amd64_frame_cache
*cache
;
2769 return (struct amd64_frame_cache
*) *this_cache
;
2771 cache
= amd64_alloc_frame_cache ();
2772 *this_cache
= cache
;
2776 /* Cache base will be %esp plus cache->sp_offset (-8). */
2777 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2778 cache
->base
= extract_unsigned_integer (buf
, 8,
2779 byte_order
) + cache
->sp_offset
;
2781 /* Cache pc will be the frame func. */
2782 cache
->pc
= get_frame_pc (this_frame
);
2784 /* The saved %esp will be at cache->base plus 16. */
2785 cache
->saved_sp
= cache
->base
+ 16;
2787 /* The saved %eip will be at cache->base plus 8. */
2788 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->base
+ 8;
2792 CATCH (ex
, RETURN_MASK_ERROR
)
2794 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2795 throw_exception (ex
);
2802 static enum unwind_stop_reason
2803 amd64_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2806 struct amd64_frame_cache
*cache
2807 = amd64_epilogue_frame_cache (this_frame
, this_cache
);
2810 return UNWIND_UNAVAILABLE
;
2812 return UNWIND_NO_REASON
;
2816 amd64_epilogue_frame_this_id (struct frame_info
*this_frame
,
2818 struct frame_id
*this_id
)
2820 struct amd64_frame_cache
*cache
= amd64_epilogue_frame_cache (this_frame
,
2824 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2826 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2829 static const struct frame_unwind amd64_epilogue_frame_unwind
=
2832 amd64_epilogue_frame_unwind_stop_reason
,
2833 amd64_epilogue_frame_this_id
,
2834 amd64_frame_prev_register
,
2836 amd64_epilogue_frame_sniffer
2839 static struct frame_id
2840 amd64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2844 fp
= get_frame_register_unsigned (this_frame
, AMD64_RBP_REGNUM
);
2846 return frame_id_build (fp
+ 16, get_frame_pc (this_frame
));
2849 /* 16 byte align the SP per frame requirements. */
2852 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2854 return sp
& -(CORE_ADDR
)16;
2858 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2859 in the floating-point register set REGSET to register cache
2860 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2863 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2864 int regnum
, const void *fpregs
, size_t len
)
2866 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2867 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2869 gdb_assert (len
>= tdep
->sizeof_fpregset
);
2870 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
2873 /* Collect register REGNUM from the register cache REGCACHE and store
2874 it in the buffer specified by FPREGS and LEN as described by the
2875 floating-point register set REGSET. If REGNUM is -1, do this for
2876 all registers in REGSET. */
2879 amd64_collect_fpregset (const struct regset
*regset
,
2880 const struct regcache
*regcache
,
2881 int regnum
, void *fpregs
, size_t len
)
2883 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2884 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2886 gdb_assert (len
>= tdep
->sizeof_fpregset
);
2887 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
2890 const struct regset amd64_fpregset
=
2892 NULL
, amd64_supply_fpregset
, amd64_collect_fpregset
2896 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2897 %rdi. We expect its value to be a pointer to the jmp_buf structure
2898 from which we extract the address that we will land at. This
2899 address is copied into PC. This routine returns non-zero on
2903 amd64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2907 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2908 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2909 int len
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_func_ptr
);
2911 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2912 longjmp will land. */
2913 if (jb_pc_offset
== -1)
2916 get_frame_register (frame
, AMD64_RDI_REGNUM
, buf
);
2917 jb_addr
= extract_typed_address
2918 (buf
, builtin_type (gdbarch
)->builtin_data_ptr
);
2919 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, len
))
2922 *pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
2927 static const int amd64_record_regmap
[] =
2929 AMD64_RAX_REGNUM
, AMD64_RCX_REGNUM
, AMD64_RDX_REGNUM
, AMD64_RBX_REGNUM
,
2930 AMD64_RSP_REGNUM
, AMD64_RBP_REGNUM
, AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
2931 AMD64_R8_REGNUM
, AMD64_R9_REGNUM
, AMD64_R10_REGNUM
, AMD64_R11_REGNUM
,
2932 AMD64_R12_REGNUM
, AMD64_R13_REGNUM
, AMD64_R14_REGNUM
, AMD64_R15_REGNUM
,
2933 AMD64_RIP_REGNUM
, AMD64_EFLAGS_REGNUM
, AMD64_CS_REGNUM
, AMD64_SS_REGNUM
,
2934 AMD64_DS_REGNUM
, AMD64_ES_REGNUM
, AMD64_FS_REGNUM
, AMD64_GS_REGNUM
2938 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2940 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2941 const struct target_desc
*tdesc
= info
.target_desc
;
2942 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
2943 static const char *const stap_register_prefixes
[] = { "%", NULL
};
2944 static const char *const stap_register_indirection_prefixes
[] = { "(",
2946 static const char *const stap_register_indirection_suffixes
[] = { ")",
2949 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
2950 floating-point registers. */
2951 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
2952 tdep
->fpregset
= &amd64_fpregset
;
2954 if (! tdesc_has_registers (tdesc
))
2955 tdesc
= tdesc_amd64
;
2956 tdep
->tdesc
= tdesc
;
2958 tdep
->num_core_regs
= AMD64_NUM_GREGS
+ I387_NUM_REGS
;
2959 tdep
->register_names
= amd64_register_names
;
2961 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512") != NULL
)
2963 tdep
->zmmh_register_names
= amd64_zmmh_names
;
2964 tdep
->k_register_names
= amd64_k_names
;
2965 tdep
->xmm_avx512_register_names
= amd64_xmm_avx512_names
;
2966 tdep
->ymm16h_register_names
= amd64_ymmh_avx512_names
;
2968 tdep
->num_zmm_regs
= 32;
2969 tdep
->num_xmm_avx512_regs
= 16;
2970 tdep
->num_ymm_avx512_regs
= 16;
2972 tdep
->zmm0h_regnum
= AMD64_ZMM0H_REGNUM
;
2973 tdep
->k0_regnum
= AMD64_K0_REGNUM
;
2974 tdep
->xmm16_regnum
= AMD64_XMM16_REGNUM
;
2975 tdep
->ymm16h_regnum
= AMD64_YMM16H_REGNUM
;
2978 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx") != NULL
)
2980 tdep
->ymmh_register_names
= amd64_ymmh_names
;
2981 tdep
->num_ymm_regs
= 16;
2982 tdep
->ymm0h_regnum
= AMD64_YMM0H_REGNUM
;
2985 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
)
2987 tdep
->mpx_register_names
= amd64_mpx_names
;
2988 tdep
->bndcfgu_regnum
= AMD64_BNDCFGU_REGNUM
;
2989 tdep
->bnd0r_regnum
= AMD64_BND0R_REGNUM
;
2992 tdep
->num_byte_regs
= 20;
2993 tdep
->num_word_regs
= 16;
2994 tdep
->num_dword_regs
= 16;
2995 /* Avoid wiring in the MMX registers for now. */
2996 tdep
->num_mmx_regs
= 0;
2998 set_gdbarch_pseudo_register_read_value (gdbarch
,
2999 amd64_pseudo_register_read_value
);
3000 set_gdbarch_pseudo_register_write (gdbarch
,
3001 amd64_pseudo_register_write
);
3003 set_tdesc_pseudo_register_name (gdbarch
, amd64_pseudo_register_name
);
3005 /* AMD64 has an FPU and 16 SSE registers. */
3006 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
3007 tdep
->num_xmm_regs
= 16;
3009 /* This is what all the fuss is about. */
3010 set_gdbarch_long_bit (gdbarch
, 64);
3011 set_gdbarch_long_long_bit (gdbarch
, 64);
3012 set_gdbarch_ptr_bit (gdbarch
, 64);
3014 /* In contrast to the i386, on AMD64 a `long double' actually takes
3015 up 128 bits, even though it's still based on the i387 extended
3016 floating-point format which has only 80 significant bits. */
3017 set_gdbarch_long_double_bit (gdbarch
, 128);
3019 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
3021 /* Register numbers of various important registers. */
3022 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
3023 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
3024 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
3025 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
3027 /* The "default" register numbering scheme for AMD64 is referred to
3028 as the "DWARF Register Number Mapping" in the System V psABI.
3029 The preferred debugging format for all known AMD64 targets is
3030 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3031 DWARF-1), but we provide the same mapping just in case. This
3032 mapping is also used for stabs, which GCC does support. */
3033 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3034 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3036 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
3037 be in use on any of the supported AMD64 targets. */
3039 /* Call dummy code. */
3040 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
3041 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
3042 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
3044 set_gdbarch_convert_register_p (gdbarch
, i387_convert_register_p
);
3045 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
3046 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
3048 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
3050 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
3052 tdep
->record_regmap
= amd64_record_regmap
;
3054 set_gdbarch_dummy_id (gdbarch
, amd64_dummy_id
);
3056 /* Hook the function epilogue frame unwinder. This unwinder is
3057 appended to the list first, so that it supercedes the other
3058 unwinders in function epilogues. */
3059 frame_unwind_prepend_unwinder (gdbarch
, &amd64_epilogue_frame_unwind
);
3061 /* Hook the prologue-based frame unwinders. */
3062 frame_unwind_append_unwinder (gdbarch
, &amd64_sigtramp_frame_unwind
);
3063 frame_unwind_append_unwinder (gdbarch
, &amd64_frame_unwind
);
3064 frame_base_set_default (gdbarch
, &amd64_frame_base
);
3066 set_gdbarch_get_longjmp_target (gdbarch
, amd64_get_longjmp_target
);
3068 set_gdbarch_relocate_instruction (gdbarch
, amd64_relocate_instruction
);
3070 set_gdbarch_gen_return_address (gdbarch
, amd64_gen_return_address
);
3072 /* SystemTap variables and functions. */
3073 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
3074 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
3075 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
3076 stap_register_indirection_prefixes
);
3077 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
3078 stap_register_indirection_suffixes
);
3079 set_gdbarch_stap_is_single_operand (gdbarch
,
3080 i386_stap_is_single_operand
);
3081 set_gdbarch_stap_parse_special_token (gdbarch
,
3082 i386_stap_parse_special_token
);
3083 set_gdbarch_insn_is_call (gdbarch
, amd64_insn_is_call
);
3084 set_gdbarch_insn_is_ret (gdbarch
, amd64_insn_is_ret
);
3085 set_gdbarch_insn_is_jump (gdbarch
, amd64_insn_is_jump
);
3089 static struct type
*
3090 amd64_x32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3092 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3094 switch (regnum
- tdep
->eax_regnum
)
3096 case AMD64_RBP_REGNUM
: /* %ebp */
3097 case AMD64_RSP_REGNUM
: /* %esp */
3098 return builtin_type (gdbarch
)->builtin_data_ptr
;
3099 case AMD64_RIP_REGNUM
: /* %eip */
3100 return builtin_type (gdbarch
)->builtin_func_ptr
;
3103 return i386_pseudo_register_type (gdbarch
, regnum
);
3107 amd64_x32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3109 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3110 const struct target_desc
*tdesc
= info
.target_desc
;
3112 amd64_init_abi (info
, gdbarch
);
3114 if (! tdesc_has_registers (tdesc
))
3116 tdep
->tdesc
= tdesc
;
3118 tdep
->num_dword_regs
= 17;
3119 set_tdesc_pseudo_register_type (gdbarch
, amd64_x32_pseudo_register_type
);
3121 set_gdbarch_long_bit (gdbarch
, 32);
3122 set_gdbarch_ptr_bit (gdbarch
, 32);
3125 /* Return the target description for a specified XSAVE feature mask. */
3127 const struct target_desc
*
3128 amd64_target_description (uint64_t xcr0
)
3130 switch (xcr0
& X86_XSTATE_ALL_MASK
)
3132 case X86_XSTATE_MPX_AVX512_MASK
:
3133 case X86_XSTATE_AVX512_MASK
:
3134 return tdesc_amd64_avx512
;
3135 case X86_XSTATE_MPX_MASK
:
3136 return tdesc_amd64_mpx
;
3137 case X86_XSTATE_AVX_MASK
:
3138 return tdesc_amd64_avx
;
3144 /* Provide a prototype to silence -Wmissing-prototypes. */
3145 void _initialize_amd64_tdep (void);
3148 _initialize_amd64_tdep (void)
3150 initialize_tdesc_amd64 ();
3151 initialize_tdesc_amd64_avx ();
3152 initialize_tdesc_amd64_mpx ();
3153 initialize_tdesc_amd64_avx512 ();
3155 initialize_tdesc_x32 ();
3156 initialize_tdesc_x32_avx ();
3157 initialize_tdesc_x32_avx512 ();
3161 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3162 sense that the instruction pointer and data pointer are simply
3163 64-bit offsets into the code segment and the data segment instead
3164 of a selector offset pair. The functions below store the upper 32
3165 bits of these pointers (instead of just the 16-bits of the segment
3168 /* Fill register REGNUM in REGCACHE with the appropriate
3169 floating-point or SSE register value from *FXSAVE. If REGNUM is
3170 -1, do this for all registers. This function masks off any of the
3171 reserved bits in *FXSAVE. */
3174 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
3177 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3178 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3180 i387_supply_fxsave (regcache
, regnum
, fxsave
);
3183 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3185 const gdb_byte
*regs
= (const gdb_byte
*) fxsave
;
3187 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3188 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
3189 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3190 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3194 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3197 amd64_supply_xsave (struct regcache
*regcache
, int regnum
,
3200 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3201 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3203 i387_supply_xsave (regcache
, regnum
, xsave
);
3206 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3208 const gdb_byte
*regs
= (const gdb_byte
*) xsave
;
3210 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3211 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
),
3213 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3214 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
),
3219 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3220 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3221 all registers. This function doesn't touch any of the reserved
3225 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
3228 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3229 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3230 gdb_byte
*regs
= (gdb_byte
*) fxsave
;
3232 i387_collect_fxsave (regcache
, regnum
, fxsave
);
3234 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3236 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3237 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
3238 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3239 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3243 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3246 amd64_collect_xsave (const struct regcache
*regcache
, int regnum
,
3247 void *xsave
, int gcore
)
3249 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3250 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3251 gdb_byte
*regs
= (gdb_byte
*) xsave
;
3253 i387_collect_xsave (regcache
, regnum
, xsave
, gcore
);
3255 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3257 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3258 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
),
3260 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3261 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
),