gdb/arc-tdep.c

   1 /* ARC target-dependent stuff.
   2    Copyright 1995, 1996, 1999, 2000, 2001 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 2 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 59 Temple Place - Suite 330,
  19    Boston, MA 02111-1307, USA.  */
  20
  21 #include "defs.h"
  22 #include "frame.h"
  23 #include "inferior.h"
  24 #include "gdbcore.h"
  25 #include "target.h"
  26 #include "floatformat.h"
  27 #include "symtab.h"
  28 #include "gdbcmd.h"
  29 #include "regcache.h"
  30
  31 /* Local functions */
  32
  33 static int arc_set_cpu_type (char *str);
  34
  35 /* Current CPU, set with the "set cpu" command.  */
  36 static int arc_bfd_mach_type;
  37 char *arc_cpu_type;
  38 char *tmp_arc_cpu_type;
  39
  40 /* Table of cpu names.  */
  41 struct
  42   {
  43     char *name;
  44     int value;
  45   }
  46 arc_cpu_type_table[] =
  47 {
  48   { "arc5", bfd_mach_arc_5 },
  49   { "arc6", bfd_mach_arc_6 },
  50   { "arc7", bfd_mach_arc_7 },
  51   { "arc8", bfd_mach_arc_8 },
  52   {  NULL,  0 }
  53 };
  54
  55 /* Used by simulator.  */
  56 int display_pipeline_p;
  57 int cpu_timer;
  58 /* This one must have the same type as used in the emulator.
  59    It's currently an enum so this should be ok for now.  */
  60 int debug_pipeline_p;
  61
  62 #define ARC_CALL_SAVED_REG(r) ((r) >= 16 && (r) < 24)
  63
  64 #define OPMASK  0xf8000000
  65
  66 /* Instruction field accessor macros.
  67    See the Programmer's Reference Manual.  */
  68 #define X_OP(i) (((i) >> 27) & 0x1f)
  69 #define X_A(i) (((i) >> 21) & 0x3f)
  70 #define X_B(i) (((i) >> 15) & 0x3f)
  71 #define X_C(i) (((i) >> 9) & 0x3f)
  72 #define X_D(i) ((((i) & 0x1ff) ^ 0x100) - 0x100)
  73 #define X_L(i) (((((i) >> 5) & 0x3ffffc) ^ 0x200000) - 0x200000)
  74 #define X_N(i) (((i) >> 5) & 3)
  75 #define X_Q(i) ((i) & 0x1f)
  76
  77 /* Return non-zero if X is a short immediate data indicator.  */
  78 #define SHIMM_P(x) ((x) == 61 || (x) == 63)
  79
  80 /* Return non-zero if X is a "long" (32 bit) immediate data indicator.  */
  81 #define LIMM_P(x) ((x) == 62)
  82
  83 /* Build a simple instruction.  */
  84 #define BUILD_INSN(op, a, b, c, d) \
  85   ((((op) & 31) << 27) \
  86    | (((a) & 63) << 21) \
  87    | (((b) & 63) << 15) \
  88    | (((c) & 63) << 9) \
  89    | ((d) & 511))
  90 \f
  91 /* Codestream stuff.  */
  92 static void codestream_read (unsigned int *, int);
  93 static void codestream_seek (CORE_ADDR);
  94 static unsigned int codestream_fill (int);
  95
  96 #define CODESTREAM_BUFSIZ 16
  97 static CORE_ADDR codestream_next_addr;
  98 static CORE_ADDR codestream_addr;
  99 /* FIXME assumes sizeof (int) == 32? */
 100 static unsigned int codestream_buf[CODESTREAM_BUFSIZ];
 101 static int codestream_off;
 102 static int codestream_cnt;
 103
 104 #define codestream_tell() \
 105   (codestream_addr + codestream_off * sizeof (codestream_buf[0]))
 106 #define codestream_peek() \
 107   (codestream_cnt == 0 \
 108    ? codestream_fill (1) \
 109    : codestream_buf[codestream_off])
 110 #define codestream_get() \
 111   (codestream_cnt-- == 0 \
 112    ? codestream_fill (0) \
 113    : codestream_buf[codestream_off++])
 114
 115 static unsigned int
 116 codestream_fill (int peek_flag)
 117 {
 118   codestream_addr = codestream_next_addr;
 119   codestream_next_addr += CODESTREAM_BUFSIZ * sizeof (codestream_buf[0]);
 120   codestream_off = 0;
 121   codestream_cnt = CODESTREAM_BUFSIZ;
 122   read_memory (codestream_addr, (char *) codestream_buf,
 123                CODESTREAM_BUFSIZ * sizeof (codestream_buf[0]));
 124   /* FIXME: check return code?  */
 125
 126
 127   /* Handle byte order differences -> convert to host byte ordering.  */
 128   {
 129     int i;
 130     for (i = 0; i < CODESTREAM_BUFSIZ; i++)
 131       codestream_buf[i] =
 132         extract_unsigned_integer (&codestream_buf[i],
 133                                   sizeof (codestream_buf[i]));
 134   }
 135
 136   if (peek_flag)
 137     return codestream_peek ();
 138   else
 139     return codestream_get ();
 140 }
 141
 142 static void
 143 codestream_seek (CORE_ADDR place)
 144 {
 145   codestream_next_addr = place / CODESTREAM_BUFSIZ;
 146   codestream_next_addr *= CODESTREAM_BUFSIZ;
 147   codestream_cnt = 0;
 148   codestream_fill (1);
 149   while (codestream_tell () != place)
 150     codestream_get ();
 151 }
 152
 153 /* This function is currently unused but leave in for now.  */
 154
 155 static void
 156 codestream_read (unsigned int *buf, int count)
 157 {
 158   unsigned int *p;
 159   int i;
 160   p = buf;
 161   for (i = 0; i < count; i++)
 162     *p++ = codestream_get ();
 163 }
 164 \f
 165 /* Set up prologue scanning and return the first insn.  */
 166
 167 static unsigned int
 168 setup_prologue_scan (CORE_ADDR pc)
 169 {
 170   unsigned int insn;
 171
 172   codestream_seek (pc);
 173   insn = codestream_get ();
 174
 175   return insn;
 176 }
 177
 178 /*
 179  * Find & return amount a local space allocated, and advance codestream to
 180  * first register push (if any).
 181  * If entry sequence doesn't make sense, return -1, and leave
 182  * codestream pointer random.
 183  */
 184
 185 static long
 186 arc_get_frame_setup (CORE_ADDR pc)
 187 {
 188   unsigned int insn;
 189   /* Size of frame or -1 if unrecognizable prologue.  */
 190   int frame_size = -1;
 191   /* An initial "sub sp,sp,N" may or may not be for a stdarg fn.  */
 192   int maybe_stdarg_decr = -1;
 193
 194   insn = setup_prologue_scan (pc);
 195
 196   /* The authority for what appears here is the home-grown ABI.
 197      The most recent version is 1.2.  */
 198
 199   /* First insn may be "sub sp,sp,N" if stdarg fn.  */
 200   if ((insn & BUILD_INSN (-1, -1, -1, -1, 0))
 201       == BUILD_INSN (10, SP_REGNUM, SP_REGNUM, SHIMM_REGNUM, 0))
 202     {
 203       maybe_stdarg_decr = X_D (insn);
 204       insn = codestream_get ();
 205     }
 206
 207   if ((insn & BUILD_INSN (-1, 0, -1, -1, -1))   /* st blink,[sp,4] */
 208       == BUILD_INSN (2, 0, SP_REGNUM, BLINK_REGNUM, 4))
 209     {
 210       insn = codestream_get ();
 211       /* Frame may not be necessary, even though blink is saved.
 212          At least this is something we recognize.  */
 213       frame_size = 0;
 214     }
 215
 216   if ((insn & BUILD_INSN (-1, 0, -1, -1, -1))   /* st fp,[sp] */
 217       == BUILD_INSN (2, 0, SP_REGNUM, FP_REGNUM, 0))
 218     {
 219       insn = codestream_get ();
 220       if ((insn & BUILD_INSN (-1, -1, -1, -1, 0))
 221           != BUILD_INSN (12, FP_REGNUM, SP_REGNUM, SP_REGNUM, 0))
 222         return -1;
 223
 224       /* Check for stack adjustment sub sp,sp,N.  */
 225       insn = codestream_peek ();
 226       if ((insn & BUILD_INSN (-1, -1, -1, 0, 0))
 227           == BUILD_INSN (10, SP_REGNUM, SP_REGNUM, 0, 0))
 228         {
 229           if (LIMM_P (X_C (insn)))
 230             frame_size = codestream_get ();
 231           else if (SHIMM_P (X_C (insn)))
 232             frame_size = X_D (insn);
 233           else
 234             return -1;
 235           if (frame_size < 0)
 236             return -1;
 237
 238           codestream_get ();
 239
 240           /* This sequence is used to get the address of the return
 241              buffer for a function that returns a structure.  */
 242           insn = codestream_peek ();
 243           if ((insn & OPMASK) == 0x60000000)
 244             codestream_get ();
 245         }
 246       /* Frameless fn.  */
 247       else
 248         {
 249           frame_size = 0;
 250         }
 251     }
 252
 253   /* If we found a "sub sp,sp,N" and nothing else, it may or may not be a
 254      stdarg fn.  The stdarg decrement is not treated as part of the frame size,
 255      so we have a dilemma: what do we return?  For now, if we get a
 256      "sub sp,sp,N" and nothing else assume this isn't a stdarg fn.  One way
 257      to fix this completely would be to add a bit to the function descriptor
 258      that says the function is a stdarg function.  */
 259
 260   if (frame_size < 0 && maybe_stdarg_decr > 0)
 261     return maybe_stdarg_decr;
 262   return frame_size;
 263 }
 264
 265 /* Given a pc value, skip it forward past the function prologue by
 266    disassembling instructions that appear to be a prologue.
 267
 268    If FRAMELESS_P is set, we are only testing to see if the function
 269    is frameless.  If it is a frameless function, return PC unchanged.
 270    This allows a quicker answer.  */
 271
 272 CORE_ADDR
 273 arc_skip_prologue (CORE_ADDR pc, int frameless_p)
 274 {
 275   unsigned int insn;
 276   int i, frame_size;
 277
 278   if ((frame_size = arc_get_frame_setup (pc)) < 0)
 279     return (pc);
 280
 281   if (frameless_p)
 282     return frame_size == 0 ? pc : codestream_tell ();
 283
 284   /* Skip over register saves.  */
 285   for (i = 0; i < 8; i++)
 286     {
 287       insn = codestream_peek ();
 288       if ((insn & BUILD_INSN (-1, 0, -1, 0, 0))
 289           != BUILD_INSN (2, 0, SP_REGNUM, 0, 0))
 290         break;                  /* not st insn */
 291       if (!ARC_CALL_SAVED_REG (X_C (insn)))
 292         break;
 293       codestream_get ();
 294     }
 295
 296   return codestream_tell ();
 297 }
 298
 299 /* Is the prologue at PC frameless?  */
 300
 301 int
 302 arc_prologue_frameless_p (CORE_ADDR pc)
 303 {
 304   return (pc == arc_skip_prologue (pc, 1));
 305 }
 306
 307 /* Return the return address for a frame.
 308    This is used to implement FRAME_SAVED_PC.
 309    This is taken from frameless_look_for_prologue.  */
 310
 311 CORE_ADDR
 312 arc_frame_saved_pc (struct frame_info *frame)
 313 {
 314   CORE_ADDR func_start;
 315   unsigned int insn;
 316
 317   func_start = get_pc_function_start (frame->pc) + FUNCTION_START_OFFSET;
 318   if (func_start == 0)
 319     {
 320       /* Best guess.  */
 321       return ARC_PC_TO_REAL_ADDRESS (read_memory_integer (FRAME_FP (frame) + 4, 4));
 322     }
 323
 324   /* The authority for what appears here is the home-grown ABI.
 325      The most recent version is 1.2.  */
 326
 327   insn = setup_prologue_scan (func_start);
 328
 329   /* First insn may be "sub sp,sp,N" if stdarg fn.  */
 330   if ((insn & BUILD_INSN (-1, -1, -1, -1, 0))
 331       == BUILD_INSN (10, SP_REGNUM, SP_REGNUM, SHIMM_REGNUM, 0))
 332     insn = codestream_get ();
 333
 334   /* If the next insn is "st blink,[sp,4]" we can get blink from there.
 335      Otherwise this is a leaf function and we can use blink.  Note that
 336      this still allows for the case where a leaf function saves/clobbers/
 337      restores blink.  */
 338
 339   if ((insn & BUILD_INSN (-1, 0, -1, -1, -1))   /* st blink,[sp,4] */
 340       != BUILD_INSN (2, 0, SP_REGNUM, BLINK_REGNUM, 4))
 341     return ARC_PC_TO_REAL_ADDRESS (read_register (BLINK_REGNUM));
 342   else
 343     return ARC_PC_TO_REAL_ADDRESS (read_memory_integer (FRAME_FP (frame) + 4, 4));
 344 }
 345
 346 /*
 347  * Parse the first few instructions of the function to see
 348  * what registers were stored.
 349  *
 350  * The startup sequence can be at the start of the function.
 351  * 'st blink,[sp+4], st fp,[sp], mov fp,sp'
 352  *
 353  * Local space is allocated just below by sub sp,sp,nnn.
 354  * Next, the registers used by this function are stored (as offsets from sp).
 355  */
 356
 357 void
 358 frame_find_saved_regs (struct frame_info *fip, struct frame_saved_regs *fsrp)
 359 {
 360   long locals;
 361   unsigned int insn;
 362   CORE_ADDR dummy_bottom;
 363   CORE_ADDR adr;
 364   int i, regnum, offset;
 365
 366   memset (fsrp, 0, sizeof *fsrp);
 367
 368   /* If frame is the end of a dummy, compute where the beginning would be.  */
 369   dummy_bottom = fip->frame - 4 - REGISTER_BYTES - CALL_DUMMY_LENGTH;
 370
 371   /* Check if the PC is in the stack, in a dummy frame.  */
 372   if (dummy_bottom <= fip->pc && fip->pc <= fip->frame)
 373     {
 374       /* all regs were saved by push_call_dummy () */
 375       adr = fip->frame;
 376       for (i = 0; i < NUM_REGS; i++)
 377         {
 378           adr -= REGISTER_RAW_SIZE (i);
 379           fsrp->regs[i] = adr;
 380         }
 381       return;
 382     }
 383
 384   locals = arc_get_frame_setup (get_pc_function_start (fip->pc));
 385
 386   if (locals >= 0)
 387     {
 388       /* Set `adr' to the value of `sp'.  */
 389       adr = fip->frame - locals;
 390       for (i = 0; i < 8; i++)
 391         {
 392           insn = codestream_get ();
 393           if ((insn & BUILD_INSN (-1, 0, -1, 0, 0))
 394               != BUILD_INSN (2, 0, SP_REGNUM, 0, 0))
 395             break;
 396           regnum = X_C (insn);
 397           offset = X_D (insn);
 398           fsrp->regs[regnum] = adr + offset;
 399         }
 400     }
 401
 402   fsrp->regs[PC_REGNUM] = fip->frame + 4;
 403   fsrp->regs[FP_REGNUM] = fip->frame;
 404 }
 405
 406 void
 407 arc_push_dummy_frame (void)
 408 {
 409   CORE_ADDR sp = read_register (SP_REGNUM);
 410   int regnum;
 411   char regbuf[MAX_REGISTER_RAW_SIZE];
 412
 413   read_register_gen (PC_REGNUM, regbuf);
 414   write_memory (sp + 4, regbuf, REGISTER_SIZE);
 415   read_register_gen (FP_REGNUM, regbuf);
 416   write_memory (sp, regbuf, REGISTER_SIZE);
 417   write_register (FP_REGNUM, sp);
 418   for (regnum = 0; regnum < NUM_REGS; regnum++)
 419     {
 420       read_register_gen (regnum, regbuf);
 421       sp = push_bytes (sp, regbuf, REGISTER_RAW_SIZE (regnum));
 422     }
 423   sp += (2 * REGISTER_SIZE);
 424   write_register (SP_REGNUM, sp);
 425 }
 426
 427 void
 428 arc_pop_frame (void)
 429 {
 430   struct frame_info *frame = get_current_frame ();
 431   CORE_ADDR fp;
 432   int regnum;
 433   struct frame_saved_regs fsr;
 434   char regbuf[MAX_REGISTER_RAW_SIZE];
 435
 436   fp = FRAME_FP (frame);
 437   get_frame_saved_regs (frame, &fsr);
 438   for (regnum = 0; regnum < NUM_REGS; regnum++)
 439     {
 440       CORE_ADDR adr;
 441       adr = fsr.regs[regnum];
 442       if (adr)
 443         {
 444           read_memory (adr, regbuf, REGISTER_RAW_SIZE (regnum));
 445           write_register_bytes (REGISTER_BYTE (regnum), regbuf,
 446                                 REGISTER_RAW_SIZE (regnum));
 447         }
 448     }
 449   write_register (FP_REGNUM, read_memory_integer (fp, 4));
 450   write_register (PC_REGNUM, read_memory_integer (fp + 4, 4));
 451   write_register (SP_REGNUM, fp + 8);
 452   flush_cached_frames ();
 453 }
 454 \f
 455 /* Simulate single-step.  */
 456
 457 typedef enum
 458 {
 459   NORMAL4,                      /* a normal 4 byte insn */
 460   NORMAL8,                      /* a normal 8 byte insn */
 461   BRANCH4,                      /* a 4 byte branch insn, including ones without delay slots */
 462   BRANCH8,                      /* an 8 byte branch insn, including ones with delay slots */
 463 }
 464 insn_type;
 465
 466 /* Return the type of INSN and store in TARGET the destination address of a
 467    branch if this is one.  */
 468 /* ??? Need to verify all cases are properly handled.  */
 469
 470 static insn_type
 471 get_insn_type (unsigned long insn, CORE_ADDR pc, CORE_ADDR *target)
 472 {
 473   unsigned long limm;
 474
 475   switch (insn >> 27)
 476     {
 477     case 0:
 478     case 1:
 479     case 2:                     /* load/store insns */
 480       if (LIMM_P (X_A (insn))
 481           || LIMM_P (X_B (insn))
 482           || LIMM_P (X_C (insn)))
 483         return NORMAL8;
 484       return NORMAL4;
 485     case 4:
 486     case 5:
 487     case 6:                     /* branch insns */
 488       *target = pc + 4 + X_L (insn);
 489       /* ??? It isn't clear that this is always the right answer.
 490          The problem occurs when the next insn is an 8 byte insn.  If the
 491          branch is conditional there's no worry as there shouldn't be an 8
 492          byte insn following.  The programmer may be cheating if s/he knows
 493          the branch will never be taken, but we don't deal with that.
 494          Note that the programmer is also allowed to play games by putting
 495          an insn with long immediate data in the delay slot and then duplicate
 496          the long immediate data at the branch target.  Ugh!  */
 497       if (X_N (insn) == 0)
 498         return BRANCH4;
 499       return BRANCH8;
 500     case 7:                     /* jump insns */
 501       if (LIMM_P (X_B (insn)))
 502         {
 503           limm = read_memory_integer (pc + 4, 4);
 504           *target = ARC_PC_TO_REAL_ADDRESS (limm);
 505           return BRANCH8;
 506         }
 507       if (SHIMM_P (X_B (insn)))
 508         *target = ARC_PC_TO_REAL_ADDRESS (X_D (insn));
 509       else
 510         *target = ARC_PC_TO_REAL_ADDRESS (read_register (X_B (insn)));
 511       if (X_Q (insn) == 0 && X_N (insn) == 0)
 512         return BRANCH4;
 513       return BRANCH8;
 514     default:                    /* arithmetic insns, etc. */
 515       if (LIMM_P (X_A (insn))
 516           || LIMM_P (X_B (insn))
 517           || LIMM_P (X_C (insn)))
 518         return NORMAL8;
 519       return NORMAL4;
 520     }
 521 }
 522
 523 /* single_step() is called just before we want to resume the inferior, if we
 524    want to single-step it but there is no hardware or kernel single-step
 525    support.  We find all the possible targets of the coming instruction and
 526    breakpoint them.
 527
 528    single_step is also called just after the inferior stops.  If we had
 529    set up a simulated single-step, we undo our damage.  */
 530
 531 void
 532 arc_software_single_step (enum target_signal ignore,    /* sig but we don't need it */
 533                           int insert_breakpoints_p)
 534 {
 535   static CORE_ADDR next_pc, target;
 536   static int brktrg_p;
 537   typedef char binsn_quantum[BREAKPOINT_MAX];
 538   static binsn_quantum break_mem[2];
 539
 540   if (insert_breakpoints_p)
 541     {
 542       insn_type type;
 543       CORE_ADDR pc;
 544       unsigned long insn;
 545
 546       pc = read_register (PC_REGNUM);
 547       insn = read_memory_integer (pc, 4);
 548       type = get_insn_type (insn, pc, &target);
 549
 550       /* Always set a breakpoint for the insn after the branch.  */
 551       next_pc = pc + ((type == NORMAL8 || type == BRANCH8) ? 8 : 4);
 552       target_insert_breakpoint (next_pc, break_mem[0]);
 553
 554       brktrg_p = 0;
 555
 556       if ((type == BRANCH4 || type == BRANCH8)
 557       /* Watch out for branches to the following location.
 558          We just stored a breakpoint there and another call to
 559          target_insert_breakpoint will think the real insn is the
 560          breakpoint we just stored there.  */
 561           && target != next_pc)
 562         {
 563           brktrg_p = 1;
 564           target_insert_breakpoint (target, break_mem[1]);
 565         }
 566
 567     }
 568   else
 569     {
 570       /* Remove breakpoints.  */
 571       target_remove_breakpoint (next_pc, break_mem[0]);
 572
 573       if (brktrg_p)
 574         target_remove_breakpoint (target, break_mem[1]);
 575
 576       /* Fix the pc.  */
 577       stop_pc -= DECR_PC_AFTER_BREAK;
 578       write_pc (stop_pc);
 579     }
 580 }
 581 \f
 582 /* Because of Multi-arch, GET_LONGJMP_TARGET is always defined.  So test
 583    for a definition of JB_PC.  */
 584 #ifdef JB_PC
 585 /* Figure out where the longjmp will land.  Slurp the args out of the stack.
 586    We expect the first arg to be a pointer to the jmp_buf structure from which
 587    we extract the pc (JB_PC) that we will land at.  The pc is copied into PC.
 588    This routine returns true on success. */
 589
 590 int
 591 get_longjmp_target (CORE_ADDR *pc)
 592 {
 593   char buf[TARGET_PTR_BIT / TARGET_CHAR_BIT];
 594   CORE_ADDR sp, jb_addr;
 595
 596   sp = read_register (SP_REGNUM);
 597
 598   if (target_read_memory (sp + SP_ARG0,         /* Offset of first arg on stack */
 599                           buf,
 600                           TARGET_PTR_BIT / TARGET_CHAR_BIT))
 601     return 0;
 602
 603   jb_addr = extract_address (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
 604
 605   if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf,
 606                           TARGET_PTR_BIT / TARGET_CHAR_BIT))
 607     return 0;
 608
 609   *pc = extract_address (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
 610
 611   return 1;
 612 }
 613 #endif /* GET_LONGJMP_TARGET */
 614 \f
 615 /* Disassemble one instruction.  */
 616
 617 static int
 618 arc_print_insn (bfd_vma vma, disassemble_info *info)
 619 {
 620   static int current_mach;
 621   static int current_endian;
 622   static disassembler_ftype current_disasm;
 623
 624   if (current_disasm == NULL
 625       || arc_bfd_mach_type != current_mach
 626       || TARGET_BYTE_ORDER != current_endian)
 627     {
 628       current_mach = arc_bfd_mach_type;
 629       current_endian = TARGET_BYTE_ORDER;
 630       current_disasm = arc_get_disassembler (NULL);
 631     }
 632
 633   return (*current_disasm) (vma, info);
 634 }
 635 \f
 636 /* Command to set cpu type.  */
 637
 638 void
 639 arc_set_cpu_type_command (char *args, int from_tty)
 640 {
 641   int i;
 642
 643   if (tmp_arc_cpu_type == NULL || *tmp_arc_cpu_type == '\0')
 644     {
 645       printf_unfiltered ("The known ARC cpu types are as follows:\n");
 646       for (i = 0; arc_cpu_type_table[i].name != NULL; ++i)
 647         printf_unfiltered ("%s\n", arc_cpu_type_table[i].name);
 648
 649       /* Restore the value.  */
 650       tmp_arc_cpu_type = xstrdup (arc_cpu_type);
 651
 652       return;
 653     }
 654
 655   if (!arc_set_cpu_type (tmp_arc_cpu_type))
 656     {
 657       error ("Unknown cpu type `%s'.", tmp_arc_cpu_type);
 658       /* Restore its value.  */
 659       tmp_arc_cpu_type = xstrdup (arc_cpu_type);
 660     }
 661 }
 662
 663 static void
 664 arc_show_cpu_type_command (char *args, int from_tty)
 665 {
 666 }
 667
 668 /* Modify the actual cpu type.
 669    Result is a boolean indicating success.  */
 670
 671 static int
 672 arc_set_cpu_type (char *str)
 673 {
 674   int i, j;
 675
 676   if (str == NULL)
 677     return 0;
 678
 679   for (i = 0; arc_cpu_type_table[i].name != NULL; ++i)
 680     {
 681       if (strcasecmp (str, arc_cpu_type_table[i].name) == 0)
 682         {
 683           arc_cpu_type = str;
 684           arc_bfd_mach_type = arc_cpu_type_table[i].value;
 685           return 1;
 686         }
 687     }
 688
 689   return 0;
 690 }
 691 \f
 692 void
 693 _initialize_arc_tdep (void)
 694 {
 695   struct cmd_list_element *c;
 696
 697   c = add_set_cmd ("cpu", class_support, var_string_noescape,
 698                    (char *) &tmp_arc_cpu_type,
 699                    "Set the type of ARC cpu in use.\n\
 700 This command has two purposes.  In a multi-cpu system it lets one\n\
 701 change the cpu being debugged.  It also gives one access to\n\
 702 cpu-type-specific registers and recognize cpu-type-specific instructions.\
 703 ",
 704                    &setlist);
 705   set_cmd_cfunc (c, arc_set_cpu_type_command);
 706   c = add_show_from_set (c, &showlist);
 707   set_cmd_cfunc (c, arc_show_cpu_type_command);
 708
 709   /* We have to use xstrdup() here because the `set' command frees it
 710      before setting a new value.  */
 711   tmp_arc_cpu_type = xstrdup (DEFAULT_ARC_CPU_TYPE);
 712   arc_set_cpu_type (tmp_arc_cpu_type);
 713
 714   c = add_set_cmd ("displaypipeline", class_support, var_zinteger,
 715                    (char *) &display_pipeline_p,
 716                    "Set pipeline display (simulator only).\n\
 717 When enabled, the state of the pipeline after each cycle is displayed.",
 718                    &setlist);
 719   c = add_show_from_set (c, &showlist);
 720
 721   c = add_set_cmd ("debugpipeline", class_support, var_zinteger,
 722                    (char *) &debug_pipeline_p,
 723                    "Set pipeline debug display (simulator only).\n\
 724 When enabled, debugging information about the pipeline is displayed.",
 725                    &setlist);
 726   c = add_show_from_set (c, &showlist);
 727
 728   c = add_set_cmd ("cputimer", class_support, var_zinteger,
 729                    (char *) &cpu_timer,
 730                    "Set maximum cycle count (simulator only).\n\
 731 Control will return to gdb if the timer expires.\n\
 732 A negative value disables the timer.",
 733                    &setlist);
 734   c = add_show_from_set (c, &showlist);
 735
 736   tm_print_insn = arc_print_insn;
 737 }