gdb/arc-tdep.h

   1 /* Target dependent code for ARC architecture, for GDB.
   2
   3    Copyright 2005-2020 Free Software Foundation, Inc.
   4    Contributed by Synopsys Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef ARC_TDEP_H
  22 #define ARC_TDEP_H
  23
  24 /* Need disassemble_info.  */
  25 #include "dis-asm.h"
  26 #include "arch/arc.h"
  27
  28 /* To simplify GDB code this enum assumes that internal regnums should be same
  29    as architectural register numbers, i.e. PCL regnum is 63.  This allows to
  30    use internal GDB regnums as architectural numbers when dealing with
  31    instruction encodings, for example when analyzing what are the registers
  32    saved in function prologue.  */
  33
  34 enum arc_regnum
  35   {
  36     /* Core registers.  */
  37     ARC_R0_REGNUM = 0,
  38     ARC_FIRST_CORE_REGNUM = ARC_R0_REGNUM,
  39     ARC_R1_REGNUM = 1,
  40     ARC_R4_REGNUM = 4,
  41     ARC_R7_REGNUM = 7,
  42     ARC_R9_REGNUM = 9,
  43     ARC_R13_REGNUM = 13,
  44     ARC_R16_REGNUM = 16,
  45     ARC_R25_REGNUM = 25,
  46     /* Global data pointer.  */
  47     ARC_GP_REGNUM,
  48     /* Frame pointer.  */
  49     ARC_FP_REGNUM,
  50     /* Stack pointer.  */
  51     ARC_SP_REGNUM,
  52     /* Return address from interrupt.  */
  53     ARC_ILINK_REGNUM,
  54     ARC_R30_REGNUM,
  55     /* Return address from function.  */
  56     ARC_BLINK_REGNUM,
  57     /* Zero-delay loop counter.  */
  58     ARC_LP_COUNT_REGNUM = 60,
  59     /* Reserved register number.  There should never be a register with such
  60        number, this name is needed only for a sanity check in
  61       arc_cannot_(fetch|store)_register.  */
  62     ARC_RESERVED_REGNUM,
  63     /* Long-immediate value.  This is not a physical register - if instruction
  64        has register 62 as an operand, then this operand is a literal value
  65        stored in the instruction memory right after the instruction itself.
  66        This value is required in this enumeration as an architectural number
  67        for instruction analysis.  */
  68     ARC_LIMM_REGNUM,
  69     /* Program counter, aligned to 4-bytes, read-only.  */
  70     ARC_PCL_REGNUM,
  71     ARC_LAST_CORE_REGNUM = ARC_PCL_REGNUM,
  72     /* AUX registers.  */
  73     /* Actual program counter.  */
  74     ARC_PC_REGNUM,
  75     ARC_FIRST_AUX_REGNUM = ARC_PC_REGNUM,
  76     /* Status register.  */
  77     ARC_STATUS32_REGNUM,
  78     ARC_LAST_REGNUM = ARC_STATUS32_REGNUM,
  79     ARC_LAST_AUX_REGNUM = ARC_STATUS32_REGNUM,
  80
  81     /* Additional ABI constants.  */
  82     ARC_FIRST_ARG_REGNUM = ARC_R0_REGNUM,
  83     ARC_LAST_ARG_REGNUM = ARC_R7_REGNUM,
  84     ARC_FIRST_CALLEE_SAVED_REGNUM = ARC_R13_REGNUM,
  85     ARC_LAST_CALLEE_SAVED_REGNUM = ARC_R25_REGNUM,
  86   };
  87
  88 /* Number of bytes in ARC register.  All ARC registers are considered 32-bit.
  89    Those registers, which are actually shorter has zero-on-read for extra bits.
  90    Longer registers are represented as pairs of 32-bit registers.  */
  91 #define ARC_REGISTER_SIZE  4
  92
  93 #define arc_print(fmt, args...) fprintf_unfiltered (gdb_stdlog, fmt, ##args)
  94
  95 extern int arc_debug;
  96
  97 /* Target-dependent information.  */
  98
  99 struct gdbarch_tdep
 100 {
 101   /* Offset to PC value in jump buffer.  If this is negative, longjmp
 102      support will be disabled.  */
 103   int jb_pc;
 104 };
 105
 106 /* Utility functions used by other ARC-specific modules.  */
 107
 108 static inline int
 109 arc_mach_is_arc600 (struct gdbarch *gdbarch)
 110 {
 111   return (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arc600
 112           || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arc601);
 113 }
 114
 115 static inline int
 116 arc_mach_is_arc700 (struct gdbarch *gdbarch)
 117 {
 118   return gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arc700;
 119 }
 120
 121 static inline int
 122 arc_mach_is_arcv2 (struct gdbarch *gdbarch)
 123 {
 124   return gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arcv2;
 125 }
 126
 127 /* ARC EM and ARC HS are unique BFD arches, however they share the same machine
 128    number as "ARCv2".  */
 129
 130 static inline bool
 131 arc_arch_is_hs (const struct bfd_arch_info* arch)
 132 {
 133   return startswith (arch->printable_name, "HS");
 134 }
 135
 136 static inline bool
 137 arc_arch_is_em (const struct bfd_arch_info* arch)
 138 {
 139   return startswith (arch->printable_name, "EM");
 140 }
 141
 142 /* Function to access ARC disassembler.  Underlying opcodes disassembler will
 143    print an instruction into stream specified in the INFO, so if it is
 144    undesired, then this stream should be set to some invisible stream, but it
 145    can't be set to an actual NULL value - that would cause a crash.  */
 146 int arc_delayed_print_insn (bfd_vma addr, struct disassemble_info *info);
 147
 148 /* Return properly initialized disassemble_info for ARC disassembler - it will
 149    not print disassembled instructions to stderr.  */
 150
 151 struct disassemble_info arc_disassemble_info (struct gdbarch *gdbarch);
 152
 153 /* Get branch/jump target address for the INSN.  Note that this function
 154    returns branch target and doesn't evaluate if this branch is taken or not.
 155    For the indirect jumps value depends in register state, hence can change.
 156    It is an error to call this function for a non-branch instruction.  */
 157
 158 CORE_ADDR arc_insn_get_branch_target (const struct arc_instruction &insn);
 159
 160 /* Get address of next instruction after INSN, assuming linear execution (no
 161    taken branches).  If instruction has a delay slot, then returned value will
 162    point at the instruction in delay slot.  That is - "address of instruction +
 163    instruction length with LIMM".  */
 164
 165 CORE_ADDR arc_insn_get_linear_next_pc (const struct arc_instruction &insn);
 166
 167 /* Get the correct ARC target description for the given system type.  */
 168 const target_desc *arc_read_description (arc_sys_type sys_type);
 169
 170 #endif /* ARC_TDEP_H */