1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988-2019 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 #include "gdbsupport/common-defs.h"
21 #include "gdbsupport/common-regcache.h"
24 extern struct target_desc
*tdesc_arm_with_vfpv2
;
25 extern struct target_desc
*tdesc_arm_with_vfpv3
;
26 extern struct target_desc
*tdesc_arm_with_iwmmxt
;
28 /* Temporary ifdef. Will be removed when target descriptions are switched. */
30 extern struct target_desc
*tdesc_arm_with_m
;
31 extern struct target_desc
*tdesc_arm_with_m_vfp_d16
;
32 extern struct target_desc
*tdesc_arm_with_m_fpa_layout
;
38 thumb_insn_size (unsigned short inst1
)
40 if ((inst1
& 0xe000) == 0xe000 && (inst1
& 0x1800) != 0)
49 bitcount (unsigned long val
)
52 for (nbits
= 0; val
!= 0; nbits
++)
53 val
&= val
- 1; /* Delete rightmost 1-bit in val. */
60 condition_true (unsigned long cond
, unsigned long status_reg
)
62 if (cond
== INST_AL
|| cond
== INST_NV
)
68 return ((status_reg
& FLAG_Z
) != 0);
70 return ((status_reg
& FLAG_Z
) == 0);
72 return ((status_reg
& FLAG_C
) != 0);
74 return ((status_reg
& FLAG_C
) == 0);
76 return ((status_reg
& FLAG_N
) != 0);
78 return ((status_reg
& FLAG_N
) == 0);
80 return ((status_reg
& FLAG_V
) != 0);
82 return ((status_reg
& FLAG_V
) == 0);
84 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
86 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
88 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
90 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
92 return (((status_reg
& FLAG_Z
) == 0)
93 && (((status_reg
& FLAG_N
) == 0)
94 == ((status_reg
& FLAG_V
) == 0)));
96 return (((status_reg
& FLAG_Z
) != 0)
97 || (((status_reg
& FLAG_N
) == 0)
98 != ((status_reg
& FLAG_V
) == 0)));
107 thumb_advance_itstate (unsigned int itstate
)
109 /* Preserve IT[7:5], the first three bits of the condition. Shift
110 the upcoming condition flags left by one bit. */
111 itstate
= (itstate
& 0xe0) | ((itstate
<< 1) & 0x1f);
113 /* If we have finished the IT block, clear the state. */
114 if ((itstate
& 0x0f) == 0)
123 arm_instruction_changes_pc (uint32_t this_instr
)
125 if (bits (this_instr
, 28, 31) == INST_NV
)
126 /* Unconditional instructions. */
127 switch (bits (this_instr
, 24, 27))
131 /* Branch with Link and change to Thumb. */
136 /* Coprocessor register transfer. */
137 if (bits (this_instr
, 12, 15) == 15)
138 error (_("Invalid update to pc in instruction"));
144 switch (bits (this_instr
, 25, 27))
147 if (bits (this_instr
, 23, 24) == 2 && bit (this_instr
, 20) == 0)
149 /* Multiplies and extra load/stores. */
150 if (bit (this_instr
, 4) == 1 && bit (this_instr
, 7) == 1)
151 /* Neither multiplies nor extension load/stores are allowed
155 /* Otherwise, miscellaneous instructions. */
157 /* BX <reg>, BXJ <reg>, BLX <reg> */
158 if (bits (this_instr
, 4, 27) == 0x12fff1
159 || bits (this_instr
, 4, 27) == 0x12fff2
160 || bits (this_instr
, 4, 27) == 0x12fff3)
163 /* Other miscellaneous instructions are unpredictable if they
167 /* Data processing instruction. */
171 if (bits (this_instr
, 12, 15) == 15)
178 /* Media instructions and architecturally undefined instructions. */
179 if (bits (this_instr
, 25, 27) == 3 && bit (this_instr
, 4) == 1)
183 if (bit (this_instr
, 20) == 0)
187 if (bits (this_instr
, 12, 15) == ARM_PC_REGNUM
)
193 /* Load/store multiple. */
194 if (bit (this_instr
, 20) == 1 && bit (this_instr
, 15) == 1)
200 /* Branch and branch with link. */
205 /* Coprocessor transfers or SWIs can not affect PC. */
209 internal_error (__FILE__
, __LINE__
, _("bad value in switch"));
216 thumb_instruction_changes_pc (unsigned short inst
)
218 if ((inst
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
221 if ((inst
& 0xf000) == 0xd000) /* conditional branch */
224 if ((inst
& 0xf800) == 0xe000) /* unconditional branch */
227 if ((inst
& 0xff00) == 0x4700) /* bx REG, blx REG */
230 if ((inst
& 0xff87) == 0x4687) /* mov pc, REG */
233 if ((inst
& 0xf500) == 0xb100) /* CBNZ or CBZ. */
243 thumb2_instruction_changes_pc (unsigned short inst1
, unsigned short inst2
)
245 if ((inst1
& 0xf800) == 0xf000 && (inst2
& 0x8000) == 0x8000)
247 /* Branches and miscellaneous control instructions. */
249 if ((inst2
& 0x1000) != 0 || (inst2
& 0xd001) == 0xc000)
254 else if (inst1
== 0xf3de && (inst2
& 0xff00) == 0x3f00)
256 /* SUBS PC, LR, #imm8. */
259 else if ((inst2
& 0xd000) == 0x8000 && (inst1
& 0x0380) != 0x0380)
261 /* Conditional branch. */
268 if ((inst1
& 0xfe50) == 0xe810)
270 /* Load multiple or RFE. */
272 if (bit (inst1
, 7) && !bit (inst1
, 8))
278 else if (!bit (inst1
, 7) && bit (inst1
, 8))
284 else if (bit (inst1
, 7) && bit (inst1
, 8))
289 else if (!bit (inst1
, 7) && !bit (inst1
, 8))
298 if ((inst1
& 0xffef) == 0xea4f && (inst2
& 0xfff0) == 0x0f00)
300 /* MOV PC or MOVS PC. */
304 if ((inst1
& 0xff70) == 0xf850 && (inst2
& 0xf000) == 0xf000)
307 if (bits (inst1
, 0, 3) == 15)
313 if ((inst2
& 0x0fc0) == 0x0000)
319 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf000)
325 if ((inst1
& 0xfff0) == 0xe8d0 && (inst2
& 0xfff0) == 0xf010)
337 shifted_reg_val (struct regcache
*regcache
, unsigned long inst
,
338 int carry
, unsigned long pc_val
, unsigned long status_reg
)
340 unsigned long res
, shift
;
341 int rm
= bits (inst
, 0, 3);
342 unsigned long shifttype
= bits (inst
, 5, 6);
346 int rs
= bits (inst
, 8, 11);
349 : regcache_raw_get_unsigned (regcache
, rs
)) & 0xFF;
352 shift
= bits (inst
, 7, 11);
354 res
= (rm
== ARM_PC_REGNUM
355 ? (pc_val
+ (bit (inst
, 4) ? 12 : 8))
356 : regcache_raw_get_unsigned (regcache
, rm
));
361 res
= shift
>= 32 ? 0 : res
<< shift
;
365 res
= shift
>= 32 ? 0 : res
>> shift
;
371 res
= ((res
& 0x80000000L
)
372 ? ~((~res
) >> shift
) : res
>> shift
);
375 case 3: /* ROR/RRX */
378 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
380 res
= (res
>> shift
) | (res
<< (32 - shift
));
384 return res
& 0xffffffff;
387 /* See arch/arm.h. */
390 arm_create_target_description (arm_fp_type fp_type
)
394 case ARM_FP_TYPE_NONE
:
396 /* Temporary ifdef. Will be removed when target descriptions are switched. */
398 case ARM_FP_TYPE_VFPV2
:
399 return tdesc_arm_with_vfpv2
;
401 case ARM_FP_TYPE_VFPV3
:
402 return tdesc_arm_with_vfpv3
;
404 case ARM_FP_TYPE_IWMMXT
:
405 return tdesc_arm_with_iwmmxt
;
408 error (_("Invalid Arm FP type: %d"), fp_type
);
412 /* See arch/arm.h. */
415 arm_create_mprofile_target_description (arm_m_profile_type m_type
)
419 /* Temporary ifdef. Will be removed when target descriptions are switched. */
421 case ARM_M_TYPE_M_PROFILE
:
422 return tdesc_arm_with_m
;
424 case ARM_M_TYPE_VFP_D16
:
425 return tdesc_arm_with_m_fpa_layout
;
427 case ARM_M_TYPE_WITH_FPA
:
428 return tdesc_arm_with_m_vfp_d16
;
431 error (_("Invalid Arm M type: %d"), m_type
);