gdb/arch/arm.c

   1 /* Common target dependent code for GDB on ARM systems.
   2
   3    Copyright (C) 1988-2019 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "gdbsupport/common-defs.h"
  21 #include "gdbsupport/common-regcache.h"
  22 #include "arm.h"
  23
  24 extern struct target_desc *tdesc_arm_with_vfpv2;
  25 extern struct target_desc *tdesc_arm_with_vfpv3;
  26 extern struct target_desc *tdesc_arm_with_iwmmxt;
  27
  28 /* Temporary ifdef.  Will be removed when target descriptions are switched.  */
  29 #ifndef GDBSERVER
  30 extern struct target_desc *tdesc_arm_with_m;
  31 extern struct target_desc *tdesc_arm_with_m_vfp_d16;
  32 extern struct target_desc *tdesc_arm_with_m_fpa_layout;
  33 #endif
  34
  35 /* See arm.h.  */
  36
  37 int
  38 thumb_insn_size (unsigned short inst1)
  39 {
  40   if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
  41     return 4;
  42   else
  43     return 2;
  44 }
  45
  46 /* See arm.h.  */
  47
  48 int
  49 bitcount (unsigned long val)
  50 {
  51   int nbits;
  52   for (nbits = 0; val != 0; nbits++)
  53     val &= val - 1;             /* Delete rightmost 1-bit in val.  */
  54   return nbits;
  55 }
  56
  57 /* See arm.h.  */
  58
  59 int
  60 condition_true (unsigned long cond, unsigned long status_reg)
  61 {
  62   if (cond == INST_AL || cond == INST_NV)
  63     return 1;
  64
  65   switch (cond)
  66     {
  67     case INST_EQ:
  68       return ((status_reg & FLAG_Z) != 0);
  69     case INST_NE:
  70       return ((status_reg & FLAG_Z) == 0);
  71     case INST_CS:
  72       return ((status_reg & FLAG_C) != 0);
  73     case INST_CC:
  74       return ((status_reg & FLAG_C) == 0);
  75     case INST_MI:
  76       return ((status_reg & FLAG_N) != 0);
  77     case INST_PL:
  78       return ((status_reg & FLAG_N) == 0);
  79     case INST_VS:
  80       return ((status_reg & FLAG_V) != 0);
  81     case INST_VC:
  82       return ((status_reg & FLAG_V) == 0);
  83     case INST_HI:
  84       return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
  85     case INST_LS:
  86       return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
  87     case INST_GE:
  88       return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
  89     case INST_LT:
  90       return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
  91     case INST_GT:
  92       return (((status_reg & FLAG_Z) == 0)
  93               && (((status_reg & FLAG_N) == 0)
  94                   == ((status_reg & FLAG_V) == 0)));
  95     case INST_LE:
  96       return (((status_reg & FLAG_Z) != 0)
  97               || (((status_reg & FLAG_N) == 0)
  98                   != ((status_reg & FLAG_V) == 0)));
  99     }
 100   return 1;
 101 }
 102
 103
 104 /* See arm.h.  */
 105
 106 int
 107 thumb_advance_itstate (unsigned int itstate)
 108 {
 109   /* Preserve IT[7:5], the first three bits of the condition.  Shift
 110      the upcoming condition flags left by one bit.  */
 111   itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f);
 112
 113   /* If we have finished the IT block, clear the state.  */
 114   if ((itstate & 0x0f) == 0)
 115     itstate = 0;
 116
 117   return itstate;
 118 }
 119
 120 /* See arm.h.  */
 121
 122 int
 123 arm_instruction_changes_pc (uint32_t this_instr)
 124 {
 125   if (bits (this_instr, 28, 31) == INST_NV)
 126     /* Unconditional instructions.  */
 127     switch (bits (this_instr, 24, 27))
 128       {
 129       case 0xa:
 130       case 0xb:
 131         /* Branch with Link and change to Thumb.  */
 132         return 1;
 133       case 0xc:
 134       case 0xd:
 135       case 0xe:
 136         /* Coprocessor register transfer.  */
 137         if (bits (this_instr, 12, 15) == 15)
 138           error (_("Invalid update to pc in instruction"));
 139         return 0;
 140       default:
 141         return 0;
 142       }
 143   else
 144     switch (bits (this_instr, 25, 27))
 145       {
 146       case 0x0:
 147         if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0)
 148           {
 149             /* Multiplies and extra load/stores.  */
 150             if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1)
 151               /* Neither multiplies nor extension load/stores are allowed
 152                  to modify PC.  */
 153               return 0;
 154
 155             /* Otherwise, miscellaneous instructions.  */
 156
 157             /* BX <reg>, BXJ <reg>, BLX <reg> */
 158             if (bits (this_instr, 4, 27) == 0x12fff1
 159                 || bits (this_instr, 4, 27) == 0x12fff2
 160                 || bits (this_instr, 4, 27) == 0x12fff3)
 161               return 1;
 162
 163             /* Other miscellaneous instructions are unpredictable if they
 164                modify PC.  */
 165             return 0;
 166           }
 167         /* Data processing instruction.  */
 168         /* Fall through.  */
 169
 170       case 0x1:
 171         if (bits (this_instr, 12, 15) == 15)
 172           return 1;
 173         else
 174           return 0;
 175
 176       case 0x2:
 177       case 0x3:
 178         /* Media instructions and architecturally undefined instructions.  */
 179         if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1)
 180           return 0;
 181
 182         /* Stores.  */
 183         if (bit (this_instr, 20) == 0)
 184           return 0;
 185
 186         /* Loads.  */
 187         if (bits (this_instr, 12, 15) == ARM_PC_REGNUM)
 188           return 1;
 189         else
 190           return 0;
 191
 192       case 0x4:
 193         /* Load/store multiple.  */
 194         if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1)
 195           return 1;
 196         else
 197           return 0;
 198
 199       case 0x5:
 200         /* Branch and branch with link.  */
 201         return 1;
 202
 203       case 0x6:
 204       case 0x7:
 205         /* Coprocessor transfers or SWIs can not affect PC.  */
 206         return 0;
 207
 208       default:
 209         internal_error (__FILE__, __LINE__, _("bad value in switch"));
 210       }
 211 }
 212
 213 /* See arm.h.  */
 214
 215 int
 216 thumb_instruction_changes_pc (unsigned short inst)
 217 {
 218   if ((inst & 0xff00) == 0xbd00)        /* pop {rlist, pc} */
 219     return 1;
 220
 221   if ((inst & 0xf000) == 0xd000)        /* conditional branch */
 222     return 1;
 223
 224   if ((inst & 0xf800) == 0xe000)        /* unconditional branch */
 225     return 1;
 226
 227   if ((inst & 0xff00) == 0x4700)        /* bx REG, blx REG */
 228     return 1;
 229
 230   if ((inst & 0xff87) == 0x4687)        /* mov pc, REG */
 231     return 1;
 232
 233   if ((inst & 0xf500) == 0xb100)        /* CBNZ or CBZ.  */
 234     return 1;
 235
 236   return 0;
 237 }
 238
 239
 240 /* See arm.h.  */
 241
 242 int
 243 thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
 244 {
 245   if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
 246     {
 247       /* Branches and miscellaneous control instructions.  */
 248
 249       if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
 250         {
 251           /* B, BL, BLX.  */
 252           return 1;
 253         }
 254       else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
 255         {
 256           /* SUBS PC, LR, #imm8.  */
 257           return 1;
 258         }
 259       else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
 260         {
 261           /* Conditional branch.  */
 262           return 1;
 263         }
 264
 265       return 0;
 266     }
 267
 268   if ((inst1 & 0xfe50) == 0xe810)
 269     {
 270       /* Load multiple or RFE.  */
 271
 272       if (bit (inst1, 7) && !bit (inst1, 8))
 273         {
 274           /* LDMIA or POP */
 275           if (bit (inst2, 15))
 276             return 1;
 277         }
 278       else if (!bit (inst1, 7) && bit (inst1, 8))
 279         {
 280           /* LDMDB */
 281           if (bit (inst2, 15))
 282             return 1;
 283         }
 284       else if (bit (inst1, 7) && bit (inst1, 8))
 285         {
 286           /* RFEIA */
 287           return 1;
 288         }
 289       else if (!bit (inst1, 7) && !bit (inst1, 8))
 290         {
 291           /* RFEDB */
 292           return 1;
 293         }
 294
 295       return 0;
 296     }
 297
 298   if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
 299     {
 300       /* MOV PC or MOVS PC.  */
 301       return 1;
 302     }
 303
 304   if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
 305     {
 306       /* LDR PC.  */
 307       if (bits (inst1, 0, 3) == 15)
 308         return 1;
 309       if (bit (inst1, 7))
 310         return 1;
 311       if (bit (inst2, 11))
 312         return 1;
 313       if ((inst2 & 0x0fc0) == 0x0000)
 314         return 1;
 315
 316       return 0;
 317     }
 318
 319   if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
 320     {
 321       /* TBB.  */
 322       return 1;
 323     }
 324
 325   if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
 326     {
 327       /* TBH.  */
 328       return 1;
 329     }
 330
 331   return 0;
 332 }
 333
 334 /* See arm.h.  */
 335
 336 unsigned long
 337 shifted_reg_val (struct regcache *regcache, unsigned long inst,
 338                  int carry, unsigned long pc_val, unsigned long status_reg)
 339 {
 340   unsigned long res, shift;
 341   int rm = bits (inst, 0, 3);
 342   unsigned long shifttype = bits (inst, 5, 6);
 343
 344   if (bit (inst, 4))
 345     {
 346       int rs = bits (inst, 8, 11);
 347       shift = (rs == 15
 348                ? pc_val + 8
 349                : regcache_raw_get_unsigned (regcache, rs)) & 0xFF;
 350     }
 351   else
 352     shift = bits (inst, 7, 11);
 353
 354   res = (rm == ARM_PC_REGNUM
 355          ? (pc_val + (bit (inst, 4) ? 12 : 8))
 356          : regcache_raw_get_unsigned (regcache, rm));
 357
 358   switch (shifttype)
 359     {
 360     case 0:                     /* LSL */
 361       res = shift >= 32 ? 0 : res << shift;
 362       break;
 363
 364     case 1:                     /* LSR */
 365       res = shift >= 32 ? 0 : res >> shift;
 366       break;
 367
 368     case 2:                     /* ASR */
 369       if (shift >= 32)
 370         shift = 31;
 371       res = ((res & 0x80000000L)
 372              ? ~((~res) >> shift) : res >> shift);
 373       break;
 374
 375     case 3:                     /* ROR/RRX */
 376       shift &= 31;
 377       if (shift == 0)
 378         res = (res >> 1) | (carry ? 0x80000000L : 0);
 379       else
 380         res = (res >> shift) | (res << (32 - shift));
 381       break;
 382     }
 383
 384   return res & 0xffffffff;
 385 }
 386
 387 /* See arch/arm.h.  */
 388
 389 target_desc *
 390 arm_create_target_description (arm_fp_type fp_type)
 391 {
 392   switch (fp_type)
 393     {
 394     case ARM_FP_TYPE_NONE:
 395       return nullptr;
 396 /* Temporary ifdef.  Will be removed when target descriptions are switched.  */
 397 #ifndef GDBSERVER
 398     case ARM_FP_TYPE_VFPV2:
 399       return tdesc_arm_with_vfpv2;
 400
 401     case ARM_FP_TYPE_VFPV3:
 402       return tdesc_arm_with_vfpv3;
 403
 404     case ARM_FP_TYPE_IWMMXT:
 405       return tdesc_arm_with_iwmmxt;
 406 #endif
 407     default:
 408       error (_("Invalid Arm FP type: %d"), fp_type);
 409     }
 410 }
 411
 412 /* See arch/arm.h.  */
 413
 414 target_desc *
 415 arm_create_mprofile_target_description (arm_m_profile_type m_type)
 416 {
 417   switch (m_type)
 418     {
 419 /* Temporary ifdef.  Will be removed when target descriptions are switched.  */
 420 #ifndef GDBSERVER
 421     case ARM_M_TYPE_M_PROFILE:
 422       return tdesc_arm_with_m;
 423
 424     case ARM_M_TYPE_VFP_D16:
 425       return tdesc_arm_with_m_fpa_layout;
 426
 427     case ARM_M_TYPE_WITH_FPA:
 428       return tdesc_arm_with_m_vfp_d16;
 429 #endif
 430     default:
 431       error (_("Invalid Arm M type: %d"), m_type);
 432     }
 433 }
 434