1 /* Print Acorn Risc Machine instructions for GDB, the GNU debugger.
2 Copyright 1986, 1989, 1991 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
26 #include "arm-opcode.h"
28 extern char *reg_names
[];
30 static char *shift_names
[] = {
31 "lsl", "lsr", "asr", "ror",
34 static char *cond_names
[] = {
35 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
36 "hi", "ls", "ge", "lt", "gt", "le", "", "nv"
39 static char float_precision
[] = "sdep";
40 static char float_rounding
[] = " pmz";
41 static float float_immed
[] = { 0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 0.5, 10.0 };
43 static void print_ldr_str_offset();
44 static void print_ldc_stc_offset();
45 static long immediate_value();
47 /* Print the ARM instruction at address MEMADDR in debugged memory,
48 on STREAM. Returns length of the instruction, in bytes. */
51 print_insn (memaddr
, stream
)
56 register struct opcode
*op
;
61 ins
= read_memory_integer(memaddr
, 4);
62 for (i
= 0, op
= opcodes
; i
< N_OPCODES
; i
++, op
++)
63 if ((ins
& op
->mask
) == op
->value
) break;
64 assert(i
!= N_OPCODES
);
66 for (p
= op
->assembler
; *p
;) {
71 s
= s
*10 + (*p
++ - '0');
75 e
= e
*10 + (*p
++ - '0');
78 assert(s
>= 0 && s
<= 31 && e
>= 0 && e
<= 31);
79 val
= (ins
>> s
) & ((1 << (e
+ 1 - s
)) - 1);
85 fprintf(stream
, "%d", val
);
88 fprintf(stream
, "%x", val
);
91 assert(val
>= 0 && val
<= 15);
92 fprintf(stream
, "%s", reg_names
[val
]);
95 fprintf(stream
, "%s", cond_names
[ins
>> 28]);
120 if (((ins
>> 12) & 0xf) == 0xf)
125 int immed
= immediate_value(ins
& 0xfff);
126 fprintf (stream
, "#%d (0x%x)", immed
, immed
);
128 int operand2
= ins
& 0xfff;
130 bits 0-3 are the base register
131 bits 5-6 are the shift (0=lsl, 1=lsr, 2=asr, 3=ror)
132 if bit 4 is zero then bits 7-11 are an immediate shift count
133 else bit 7 must be zero and bits 8-11 are the register
134 to be used as a shift count.
135 Note: no shift at all is encoded as "reg lsl #0" */
136 fprintf (stream
, "%s", reg_names
[operand2
& 0xf]);
137 if (operand2
& 0xff0) {
138 /* ror #0 is really rrx (rotate right extend) */
139 if ((operand2
& 0xff0) == 0x060)
140 fprintf (stream
, ", rrx");
142 fprintf (stream
, ", %s ",
143 shift_names
[(operand2
>> 5) & 3]);
144 if (operand2
& (1<<4)) /* register shift */
145 fprintf (stream
, "%s",
146 reg_names
[operand2
>> 8]);
147 else /* immediate shift */
148 fprintf (stream
, "#%d",
155 fprintf (stream
, "[%s", reg_names
[(ins
>> 16) & 0xf]);
157 fprintf (stream
, ", ");
158 print_ldr_str_offset (ins
, stream
);
160 if (ins
& (1<<21)) putc('!', stream
);
161 /* If it is a pc relative load, then it is probably
162 a constant so print it */
163 if (((ins
>> 16) & 0xf) == 15 &&
164 (ins
& (1<<25)) == 0 &&
166 int addr
= memaddr
+ 8 +
167 (ins
& 0xfff) * ((ins
& (1<<23)) ? 1 : -1);
168 fprintf (stream
, " (contents=");
169 print_address (read_memory_integer(addr
, 4), stream
);
170 fprintf (stream
, ")");
173 fprintf (stream
, "]," );
174 print_ldr_str_offset (ins
, stream
);
178 print_address (memaddr
+ 8 + (((int)ins
<< 8) >> 6), stream
);
181 fprintf (stream
, "[%s", reg_names
[(ins
>> 16) & 0xf]);
183 fprintf (stream
, ", ");
184 print_ldc_stc_offset (ins
, stream
);
189 fprintf (stream
, "], ");
190 print_ldc_stc_offset (ins
, stream
);
195 int regnum
, first
= 1;
197 for (regnum
= 0; regnum
< 16; regnum
++)
198 if (ins
& (1<<regnum
)) {
202 fprintf (stream
, "%s", reg_names
[regnum
]);
208 val
= ((ins
>> 18) & 2) | ((ins
>> 7) & 1);
209 putc(float_precision
[val
], stream
);
212 val
= ((ins
>> 21) & 2) | ((ins
>> 15) & 1);
213 putc(float_precision
[val
], stream
);
216 val
= ((ins
>> 5) & 3);
217 if (val
) putc(float_rounding
[val
], stream
);
220 assert(val
>= 0 && val
<= 15);
222 fprintf (stream
, "#%3.1f", float_immed
[val
- 8]);
224 fprintf (stream
, "f%d", val
);
236 immediate_value(operand
)
239 int val
= operand
& 0xff;
240 int shift
= 2*(operand
>> 8);
241 /* immediate value is (val ror shift) */
242 return (val
>> shift
) | (val
<< (32 - shift
));
246 print_ldr_str_offset(ins
, stream
)
250 if ((ins
& (1<<25)) == 0)
251 fprintf (stream
, "#%d",
252 (ins
& 0xfff) * ((ins
& (1<<23)) ? 1 : -1));
254 fprintf (stream
, "%s%s", reg_names
[ins
& 0xf],
255 (ins
& (1<<23)) ? "" : "-");
257 fprintf (stream
, ", %s #%d",
258 shift_names
[(ins
>> 5) & 3],
264 print_ldc_stc_offset(ins
, stream
)
268 fprintf (stream
, "#%d",
269 4 * (ins
& 0xff) * ((ins
& (1<<23)) ? 1 : -1));
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